piixpcib.c revision 1.23
1 /* $NetBSD: piixpcib.c,v 1.23 2019/10/18 01:00:25 manu Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto, Matthew R. Green, and Jared D. McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel PIIX4 PCI-ISA bridge device driver with CPU frequency scaling support 34 * 35 * Based on the FreeBSD 'smist' cpufreq driver by Bruno Ducrot 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: piixpcib.c,v 1.23 2019/10/18 01:00:25 manu Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/sysctl.h> 46 #include <sys/bus.h> 47 48 #include <machine/frame.h> 49 #include <machine/bioscall.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 55 #include <i386/pci/piixreg.h> 56 #include <x86/pci/pcibvar.h> 57 58 #define PIIX4_PIRQRC 0x60 59 60 struct piixpcib_softc { 61 /* we call pcibattach() which assumes our softc starts like this: */ 62 63 struct pcib_softc sc_pcib; 64 65 device_t sc_dev; 66 67 int sc_smi_cmd; 68 int sc_smi_data; 69 int sc_command; 70 int sc_flags; 71 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_ioh; 74 75 pcireg_t sc_pirqrc; 76 uint8_t sc_elcr[2]; 77 }; 78 79 static int piixpcibmatch(device_t, cfdata_t, void *); 80 static void piixpcibattach(device_t, device_t, void *); 81 82 static bool piixpcib_suspend(device_t, const pmf_qual_t *); 83 static bool piixpcib_resume(device_t, const pmf_qual_t *); 84 85 static void speedstep_configure(struct piixpcib_softc *, 86 const struct pci_attach_args *); 87 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 88 89 static struct piixpcib_softc *speedstep_cookie; /* XXX */ 90 91 CFATTACH_DECL_NEW(piixpcib, sizeof(struct piixpcib_softc), 92 piixpcibmatch, piixpcibattach, NULL, NULL); 93 94 /* 95 * Autoconf callbacks. 96 */ 97 static int 98 piixpcibmatch(device_t parent, cfdata_t match, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 102 /* We are ISA bridge, of course */ 103 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 104 (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA && 105 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_MISC)) { 106 return 0; 107 } 108 109 /* Matches only Intel PIIX4 */ 110 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 111 switch (PCI_PRODUCT(pa->pa_id)) { 112 case PCI_PRODUCT_INTEL_82371AB_ISA: /* PIIX4 */ 113 case PCI_PRODUCT_INTEL_82440MX_PMC: /* PIIX4 in MX440 */ 114 return 10; 115 } 116 } 117 118 return 0; 119 } 120 121 static void 122 piixpcibattach(device_t parent, device_t self, void *aux) 123 { 124 struct pci_attach_args *pa = aux; 125 struct piixpcib_softc *sc = device_private(self); 126 127 sc->sc_dev = self; 128 sc->sc_iot = pa->pa_iot; 129 130 pcibattach(parent, self, aux); 131 132 /* Set up SpeedStep. */ 133 speedstep_configure(sc, pa); 134 135 /* Map edge/level control registers */ 136 if (bus_space_map(sc->sc_iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 137 &sc->sc_ioh)) { 138 aprint_error_dev(self, 139 "can't map edge/level control registers\n"); 140 return; 141 } 142 143 if (!pmf_device_register(self, piixpcib_suspend, piixpcib_resume)) 144 aprint_error_dev(self, "couldn't establish power handler\n"); 145 } 146 147 static bool 148 piixpcib_suspend(device_t dv, const pmf_qual_t *qual) 149 { 150 struct piixpcib_softc *sc = device_private(dv); 151 152 /* capture PIRQX route control registers */ 153 sc->sc_pirqrc = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 154 PIIX4_PIRQRC); 155 156 /* capture edge/level control registers */ 157 sc->sc_elcr[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0); 158 sc->sc_elcr[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 1); 159 160 return true; 161 } 162 163 static bool 164 piixpcib_resume(device_t dv, const pmf_qual_t *qual) 165 { 166 struct piixpcib_softc *sc = device_private(dv); 167 168 /* restore PIRQX route control registers */ 169 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, PIIX4_PIRQRC, 170 sc->sc_pirqrc); 171 172 /* restore edge/level control registers */ 173 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, sc->sc_elcr[0]); 174 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1, sc->sc_elcr[1]); 175 176 return true; 177 } 178 179 /* 180 * Intel PIIX4 (SMI) SpeedStep support. 181 */ 182 183 #define PIIXPCIB_GSIC 0x47534943 184 #define PIIXPCIB_GETOWNER 0 185 #define PIIXPCIB_GETSTATE 1 186 #define PIIXPCIB_SETSTATE 2 187 #define PIIXPCIB_GETFREQS 4 188 189 #define PIIXPCIB_SPEEDSTEP_HIGH 0 190 #define PIIXPCIB_SPEEDSTEP_LOW 1 191 192 static void 193 piixpcib_int15_gsic_call(int *sig, int *smicmd, int *cmd, int *smidata, 194 int *flags) 195 { 196 struct bioscallregs regs; 197 198 /* No bioscall with EFI */ 199 if (lookup_bootinfo(BTINFO_EFI) != NULL) { 200 *sig = *smicmd = *cmd = *smidata = *flags = -1; 201 return; 202 } 203 204 memset(®s, 0, sizeof(struct bioscallregs)); 205 regs.EAX = 0x0000e980; /* IST support */ 206 regs.EDX = PIIXPCIB_GSIC; 207 bioscall(0x15, ®s); 208 209 if (regs.EAX == PIIXPCIB_GSIC) { 210 *sig = regs.EAX; 211 *smicmd = regs.EBX & 0xff; 212 *cmd = (regs.EBX >> 16) & 0xff; 213 *smidata = regs.ECX; 214 *flags = regs.EDX; 215 } else 216 *sig = *smicmd = *cmd = *smidata = *flags = -1; 217 218 return; 219 } 220 221 static int 222 piixpcib_set_ownership(struct piixpcib_softc *sc) 223 { 224 int rv; 225 u_long pmagic; 226 static char magic[] = "Copyright (c) 1999 Intel Corporation"; 227 228 pmagic = vtophys((vaddr_t)magic); 229 230 __asm__ __volatile__( 231 "movl $0, %%edi\n\t" 232 "out %%al, (%%dx)\n" 233 : "=D" (rv) 234 : "a" (sc->sc_command), 235 "b" (0), 236 "c" (0), 237 "d" (sc->sc_smi_cmd), 238 "S" (pmagic) 239 ); 240 241 return (rv ? ENXIO : 0); 242 } 243 244 static int 245 piixpcib_getset_state(struct piixpcib_softc *sc, int *state, int function) 246 { 247 int new; 248 int rv; 249 int eax; 250 251 #ifdef DIAGNOSTIC 252 if (function != PIIXPCIB_GETSTATE && 253 function != PIIXPCIB_SETSTATE) { 254 aprint_error_dev(sc->sc_dev, 255 "GSI called with invalid function %d\n", function); 256 return EINVAL; 257 } 258 #endif 259 260 __asm__ __volatile__( 261 "movl $0, %%edi\n\t" 262 "out %%al, (%%dx)\n" 263 : "=a" (eax), 264 "=b" (new), 265 "=D" (rv) 266 : "a" (sc->sc_command), 267 "b" (function), 268 "c" (*state), 269 "d" (sc->sc_smi_cmd), 270 "S" (0) 271 ); 272 273 *state = new & 1; 274 275 switch (function) { 276 case PIIXPCIB_GETSTATE: 277 if (eax) 278 return ENXIO; 279 break; 280 case PIIXPCIB_SETSTATE: 281 if (rv) 282 return ENXIO; 283 break; 284 } 285 286 return 0; 287 } 288 289 static int 290 piixpcib_get(struct piixpcib_softc *sc) 291 { 292 int rv; 293 int state; 294 295 state = 0; /* XXX gcc */ 296 297 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_GETSTATE); 298 if (rv) 299 return rv; 300 301 return state & 1; 302 } 303 304 static int 305 piixpcib_set(struct piixpcib_softc *sc, int state) 306 { 307 int rv, s; 308 int try; 309 310 if (state != PIIXPCIB_SPEEDSTEP_HIGH && 311 state != PIIXPCIB_SPEEDSTEP_LOW) 312 return ENXIO; 313 if (piixpcib_get(sc) == state) 314 return 0; 315 316 try = 5; 317 318 s = splhigh(); 319 320 do { 321 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_SETSTATE); 322 if (rv) 323 delay(200); 324 } while (rv && --try); 325 326 splx(s); 327 328 return rv; 329 } 330 331 static void 332 speedstep_configure(struct piixpcib_softc *sc, 333 const struct pci_attach_args *pa) 334 { 335 const struct sysctlnode *node, *ssnode; 336 int sig, smicmd, cmd, smidata, flags; 337 int rv; 338 339 piixpcib_int15_gsic_call(&sig, &smicmd, &cmd, &smidata, &flags); 340 341 if (sig != -1) { 342 sc->sc_smi_cmd = smicmd; 343 sc->sc_smi_data = smidata; 344 if (cmd == 0x80) { 345 aprint_debug_dev(sc->sc_dev, 346 "GSIC returned cmd 0x80, should be 0x82\n"); 347 cmd = 0x82; 348 } 349 sc->sc_command = (sig & 0xffffff00) | (cmd & 0xff); 350 sc->sc_flags = flags; 351 } else { 352 /* setup some defaults */ 353 sc->sc_smi_cmd = 0xb2; 354 sc->sc_smi_data = 0xb3; 355 sc->sc_command = 0x47534982; 356 sc->sc_flags = 0; 357 } 358 359 if (piixpcib_set_ownership(sc) != 0) { 360 aprint_error_dev(sc->sc_dev, 361 "unable to claim ownership from the BIOS\n"); 362 return; /* If we can't claim ownership from the BIOS, bail */ 363 } 364 365 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 366 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 367 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 368 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 369 goto err; 370 371 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 372 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 373 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 374 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 375 CTL_EOL)) != 0) 376 goto err; 377 378 /* XXX save the sc for IO tag/handle */ 379 speedstep_cookie = sc; 380 381 aprint_verbose_dev(sc->sc_dev, "SpeedStep SMI enabled\n"); 382 return; 383 384 err: 385 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 386 } 387 388 /* 389 * get/set the SpeedStep state: 0 == low power, 1 == high power. 390 */ 391 static int 392 speedstep_sysctl_helper(SYSCTLFN_ARGS) 393 { 394 struct sysctlnode node; 395 struct piixpcib_softc *sc; 396 uint8_t state, state2; 397 int ostate, nstate, error; 398 399 sc = speedstep_cookie; 400 error = 0; 401 402 state = piixpcib_get(sc); 403 if (state == PIIXPCIB_SPEEDSTEP_HIGH) 404 ostate = 1; 405 else 406 ostate = 0; 407 nstate = ostate; 408 409 node = *rnode; 410 node.sysctl_data = &nstate; 411 412 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 413 if (error || newp == NULL) 414 goto out; 415 416 /* Only two states are available */ 417 if (nstate != 0 && nstate != 1) { 418 error = EINVAL; 419 goto out; 420 } 421 422 state2 = piixpcib_get(sc); 423 if (state2 == PIIXPCIB_SPEEDSTEP_HIGH) 424 ostate = 1; 425 else 426 ostate = 0; 427 428 if (ostate != nstate) 429 { 430 if (nstate == 0) 431 state2 = PIIXPCIB_SPEEDSTEP_LOW; 432 else 433 state2 = PIIXPCIB_SPEEDSTEP_HIGH; 434 435 error = piixpcib_set(sc, state2); 436 } 437 out: 438 return (error); 439 } 440
Indexes created Fri Sep 26 08:10:20 GMT 2025