piixpcib.c revision 1.7
1 /* $NetBSD: piixpcib.c,v 1.7 2006/06/22 16:24:34 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto, Matthew R. Green, and Jared D. McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Intel PIIX4 PCI-ISA bridge device driver with CPU frequency scaling support 41 * 42 * Based on the FreeBSD 'smist' cpufreq driver by Bruno Ducrot 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: piixpcib.c,v 1.7 2006/06/22 16:24:34 jmcneill Exp $"); 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/sysctl.h> 53 #include <machine/bus.h> 54 55 #include <machine/frame.h> 56 #include <machine/bioscall.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <i386/pci/piixreg.h> 63 64 #define PIIX4_PIRQRC 0x60 65 66 struct piixpcib_softc { 67 struct device sc_dev; 68 69 pci_chipset_tag_t sc_pc; 70 pcitag_t sc_pcitag; 71 72 int sc_smi_cmd; 73 int sc_smi_data; 74 int sc_command; 75 int sc_flags; 76 77 bus_space_tag_t sc_iot; 78 bus_space_handle_t sc_ioh; 79 80 void *sc_powerhook; 81 struct pci_conf_state sc_pciconf; 82 83 pcireg_t sc_pirqrc; 84 uint8_t sc_elcr[2]; 85 }; 86 87 static int piixpcibmatch(struct device *, struct cfdata *, void *); 88 static void piixpcibattach(struct device *, struct device *, void *); 89 90 static void piixpcib_powerhook(int, void *); 91 92 static void speedstep_configure(struct piixpcib_softc *, 93 struct pci_attach_args *); 94 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 95 96 struct piixpcib_softc *speedstep_cookie; /* XXX */ 97 98 /* Defined in arch/i386/pci/pcib.c. */ 99 extern void pcibattach(struct device *, struct device *, void *); 100 101 CFATTACH_DECL(piixpcib, sizeof(struct piixpcib_softc), 102 piixpcibmatch, piixpcibattach, NULL, NULL); 103 104 /* 105 * Autoconf callbacks. 106 */ 107 static int 108 piixpcibmatch(struct device *parent, struct cfdata *match, void *aux) 109 { 110 struct pci_attach_args *pa; 111 112 pa = (struct pci_attach_args *)aux; 113 114 /* We are ISA bridge, of course */ 115 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 116 (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA && 117 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_MISC)) { 118 return 0; 119 } 120 121 /* Matches only Intel PIIX4 */ 122 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 123 switch (PCI_PRODUCT(pa->pa_id)) { 124 case PCI_PRODUCT_INTEL_82371AB_ISA: /* PIIX4 */ 125 case PCI_PRODUCT_INTEL_82440MX_PMC: /* PIIX4 in MX440 */ 126 return 10; 127 } 128 } 129 130 return 0; 131 } 132 133 static void 134 piixpcibattach(struct device *parent, struct device *self, void *aux) 135 { 136 struct pci_attach_args *pa; 137 struct piixpcib_softc *sc; 138 139 pa = (struct pci_attach_args *)aux; 140 sc = (struct piixpcib_softc *)self; 141 142 sc->sc_pc = pa->pa_pc; 143 sc->sc_pcitag = pa->pa_tag; 144 sc->sc_iot = pa->pa_iot; 145 146 pcibattach(parent, self, aux); 147 148 /* Set up SpeedStep. */ 149 speedstep_configure(sc, pa); 150 151 /* Map edge/level control registers */ 152 if (bus_space_map(sc->sc_iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 153 &sc->sc_ioh)) { 154 aprint_error("%s: can't map edge/level control registers\n", 155 sc->sc_dev.dv_xname); 156 return; 157 } 158 159 sc->sc_powerhook = powerhook_establish(piixpcib_powerhook, sc); 160 if (sc->sc_powerhook == NULL) 161 aprint_error("%s: can't establish powerhook\n", 162 sc->sc_dev.dv_xname); 163 164 return; 165 } 166 167 static void 168 piixpcib_powerhook(int why, void *opaque) 169 { 170 struct piixpcib_softc *sc; 171 pci_chipset_tag_t pc; 172 pcitag_t tag; 173 174 sc = (struct piixpcib_softc *)opaque; 175 pc = sc->sc_pc; 176 tag = sc->sc_pcitag; 177 178 switch (why) { 179 case PWR_SUSPEND: 180 pci_conf_capture(pc, tag, &sc->sc_pciconf); 181 182 /* capture PIRQX route control registers */ 183 sc->sc_pirqrc = pci_conf_read(pc, tag, PIIX4_PIRQRC); 184 185 /* capture edge/level control registers */ 186 sc->sc_elcr[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0); 187 sc->sc_elcr[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 1); 188 break; 189 case PWR_RESUME: 190 pci_conf_restore(pc, tag, &sc->sc_pciconf); 191 192 /* restore PIRQX route control registers */ 193 pci_conf_write(pc, tag, PIIX4_PIRQRC, sc->sc_pirqrc); 194 195 /* restore edge/level control registers */ 196 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, sc->sc_elcr[0]); 197 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1, sc->sc_elcr[1]); 198 break; 199 } 200 201 return; 202 } 203 204 /* 205 * Intel PIIX4 (SMI) SpeedStep support. 206 */ 207 208 #define PIIXPCIB_GSIC 0x47534943 209 #define PIIXPCIB_GETOWNER 0 210 #define PIIXPCIB_GETSTATE 1 211 #define PIIXPCIB_SETSTATE 2 212 #define PIIXPCIB_GETFREQS 4 213 214 #define PIIXPCIB_SPEEDSTEP_HIGH 0 215 #define PIIXPCIB_SPEEDSTEP_LOW 1 216 217 static void 218 piixpcib_int15_gsic_call(int *sig, int *smicmd, int *cmd, int *smidata, int *flags) 219 { 220 struct bioscallregs regs; 221 222 memset(®s, 0, sizeof(struct bioscallregs)); 223 regs.EAX = 0x0000e980; /* IST support */ 224 regs.EDX = PIIXPCIB_GSIC; 225 bioscall(0x15, ®s); 226 227 if (regs.EAX == PIIXPCIB_GSIC) { 228 *sig = regs.EAX; 229 *smicmd = regs.EBX & 0xff; 230 *cmd = (regs.EBX >> 16) & 0xff; 231 *smidata = regs.ECX; 232 *flags = regs.EDX; 233 } else 234 *sig = *smicmd = *cmd = *smidata = *flags = -1; 235 236 return; 237 } 238 239 static int 240 piixpcib_set_ownership(struct piixpcib_softc *sc) 241 { 242 int rv; 243 paddr_t pmagic; 244 static char magic[] = "Copyright (c) 1999 Intel Corporation"; 245 246 pmagic = vtophys((vaddr_t)magic); 247 248 __asm__ __volatile__( 249 "movl $0, %%edi\n\t" 250 "out %%al, (%%dx)\n" 251 : "=D" (rv) 252 : "a" (sc->sc_command), 253 "b" (0), 254 "c" (0), 255 "d" (sc->sc_smi_cmd), 256 "S" (pmagic) 257 ); 258 259 return (rv ? ENXIO : 0); 260 } 261 262 static int 263 piixpcib_getset_state(struct piixpcib_softc *sc, int *state, int function) 264 { 265 int new; 266 int rv; 267 int eax; 268 269 #ifdef DIAGNOSTIC 270 if (function != PIIXPCIB_GETSTATE && 271 function != PIIXPCIB_SETSTATE) { 272 aprint_error("%s: GSI called with invalid function %d\n", 273 sc->sc_dev.dv_xname, function); 274 return EINVAL; 275 } 276 #endif 277 278 __asm__ __volatile__( 279 "movl $0, %%edi\n\t" 280 "out %%al, (%%dx)\n" 281 : "=a" (eax), 282 "=b" (new), 283 "=D" (rv) 284 : "a" (sc->sc_command), 285 "b" (function), 286 "c" (*state), 287 "d" (sc->sc_smi_cmd), 288 "S" (0) 289 ); 290 291 *state = new & 1; 292 293 switch (function) { 294 case PIIXPCIB_GETSTATE: 295 if (eax) 296 return ENXIO; 297 break; 298 case PIIXPCIB_SETSTATE: 299 if (rv) 300 return ENXIO; 301 break; 302 } 303 304 return 0; 305 } 306 307 static int 308 piixpcib_get(struct piixpcib_softc *sc) 309 { 310 int rv; 311 int state; 312 313 state = 0; /* XXX gcc */ 314 315 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_GETSTATE); 316 if (rv) 317 return rv; 318 319 return state & 1; 320 } 321 322 static int 323 piixpcib_set(struct piixpcib_softc *sc, int state) 324 { 325 int rv, s; 326 int try; 327 328 if (state != PIIXPCIB_SPEEDSTEP_HIGH && 329 state != PIIXPCIB_SPEEDSTEP_LOW) 330 return ENXIO; 331 if (piixpcib_get(sc) == state) 332 return 0; 333 334 try = 5; 335 336 s = splhigh(); 337 338 do { 339 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_SETSTATE); 340 if (rv) 341 delay(200); 342 } while (rv && --try); 343 344 splx(s); 345 346 return rv; 347 } 348 349 static void 350 speedstep_configure(struct piixpcib_softc *sc, struct pci_attach_args *pa) 351 { 352 const struct sysctlnode *node, *ssnode; 353 int sig, smicmd, cmd, smidata, flags; 354 int rv; 355 356 piixpcib_int15_gsic_call(&sig, &smicmd, &cmd, &smidata, &flags); 357 358 if (sig != -1) { 359 sc->sc_smi_cmd = smicmd; 360 sc->sc_smi_data = smidata; 361 if (cmd == 0x80) { 362 aprint_debug("%s: GSIC returned cmd 0x80, should be 0x82\n", 363 sc->sc_dev.dv_xname); 364 cmd = 0x82; 365 } 366 sc->sc_command = (sig & 0xffffff00) | (cmd & 0xff); 367 sc->sc_flags = flags; 368 } else { 369 /* setup some defaults */ 370 sc->sc_smi_cmd = 0xb2; 371 sc->sc_smi_data = 0xb3; 372 sc->sc_command = 0x47534982; 373 sc->sc_flags = 0; 374 } 375 376 if (piixpcib_set_ownership(sc) != 0) { 377 aprint_error("%s: unable to claim ownership from the BIOS\n", 378 sc->sc_dev.dv_xname); 379 return; /* If we can't claim ownership from the BIOS, bail */ 380 } 381 382 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 383 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 384 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 385 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 386 goto err; 387 388 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 389 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 390 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 391 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 392 CTL_EOL)) != 0) 393 goto err; 394 395 /* XXX save the sc for IO tag/handle */ 396 speedstep_cookie = sc; 397 398 aprint_verbose("%s: SpeedStep SMI enabled\n", sc->sc_dev.dv_xname); 399 400 return; 401 402 err: 403 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 404 405 return; 406 } 407 408 /* 409 * get/set the SpeedStep state: 0 == low power, 1 == high power. 410 */ 411 static int 412 speedstep_sysctl_helper(SYSCTLFN_ARGS) 413 { 414 struct sysctlnode node; 415 struct piixpcib_softc *sc; 416 uint8_t state, state2; 417 int ostate, nstate, error; 418 419 sc = speedstep_cookie; 420 error = 0; 421 422 state = piixpcib_get(sc); 423 if (state == PIIXPCIB_SPEEDSTEP_HIGH) 424 ostate = 1; 425 else 426 ostate = 0; 427 nstate = ostate; 428 429 node = *rnode; 430 node.sysctl_data = &nstate; 431 432 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 433 if (error || newp == NULL) 434 goto out; 435 436 /* Only two states are available */ 437 if (nstate != 0 && nstate != 1) { 438 error = EINVAL; 439 goto out; 440 } 441 442 state2 = piixpcib_get(sc); 443 if (state2 == PIIXPCIB_SPEEDSTEP_HIGH) 444 ostate = 1; 445 else 446 ostate = 0; 447 448 if (ostate != nstate) 449 { 450 if (nstate == 0) 451 state2 = PIIXPCIB_SPEEDSTEP_LOW; 452 else 453 state2 = PIIXPCIB_SPEEDSTEP_HIGH; 454 455 error = piixpcib_set(sc, state2); 456 } 457 out: 458 return (error); 459 } 460
Indexes created Thu Sep 25 16:09:42 GMT 2025