ncr5380reg.h revision 1.3
1 /* $NetBSD: ncr5380reg.h,v 1.3 1995/09/15 01:52:20 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Leo Weppelman. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Leo Weppelman. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _NCR5380REG_H 34 #define _NCR5380REG_H 35 /* 36 * NCR5380 common interface definitions. 37 */ 38 39 /* 40 * Register numbers: (first argument to GET/SET_5380_REG ) 41 */ 42 #define NCR5380_DATA 0 /* Data register */ 43 #define NCR5380_ICOM 1 /* Initiator command register */ 44 #define NCR5380_MODE 2 /* Mode register */ 45 #define NCR5380_TCOM 3 /* Target command register */ 46 #define NCR5380_IDSTAT 4 /* Bus status register */ 47 #define NCR5380_DMSTAT 5 /* DMA status register */ 48 #define NCR5380_TRCV 6 /* Target receive register */ 49 #define NCR5380_IRCV 7 /* Initiator receive register */ 50 51 /* 52 * Definitions for Initiator command register. 53 */ 54 #define SC_A_RST 0x80 /* RW - Assert RST */ 55 #define SC_TEST 0x40 /* W - Test mode */ 56 #define SC_AIP 0x40 /* R - Arbitration in progress */ 57 #define SC_LA 0x20 /* R - Lost arbitration */ 58 #define SC_A_ACK 0x10 /* RW - Assert ACK */ 59 #define SC_A_BSY 0x08 /* RW - Assert BSY */ 60 #define SC_A_SEL 0x04 /* RW - Assert SEL */ 61 #define SC_A_ATN 0x02 /* RW - Assert ATN */ 62 #define SC_ADTB 0x01 /* RW - Assert Data To Bus */ 63 64 /* 65 * Definitions for mode register 66 */ 67 #define SC_B_DMA 0x80 /* RW - Block mode DMA (not on TT!) */ 68 #define SC_T_MODE 0x40 /* RW - Target mode */ 69 #define SC_E_PAR 0x20 /* RW - Enable parity check */ 70 #define SC_E_PARI 0x10 /* RW - Enable parity interrupt */ 71 #define SC_E_EOPI 0x08 /* RW - Enable End Of Process Interrupt */ 72 #define SC_MON_BSY 0x04 /* RW - Monitor BSY */ 73 #define SC_M_DMA 0x02 /* RW - Set DMA mode */ 74 #define SC_ARBIT 0x01 /* RW - Arbitrate */ 75 76 /* 77 * Definitions for tcom register 78 */ 79 #define SC_LBS 0x80 /* RW - Last Byte Send (not on TT!) */ 80 #define SC_A_REQ 0x08 /* RW - Assert REQ */ 81 #define SC_A_MSG 0x04 /* RW - Assert MSG */ 82 #define SC_A_CD 0x02 /* RW - Assert C/D */ 83 #define SC_A_IO 0x01 /* RW - Assert I/O */ 84 85 /* 86 * Definitions for idstat register 87 */ 88 #define SC_S_RST 0x80 /* R - RST is set */ 89 #define SC_S_BSY 0x40 /* R - BSY is set */ 90 #define SC_S_REQ 0x20 /* R - REQ is set */ 91 #define SC_S_MSG 0x10 /* R - MSG is set */ 92 #define SC_S_CD 0x08 /* R - C/D is set */ 93 #define SC_S_IO 0x04 /* R - I/O is set */ 94 #define SC_S_SEL 0x02 /* R - SEL is set */ 95 #define SC_S_PAR 0x01 /* R - Parity bit */ 96 97 /* 98 * Definitions for dmastat register 99 */ 100 #define SC_END_DMA 0x80 /* R - End of DMA */ 101 #define SC_DMA_REQ 0x40 /* R - DMA request */ 102 #define SC_PAR_ERR 0x20 /* R - Parity error */ 103 #define SC_IRQ_SET 0x10 /* R - IRQ is active */ 104 #define SC_PHS_MTCH 0x08 /* R - Phase Match */ 105 #define SC_BSY_ERR 0x04 /* R - Busy error */ 106 #define SC_ATN_STAT 0x02 /* R - State of ATN line */ 107 #define SC_ACK_STAT 0x01 /* R - State of ACK line */ 108 #define SC_S_SEND 0x00 /* W - Start DMA output */ 109 110 #define SC_CLINT { /* Clear interrupts */ \ 111 int i = GET_5380_REG(NCR5380_IRCV); \ 112 } 113 114 115 /* 116 * Definition of SCSI-bus phases. The values are determined by signals 117 * on the SCSI-bus. DO NOT CHANGE! 118 * The values must be used to index the pointers in SCSI-PARMS. 119 */ 120 #define NR_PHASE 8 121 #define PH_DATAOUT 0 122 #define PH_DATAIN 1 123 #define PH_CMD 2 124 #define PH_STATUS 3 125 #define PH_RES1 4 126 #define PH_RES2 5 127 #define PH_MSGOUT 6 128 #define PH_MSGIN 7 129 130 #define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */ 131 #define PH_IN(phase) (phase & 1) /* TRUE if input phase */ 132 133 /* 134 * Id of Host-adapter 135 */ 136 #define SC_HOST_ID 0x80 137 138 /* 139 * Base setting for 5380 mode register 140 */ 141 #define IMODE_BASE SC_E_PAR 142 143 /* 144 * SCSI completion status codes, should move to sys/scsi/???? 145 */ 146 #define SCSMASK 0x1e /* status code mask */ 147 #define SCSGOOD 0x00 /* good status */ 148 #define SCSCHKC 0x02 /* check condition */ 149 #define SCSBUSY 0x08 /* busy status */ 150 #define SCSCMET 0x04 /* condition met / good */ 151 152 /* 153 * Return values of check_intr() 154 */ 155 #define INTR_SPURIOUS 0 156 #define INTR_RESEL 2 157 #define INTR_DMA 3 158 159 struct ncr_softc { 160 struct device sc_dev; 161 struct scsi_link sc_link; 162 163 /* 164 * Some (pre-SCSI2) devices don't support select with ATN. 165 * If the device responds to select with ATN by going into 166 * command phase (ignoring ATN), then we flag it in the 167 * following bitmask. 168 * We also keep track of which devices have been selected 169 * before. This allows us to not even try raising ATN if 170 * the target doesn't respond to it the first time. 171 */ 172 u_int8_t sc_noselatn; 173 u_int8_t sc_selected; 174 }; 175 176 /* 177 * Max. number of dma-chains per request 178 */ 179 #define MAXDMAIO (MAXPHYS/NBPG + 1) 180 181 /* 182 * Some requests are not contiguous in physical memory. We need to break them 183 * up into contiguous parts for DMA. 184 */ 185 struct dma_chain { 186 u_int dm_count; 187 u_long dm_addr; 188 }; 189 190 /* 191 * Define our issue, free and disconnect queue's. 192 */ 193 typedef struct req_q { 194 struct req_q *next; /* next in free, issue or discon queue */ 195 struct req_q *link; /* next linked command to execute */ 196 struct scsi_xfer *xs; /* request from high-level driver */ 197 u_short dr_flag; /* driver state */ 198 u_char phase; /* current SCSI phase */ 199 u_char msgout; /* message to send when requested */ 200 u_char targ_id; /* target for command */ 201 u_char targ_lun; /* lun for command */ 202 u_char status; /* returned status byte */ 203 u_char message; /* returned message byte */ 204 u_char *bounceb; /* allocated bounce buffer */ 205 u_char *bouncerp; /* bounce read-pointer */ 206 struct dma_chain dm_chain[MAXDMAIO]; 207 struct dma_chain *dm_cur; /* current dma-request */ 208 struct dma_chain *dm_last; /* last dma-request */ 209 long xdata_len; /* length of transfer */ 210 u_char *xdata_ptr; /* virtual address of transfer */ 211 struct scsi_generic xcmd; /* command to execute */ 212 } SC_REQ; 213 214 /* 215 * Values for dr_flag: 216 */ 217 #define DRIVER_IN_DMA 0x01 /* Non-polled DMA activated */ 218 #define DRIVER_AUTOSEN 0x02 /* Doing automatic sense */ 219 #define DRIVER_NOINT 0x04 /* We are booting: no interrupts */ 220 #define DRIVER_DMAOK 0x08 /* DMA can be used on this request */ 221 #define DRIVER_BOUNCING 0x10 /* Using the bounce buffer */ 222 223 /* XXX: Should go to ncr5380var.h */ 224 static SC_REQ *issue_q = NULL; /* Commands waiting to be issued*/ 225 static SC_REQ *discon_q = NULL; /* Commands disconnected */ 226 static SC_REQ *connected = NULL; /* Command currently connected */ 227 228 /* 229 * Function decls: 230 */ 231 static int transfer_pio __P((u_char *, u_char *, u_long *, int)); 232 static int wait_req_true __P((void)); 233 static int wait_req_false __P((void)); 234 static int scsi_select __P((SC_REQ *, int)); 235 static int handle_message __P((SC_REQ *, u_int)); 236 static void ack_message __P((void)); 237 static void nack_message __P((SC_REQ *)); 238 static int information_transfer __P((void)); 239 static void reselect __P((struct ncr_softc *)); 240 static int dma_ready __P((void)); 241 static void transfer_dma __P((SC_REQ *, u_int, int)); 242 static int check_autosense __P((SC_REQ *, int)); 243 static int reach_msg_out __P((struct ncr_softc *, u_long)); 244 static int check_intr __P((struct ncr_softc *)); 245 static void scsi_reset __P((struct ncr_softc *)); 246 static int scsi_dmaok __P((SC_REQ *)); 247 static void run_main __P((struct ncr_softc *)); 248 static void scsi_main __P((struct ncr_softc *)); 249 static void ncr_ctrl_intr __P((struct ncr_softc *)); 250 static void ncr_dma_intr __P((struct ncr_softc *)); 251 static void ncr_tprint __P((SC_REQ *, char *, ...)); 252 static void ncr_aprint __P((struct ncr_softc *, char *, ...)); 253 254 static void show_request __P((SC_REQ *, char *)); 255 static void show_phase __P((SC_REQ *, int)); 256 static void show_signals __P((u_char, u_char)); 257 258 #endif /* _NCR5380REG_H */ 259
Indexes created Sun Sep 28 07:09:56 GMT 2025