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      1  1.8     rin /*	$NetBSD: psc.h,v 1.8 2019/07/23 15:19:07 rin Exp $	*/
      2  1.2  briggs 
      3  1.1  briggs /*-
      4  1.5     wiz  * Copyright (c) 1997 David Huang <khym (at) azeotrope.org>
      5  1.1  briggs  * All rights reserved.
      6  1.1  briggs  *
      7  1.1  briggs  * Redistribution and use in source and binary forms, with or without
      8  1.1  briggs  * modification, are permitted provided that the following conditions
      9  1.1  briggs  * are met:
     10  1.1  briggs  * 1. Redistributions of source code must retain the above copyright
     11  1.1  briggs  *    notice, this list of conditions and the following disclaimer.
     12  1.1  briggs  * 2. The name of the author may not be used to endorse or promote products
     13  1.1  briggs  *    derived from this software without specific prior written permission
     14  1.1  briggs  *
     15  1.1  briggs  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  1.1  briggs  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  1.1  briggs  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  1.1  briggs  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  1.1  briggs  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  1.1  briggs  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  1.1  briggs  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  1.1  briggs  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  1.1  briggs  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  1.1  briggs  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  1.1  briggs  *
     26  1.1  briggs  */
     27  1.1  briggs 
     28  1.8     rin #include <sys/bus.h>	/* XXX for bus_addr_t */
     29  1.8     rin 
     30  1.1  briggs /*
     31  1.1  briggs  * Some register definitions for the PSC, present only on the
     32  1.1  briggs  * Centris/Quadra 660av and the Quadra 840av.
     33  1.1  briggs  */
     34  1.1  briggs 
     35  1.1  briggs extern volatile u_int8_t *PSCBase;
     36  1.1  briggs 
     37  1.1  briggs #define psc_reg1(r) (*((volatile u_int8_t *)(PSCBase+r)))
     38  1.1  briggs #define	psc_reg2(r) (*((volatile u_int16_t *)(PSCBase+r)))
     39  1.1  briggs #define	psc_reg4(r) (*((volatile u_int32_t *)(PSCBase+r)))
     40  1.1  briggs 
     41  1.6     chs void	psc_init(void);
     42  1.3  scottr 
     43  1.6     chs int	add_psc_lev3_intr(void (*)(void *), void *);
     44  1.6     chs int	add_psc_lev4_intr(int, int (*)(void *), void *);
     45  1.6     chs int	add_psc_lev5_intr(int, void (*)(void *), void *);
     46  1.6     chs int	add_psc_lev6_intr(int, void (*)(void *), void *);
     47  1.6     chs 
     48  1.6     chs int	remove_psc_lev3_intr(void);
     49  1.6     chs int	remove_psc_lev4_intr(int);
     50  1.6     chs int	remove_psc_lev5_intr(int);
     51  1.6     chs int	remove_psc_lev6_intr(int);
     52  1.1  briggs 
     53  1.8     rin int	start_psc_dma(int, int *, bus_addr_t, uint32_t, int);
     54  1.8     rin int	pause_psc_dma(int);
     55  1.8     rin int	wait_psc_dma(int, int, uint32_t *);
     56  1.8     rin int	stop_psc_dma(int, int, uint32_t *, int);
     57  1.8     rin 
     58  1.1  briggs /*
     59  1.1  briggs  * Reading an interrupt status register returns a mask of the
     60  1.1  briggs  * currently interrupting devices (one bit per device). Reading an
     61  1.1  briggs  * interrupt enable register returns a mask of the currently enabled
     62  1.1  briggs  * devices. Writing an interrupt enable register with the MSB set
     63  1.1  briggs  * enables the interrupts in the lower 4 bits, while writing with the
     64  1.1  briggs  * MSB clear disables the corresponding interrupts.
     65  1.1  briggs  * e.g. write 0x81 to enable device 0, write 0x86 to enable devices 1
     66  1.1  briggs  * and 2, write 0x02 to disable device 1.
     67  1.1  briggs  *
     68  1.1  briggs  * Level 3 device 0 is MACE
     69  1.1  briggs  * Level 4 device 0 is 3210 DSP?
     70  1.1  briggs  * Level 4 device 1 is SCC channel A (modem port)
     71  1.1  briggs  * Level 4 device 2 is SCC channel B (printer port)
     72  1.1  briggs  * Level 4 device 3 is MACE DMA completion
     73  1.1  briggs  * Level 5 device 0 is 3210 DSP?
     74  1.1  briggs  * Level 5 device 1 is 3210 DSP?
     75  1.1  briggs  * Level 6 device 0 is ?
     76  1.1  briggs  * Level 6 device 1 is ?
     77  1.1  briggs  * Level 6 device 2 is ?
     78  1.1  briggs  */
     79  1.1  briggs 
     80  1.1  briggs /* PSC interrupt registers */
     81  1.4  briggs #define PSC_ISR_BASE	0x100	/* ISR is BASE + 0x10 * level */
     82  1.4  briggs #define PSC_IER_BASE	0x104	/* IER is BASE + 0x10 * level */
     83  1.4  briggs 
     84  1.1  briggs #define	PSC_LEV3_ISR	0x130	/* level 3 interrupt status register */
     85  1.1  briggs #define	PSC_LEV3_IER	0x134	/* level 3 interrupt enable register */
     86  1.1  briggs #define	  PSCINTR_ENET      0	/*   Ethernet interrupt */
     87  1.1  briggs 
     88  1.1  briggs #define	PSC_LEV4_ISR	0x140	/* level 4 interrupt status register */
     89  1.1  briggs #define	PSC_LEV4_IER	0x144	/* level 4 interrupt enable register */
     90  1.1  briggs #define	  PSCINTR_SCCA      1	/*   SCC channel A interrupt */
     91  1.1  briggs #define	  PSCINTR_SCCB      2	/*   SCC channel B interrupt */
     92  1.1  briggs #define	  PSCINTR_ENET_DMA  3	/*   Ethernet DMA completion interrupt */
     93  1.1  briggs 
     94  1.1  briggs #define	PSC_LEV5_ISR	0x150	/* level 5 interrupt status register */
     95  1.1  briggs #define	PSC_LEV5_IER	0x154	/* level 5 interrupt enable register */
     96  1.1  briggs 
     97  1.1  briggs #define	PSC_LEV6_ISR	0x160	/* level 6 interrupt status register */
     98  1.1  briggs #define	PSC_LEV6_IER	0x164	/* level 6 interrupt enable register */
     99  1.1  briggs 
    100  1.1  briggs /* PSC DMA channel control registers */
    101  1.4  briggs #define	PSC_CTLBASE	0xc00
    102  1.4  briggs 
    103  1.4  briggs #define	PSC_SCSI_CTL	0xc00	/* SCSI control/status */
    104  1.1  briggs #define	PSC_ENETRD_CTL	0xc10	/* MACE receive DMA channel control/status */
    105  1.1  briggs #define	PSC_ENETWR_CTL	0xc20	/* MACE transmit DMA channel control/status */
    106  1.4  briggs #define	PSC_FDC_CTL	0xc30	/* Floppy disk */
    107  1.4  briggs #define	PSC_SCCA_CTL	0xc40	/* SCC channel A */
    108  1.4  briggs #define	PSC_SCCB_CTL	0xc50	/* SCC channel B */
    109  1.4  briggs #define	PSC_SCCATX_CTL	0xc60	/* SCC channel A transmit */
    110  1.1  briggs 
    111  1.1  briggs /* PSC DMA channels */
    112  1.4  briggs #define	PSC_ADDRBASE	0x1000
    113  1.4  briggs #define	PSC_LENBASE	0x1004
    114  1.4  briggs #define	PSC_CMDBASE	0x1008
    115  1.4  briggs 
    116  1.4  briggs #define	PSC_SCSI_ADDR	0x1000	/* SCSI DMA address register */
    117  1.4  briggs #define	PSC_SCSI_LEN	0x1004	/* SCSI DMA buffer count */
    118  1.4  briggs #define	PSC_SCSI_CMD	0x1008	/* SCSI DMA command register */
    119  1.1  briggs #define	PSC_ENETRD_ADDR	0x1020	/* MACE receive DMA address register */
    120  1.1  briggs #define	PSC_ENETRD_LEN	0x1024	/* MACE receive DMA buffer count */
    121  1.1  briggs #define	PSC_ENETRD_CMD	0x1028	/* MACE receive DMA command register */
    122  1.1  briggs #define	PSC_ENETWR_ADDR	0x1040	/* MACE transmit DMA address register */
    123  1.1  briggs #define	PSC_ENETWR_LEN	0x1044	/* MACE transmit DMA length */
    124  1.1  briggs #define	PSC_ENETWR_CMD	0x1048	/* MACE transmit DMA command register */
    125  1.1  briggs 
    126  1.1  briggs /*
    127  1.1  briggs  * PSC DMA channels are controlled by two sets of registers (see p.29
    128  1.1  briggs  * of the Quadra 840av and Centris 660av Developer Note). Add the
    129  1.1  briggs  * following offsets to get the desired register set.
    130  1.1  briggs  */
    131  1.1  briggs #define	PSC_SET0	0x00
    132  1.1  briggs #define	PSC_SET1	0x10
    133  1.8     rin 
    134  1.8     rin /*
    135  1.8     rin  * Pseudo channels for the dma control functions
    136  1.8     rin  */
    137  1.8     rin #define	PSC_DMA_CHANNEL_SCSI	0
    138  1.8     rin #define	PSC_DMA_CHANNEL_ENETRD	1
    139  1.8     rin #define	PSC_DMA_CHANNEL_ENETWR	2
    140  1.8     rin #define	PSC_DMA_CHANNEL_FDC	3
    141  1.8     rin #define	PSC_DMA_CHANNEL_SCCA	4
    142  1.8     rin #define	PSC_DMA_CHANNEL_SCCB	5
    143  1.8     rin #define	PSC_DMA_CHANNEL_SCCATX	6
    144