psc.h revision 1.2 1 1.2 briggs /* $NetBSD: psc.h,v 1.2 1997/11/07 13:31:21 briggs Exp $ */
2 1.2 briggs
3 1.1 briggs /*-
4 1.1 briggs * Copyright (c) 1997 David Huang <khym (at) bga.com>
5 1.1 briggs * All rights reserved.
6 1.1 briggs *
7 1.1 briggs * Redistribution and use in source and binary forms, with or without
8 1.1 briggs * modification, are permitted provided that the following conditions
9 1.1 briggs * are met:
10 1.1 briggs * 1. Redistributions of source code must retain the above copyright
11 1.1 briggs * notice, this list of conditions and the following disclaimer.
12 1.1 briggs * 2. The name of the author may not be used to endorse or promote products
13 1.1 briggs * derived from this software without specific prior written permission
14 1.1 briggs *
15 1.1 briggs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 1.1 briggs * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 1.1 briggs * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 1.1 briggs * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 1.1 briggs * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 1.1 briggs * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 1.1 briggs * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 1.1 briggs * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 1.1 briggs * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 1.1 briggs * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 1.1 briggs *
26 1.1 briggs */
27 1.1 briggs
28 1.1 briggs /*
29 1.1 briggs * Some register definitions for the PSC, present only on the
30 1.1 briggs * Centris/Quadra 660av and the Quadra 840av.
31 1.1 briggs */
32 1.1 briggs
33 1.1 briggs extern volatile u_int8_t *PSCBase;
34 1.1 briggs
35 1.1 briggs #define psc_reg1(r) (*((volatile u_int8_t *)(PSCBase+r)))
36 1.1 briggs #define psc_reg2(r) (*((volatile u_int16_t *)(PSCBase+r)))
37 1.1 briggs #define psc_reg4(r) (*((volatile u_int32_t *)(PSCBase+r)))
38 1.1 briggs
39 1.1 briggs int add_psc_lev3_intr __P((void (*)(void *), void *));
40 1.1 briggs int add_psc_lev4_intr __P((int, int (*)(void *), void *));
41 1.1 briggs int add_psc_lev5_intr __P((int, void (*)(void *), void *));
42 1.1 briggs int add_psc_lev6_intr __P((int, void (*)(void *), void *));
43 1.1 briggs
44 1.1 briggs int remove_psc_lev3_intr __P((void));
45 1.1 briggs int remove_psc_lev4_intr __P((int));
46 1.1 briggs int remove_psc_lev5_intr __P((int));
47 1.1 briggs int remove_psc_lev6_intr __P((int));
48 1.1 briggs
49 1.1 briggs /*
50 1.1 briggs * Reading an interrupt status register returns a mask of the
51 1.1 briggs * currently interrupting devices (one bit per device). Reading an
52 1.1 briggs * interrupt enable register returns a mask of the currently enabled
53 1.1 briggs * devices. Writing an interrupt enable register with the MSB set
54 1.1 briggs * enables the interrupts in the lower 4 bits, while writing with the
55 1.1 briggs * MSB clear disables the corresponding interrupts.
56 1.1 briggs * e.g. write 0x81 to enable device 0, write 0x86 to enable devices 1
57 1.1 briggs * and 2, write 0x02 to disable device 1.
58 1.1 briggs *
59 1.1 briggs * Level 3 device 0 is MACE
60 1.1 briggs * Level 4 device 0 is 3210 DSP?
61 1.1 briggs * Level 4 device 1 is SCC channel A (modem port)
62 1.1 briggs * Level 4 device 2 is SCC channel B (printer port)
63 1.1 briggs * Level 4 device 3 is MACE DMA completion
64 1.1 briggs * Level 5 device 0 is 3210 DSP?
65 1.1 briggs * Level 5 device 1 is 3210 DSP?
66 1.1 briggs * Level 6 device 0 is ?
67 1.1 briggs * Level 6 device 1 is ?
68 1.1 briggs * Level 6 device 2 is ?
69 1.1 briggs */
70 1.1 briggs
71 1.1 briggs /* PSC interrupt registers */
72 1.1 briggs #define PSC_LEV3_ISR 0x130 /* level 3 interrupt status register */
73 1.1 briggs #define PSC_LEV3_IER 0x134 /* level 3 interrupt enable register */
74 1.1 briggs #define PSCINTR_ENET 0 /* Ethernet interrupt */
75 1.1 briggs
76 1.1 briggs #define PSC_LEV4_ISR 0x140 /* level 4 interrupt status register */
77 1.1 briggs #define PSC_LEV4_IER 0x144 /* level 4 interrupt enable register */
78 1.1 briggs #define PSCINTR_SCCA 1 /* SCC channel A interrupt */
79 1.1 briggs #define PSCINTR_SCCB 2 /* SCC channel B interrupt */
80 1.1 briggs #define PSCINTR_ENET_DMA 3 /* Ethernet DMA completion interrupt */
81 1.1 briggs
82 1.1 briggs #define PSC_LEV5_ISR 0x150 /* level 5 interrupt status register */
83 1.1 briggs #define PSC_LEV5_IER 0x154 /* level 5 interrupt enable register */
84 1.1 briggs
85 1.1 briggs #define PSC_LEV6_ISR 0x160 /* level 6 interrupt status register */
86 1.1 briggs #define PSC_LEV6_IER 0x164 /* level 6 interrupt enable register */
87 1.1 briggs
88 1.1 briggs /* PSC DMA channel control registers */
89 1.1 briggs #define PSC_ENETRD_CTL 0xc10 /* MACE receive DMA channel control/status */
90 1.1 briggs #define PSC_ENETWR_CTL 0xc20 /* MACE transmit DMA channel control/status */
91 1.1 briggs
92 1.1 briggs /* PSC DMA channels */
93 1.1 briggs #define PSC_ENETRD_ADDR 0x1020 /* MACE receive DMA address register */
94 1.1 briggs #define PSC_ENETRD_LEN 0x1024 /* MACE receive DMA buffer count */
95 1.1 briggs #define PSC_ENETRD_CMD 0x1028 /* MACE receive DMA command register */
96 1.1 briggs #define PSC_ENETWR_ADDR 0x1040 /* MACE transmit DMA address register */
97 1.1 briggs #define PSC_ENETWR_LEN 0x1044 /* MACE transmit DMA length */
98 1.1 briggs #define PSC_ENETWR_CMD 0x1048 /* MACE transmit DMA command register */
99 1.1 briggs
100 1.1 briggs /*
101 1.1 briggs * PSC DMA channels are controlled by two sets of registers (see p.29
102 1.1 briggs * of the Quadra 840av and Centris 660av Developer Note). Add the
103 1.1 briggs * following offsets to get the desired register set.
104 1.1 briggs */
105 1.1 briggs #define PSC_SET0 0x00
106 1.1 briggs #define PSC_SET1 0x10
107