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psc.h revision 1.1 
      1 /*-
      2  * Copyright (c) 1997 David Huang <khym (at) bga.com>
      3  * All rights reserved.
      4  *
      5  * Redistribution and use in source and binary forms, with or without
      6  * modification, are permitted provided that the following conditions
      7  * are met:
      8  * 1. Redistributions of source code must retain the above copyright
      9  *    notice, this list of conditions and the following disclaimer.
     10  * 2. The name of the author may not be used to endorse or promote products
     11  *    derived from this software without specific prior written permission
     12  *
     13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     23  *
     24  */
     25 
     26 /*
     27  * Some register definitions for the PSC, present only on the
     28  * Centris/Quadra 660av and the Quadra 840av.
     29  */
     30 
     31 extern volatile u_int8_t *PSCBase;
     32 
     33 #define psc_reg1(r) (*((volatile u_int8_t *)(PSCBase+r)))
     34 #define	psc_reg2(r) (*((volatile u_int16_t *)(PSCBase+r)))
     35 #define	psc_reg4(r) (*((volatile u_int32_t *)(PSCBase+r)))
     36 
     37 int add_psc_lev3_intr __P((void (*)(void *), void *));
     38 int add_psc_lev4_intr __P((int, int (*)(void *), void *));
     39 int add_psc_lev5_intr __P((int, void (*)(void *), void *));
     40 int add_psc_lev6_intr __P((int, void (*)(void *), void *));
     41 
     42 int remove_psc_lev3_intr __P((void));
     43 int remove_psc_lev4_intr __P((int));
     44 int remove_psc_lev5_intr __P((int));
     45 int remove_psc_lev6_intr __P((int));
     46 
     47 /*
     48  * Reading an interrupt status register returns a mask of the
     49  * currently interrupting devices (one bit per device). Reading an
     50  * interrupt enable register returns a mask of the currently enabled
     51  * devices. Writing an interrupt enable register with the MSB set
     52  * enables the interrupts in the lower 4 bits, while writing with the
     53  * MSB clear disables the corresponding interrupts.
     54  * e.g. write 0x81 to enable device 0, write 0x86 to enable devices 1
     55  * and 2, write 0x02 to disable device 1.
     56  *
     57  * Level 3 device 0 is MACE
     58  * Level 4 device 0 is 3210 DSP?
     59  * Level 4 device 1 is SCC channel A (modem port)
     60  * Level 4 device 2 is SCC channel B (printer port)
     61  * Level 4 device 3 is MACE DMA completion
     62  * Level 5 device 0 is 3210 DSP?
     63  * Level 5 device 1 is 3210 DSP?
     64  * Level 6 device 0 is ?
     65  * Level 6 device 1 is ?
     66  * Level 6 device 2 is ?
     67  */
     68 
     69 /* PSC interrupt registers */
     70 #define	PSC_LEV3_ISR	0x130	/* level 3 interrupt status register */
     71 #define	PSC_LEV3_IER	0x134	/* level 3 interrupt enable register */
     72 #define	  PSCINTR_ENET      0	/*   Ethernet interrupt */
     73 
     74 #define	PSC_LEV4_ISR	0x140	/* level 4 interrupt status register */
     75 #define	PSC_LEV4_IER	0x144	/* level 4 interrupt enable register */
     76 #define	  PSCINTR_SCCA      1	/*   SCC channel A interrupt */
     77 #define	  PSCINTR_SCCB      2	/*   SCC channel B interrupt */
     78 #define	  PSCINTR_ENET_DMA  3	/*   Ethernet DMA completion interrupt */
     79 
     80 #define	PSC_LEV5_ISR	0x150	/* level 5 interrupt status register */
     81 #define	PSC_LEV5_IER	0x154	/* level 5 interrupt enable register */
     82 
     83 #define	PSC_LEV6_ISR	0x160	/* level 6 interrupt status register */
     84 #define	PSC_LEV6_IER	0x164	/* level 6 interrupt enable register */
     85 
     86 /* PSC DMA channel control registers */
     87 #define	PSC_ENETRD_CTL	0xc10	/* MACE receive DMA channel control/status */
     88 #define	PSC_ENETWR_CTL	0xc20	/* MACE transmit DMA channel control/status */
     89 
     90 /* PSC DMA channels */
     91 #define	PSC_ENETRD_ADDR	0x1020	/* MACE receive DMA address register */
     92 #define	PSC_ENETRD_LEN	0x1024	/* MACE receive DMA buffer count */
     93 #define	PSC_ENETRD_CMD	0x1028	/* MACE receive DMA command register */
     94 #define	PSC_ENETWR_ADDR	0x1040	/* MACE transmit DMA address register */
     95 #define	PSC_ENETWR_LEN	0x1044	/* MACE transmit DMA length */
     96 #define	PSC_ENETWR_CMD	0x1048	/* MACE transmit DMA command register */
     97 
     98 /*
     99  * PSC DMA channels are controlled by two sets of registers (see p.29
    100  * of the Quadra 840av and Centris 660av Developer Note). Add the
    101  * following offsets to get the desired register set.
    102  */
    103 #define	PSC_SET0	0x00
    104 #define	PSC_SET1	0x10
    105