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psc.h revision 1.2 
      1 /*	$NetBSD: psc.h,v 1.2 1997/11/07 13:31:21 briggs Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1997 David Huang <khym (at) bga.com>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. The name of the author may not be used to endorse or promote products
     13  *    derived from this software without specific prior written permission
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  *
     26  */
     27 
     28 /*
     29  * Some register definitions for the PSC, present only on the
     30  * Centris/Quadra 660av and the Quadra 840av.
     31  */
     32 
     33 extern volatile u_int8_t *PSCBase;
     34 
     35 #define psc_reg1(r) (*((volatile u_int8_t *)(PSCBase+r)))
     36 #define	psc_reg2(r) (*((volatile u_int16_t *)(PSCBase+r)))
     37 #define	psc_reg4(r) (*((volatile u_int32_t *)(PSCBase+r)))
     38 
     39 int add_psc_lev3_intr __P((void (*)(void *), void *));
     40 int add_psc_lev4_intr __P((int, int (*)(void *), void *));
     41 int add_psc_lev5_intr __P((int, void (*)(void *), void *));
     42 int add_psc_lev6_intr __P((int, void (*)(void *), void *));
     43 
     44 int remove_psc_lev3_intr __P((void));
     45 int remove_psc_lev4_intr __P((int));
     46 int remove_psc_lev5_intr __P((int));
     47 int remove_psc_lev6_intr __P((int));
     48 
     49 /*
     50  * Reading an interrupt status register returns a mask of the
     51  * currently interrupting devices (one bit per device). Reading an
     52  * interrupt enable register returns a mask of the currently enabled
     53  * devices. Writing an interrupt enable register with the MSB set
     54  * enables the interrupts in the lower 4 bits, while writing with the
     55  * MSB clear disables the corresponding interrupts.
     56  * e.g. write 0x81 to enable device 0, write 0x86 to enable devices 1
     57  * and 2, write 0x02 to disable device 1.
     58  *
     59  * Level 3 device 0 is MACE
     60  * Level 4 device 0 is 3210 DSP?
     61  * Level 4 device 1 is SCC channel A (modem port)
     62  * Level 4 device 2 is SCC channel B (printer port)
     63  * Level 4 device 3 is MACE DMA completion
     64  * Level 5 device 0 is 3210 DSP?
     65  * Level 5 device 1 is 3210 DSP?
     66  * Level 6 device 0 is ?
     67  * Level 6 device 1 is ?
     68  * Level 6 device 2 is ?
     69  */
     70 
     71 /* PSC interrupt registers */
     72 #define	PSC_LEV3_ISR	0x130	/* level 3 interrupt status register */
     73 #define	PSC_LEV3_IER	0x134	/* level 3 interrupt enable register */
     74 #define	  PSCINTR_ENET      0	/*   Ethernet interrupt */
     75 
     76 #define	PSC_LEV4_ISR	0x140	/* level 4 interrupt status register */
     77 #define	PSC_LEV4_IER	0x144	/* level 4 interrupt enable register */
     78 #define	  PSCINTR_SCCA      1	/*   SCC channel A interrupt */
     79 #define	  PSCINTR_SCCB      2	/*   SCC channel B interrupt */
     80 #define	  PSCINTR_ENET_DMA  3	/*   Ethernet DMA completion interrupt */
     81 
     82 #define	PSC_LEV5_ISR	0x150	/* level 5 interrupt status register */
     83 #define	PSC_LEV5_IER	0x154	/* level 5 interrupt enable register */
     84 
     85 #define	PSC_LEV6_ISR	0x160	/* level 6 interrupt status register */
     86 #define	PSC_LEV6_IER	0x164	/* level 6 interrupt enable register */
     87 
     88 /* PSC DMA channel control registers */
     89 #define	PSC_ENETRD_CTL	0xc10	/* MACE receive DMA channel control/status */
     90 #define	PSC_ENETWR_CTL	0xc20	/* MACE transmit DMA channel control/status */
     91 
     92 /* PSC DMA channels */
     93 #define	PSC_ENETRD_ADDR	0x1020	/* MACE receive DMA address register */
     94 #define	PSC_ENETRD_LEN	0x1024	/* MACE receive DMA buffer count */
     95 #define	PSC_ENETRD_CMD	0x1028	/* MACE receive DMA command register */
     96 #define	PSC_ENETWR_ADDR	0x1040	/* MACE transmit DMA address register */
     97 #define	PSC_ENETWR_LEN	0x1044	/* MACE transmit DMA length */
     98 #define	PSC_ENETWR_CMD	0x1048	/* MACE transmit DMA command register */
     99 
    100 /*
    101  * PSC DMA channels are controlled by two sets of registers (see p.29
    102  * of the Quadra 840av and Centris 660av Developer Note). Add the
    103  * following offsets to get the desired register set.
    104  */
    105 #define	PSC_SET0	0x00
    106 #define	PSC_SET1	0x10
    107