if_bmreg.h revision 1.2 1 1.2 tsubai /* $NetBSD: if_bmreg.h,v 1.2 2000/01/25 14:38:50 tsubai Exp $ */
2 1.1 tsubai
3 1.1 tsubai /*
4 1.1 tsubai * Copyright 1991-1998 by Open Software Foundation, Inc.
5 1.1 tsubai * All Rights Reserved
6 1.1 tsubai *
7 1.1 tsubai * Permission to use, copy, modify, and distribute this software and
8 1.1 tsubai * its documentation for any purpose and without fee is hereby granted,
9 1.1 tsubai * provided that the above copyright notice appears in all copies and
10 1.1 tsubai * that both the copyright notice and this permission notice appear in
11 1.1 tsubai * supporting documentation.
12 1.1 tsubai *
13 1.1 tsubai * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
14 1.1 tsubai * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
15 1.1 tsubai * FOR A PARTICULAR PURPOSE.
16 1.1 tsubai *
17 1.1 tsubai * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
18 1.1 tsubai * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
19 1.1 tsubai * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
20 1.1 tsubai * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
21 1.1 tsubai * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 1.1 tsubai */
23 1.1 tsubai
24 1.1 tsubai /* -------------------------------------------------------------------- */
25 1.1 tsubai /* Heathrow (F)eature (C)ontrol (R)egister Addresses */
26 1.1 tsubai /* -------------------------------------------------------------------- */
27 1.1 tsubai #define EnetEnable 0x60000000 /* enable Enet Xcvr/Controller */
28 1.1 tsubai #define ResetEnetCell 0x80000000 /* reset Enet cell */
29 1.1 tsubai
30 1.1 tsubai /* -------------------------------------------------------------------- */
31 1.1 tsubai /* BigMac Register Numbers & Bit Assignments */
32 1.1 tsubai /* -------------------------------------------------------------------- */
33 1.1 tsubai #define XIFC 0x0000
34 1.1 tsubai #define TxOutputEnable 0x0001
35 1.1 tsubai #define MIILoopbackBits 0x0006
36 1.1 tsubai #define MIIBufferEnable 0x0008
37 1.1 tsubai #define SQETestEnable 0x0010
38 1.1 tsubai #define LinkStatus 0x0100
39 1.1 tsubai #define TXFIFOCSR 0x0100
40 1.1 tsubai #define TxFIFOEnable 0x0001
41 1.1 tsubai #define TxFIFO128 0x0000
42 1.1 tsubai #define TXTH 0x0110
43 1.1 tsubai #define RXFIFOCSR 0x0120
44 1.1 tsubai #define RxFIFOEnable TxFIFOEnable
45 1.1 tsubai #define RxFIFO128 TxFIFO128
46 1.1 tsubai #define MEMADD 0x0130
47 1.1 tsubai #define MEMDATAHI 0x0140
48 1.1 tsubai #define MEMDATALO 0x0150
49 1.1 tsubai #define XCVRIF 0x0160
50 1.1 tsubai #define COLActiveLow 0x0002
51 1.1 tsubai #define SerialMode 0x0004
52 1.1 tsubai #define ClkBit 0x0008
53 1.1 tsubai #define CHIPID 0x0170
54 1.1 tsubai #define MIFCSR 0x0180
55 1.2 tsubai #define MIFDC 0x0001 /* MII clock */
56 1.2 tsubai #define MIFDO 0x0002 /* MII data out */
57 1.2 tsubai #define MIFDIR 0x0004 /* MII direction (1: write) */
58 1.2 tsubai #define MIFDI 0x0008 /* MII data in */
59 1.1 tsubai #define SROMCSR 0x0190
60 1.1 tsubai #define TXPNTR 0x01A0
61 1.1 tsubai #define RXPNTR 0x01B0
62 1.1 tsubai #define STATUS 0x0200
63 1.1 tsubai #define INTDISABLE 0x0210
64 1.1 tsubai #define IntFrameReceived 0x0001
65 1.1 tsubai #define IntRxFrameCntExp 0x0002
66 1.1 tsubai #define IntRxAlignCntExp 0x0004
67 1.1 tsubai #define IntRxCRCCntExp 0x0008
68 1.1 tsubai #define IntRxLenCntExp 0x0010
69 1.1 tsubai #define IntRxOverFlow 0x0020
70 1.1 tsubai #define IntRxCodeViolation 0x0040
71 1.1 tsubai #define IntSQETestError 0x0080
72 1.1 tsubai #define IntFrameSent 0x0100
73 1.1 tsubai #define IntTxUnderrun 0x0200
74 1.1 tsubai #define IntTxMaxSizeError 0x0400
75 1.1 tsubai #define IntTxNormalCollExp 0x0800
76 1.1 tsubai #define IntTxExcessCollExp 0x1000
77 1.1 tsubai #define IntTxLateCollExp 0x2000
78 1.1 tsubai #define IntTxNetworkCollExp 0x4000
79 1.1 tsubai #define IntTxDeferTimerExp 0x8000
80 1.1 tsubai #define NormalIntEvents ~(IntFrameSent)
81 1.1 tsubai #define NoEventsMask 0xFFFF
82 1.1 tsubai
83 1.1 tsubai #define TxNeverGiveUp 0x0400
84 1.1 tsubai #define TXRST 0x0420
85 1.1 tsubai #define TxResetBit 0x0001
86 1.1 tsubai #define TXCFG 0x0430
87 1.1 tsubai #define TxMACEnable 0x0001
88 1.1 tsubai #define TxThreshold 0x0004
89 1.2 tsubai #define TxFullDuplex 0x0200
90 1.1 tsubai #define IPG1 0x0440
91 1.1 tsubai #define IPG2 0x0450
92 1.1 tsubai #define ALIMIT 0x0460
93 1.1 tsubai #define SLOT 0x0470
94 1.1 tsubai #define PALEN 0x0480
95 1.1 tsubai #define PAPAT 0x0490
96 1.1 tsubai #define TXSFD 0x04A0
97 1.1 tsubai #define JAM 0x04B0
98 1.1 tsubai #define TXMAX 0x04C0
99 1.1 tsubai #define TXMIN 0x04D0
100 1.1 tsubai #define PAREG 0x04E0
101 1.1 tsubai #define DCNT 0x04F0
102 1.1 tsubai #define NCCNT 0x0500
103 1.1 tsubai #define NTCNT 0x0510
104 1.1 tsubai #define EXCNT 0x0520
105 1.1 tsubai #define LTCNT 0x0530
106 1.1 tsubai #define RSEED 0x0540
107 1.1 tsubai #define TXSM 0x0550
108 1.1 tsubai #define RXRST 0x0620
109 1.1 tsubai #define RxResetValue 0x0000
110 1.1 tsubai #define RXCFG 0x0630
111 1.1 tsubai #define RxMACEnable 0x0001
112 1.1 tsubai #define ReservedValue 0x0004
113 1.1 tsubai #define RxPromiscEnable 0x0040
114 1.1 tsubai #define RxCRCEnable 0x0100
115 1.1 tsubai #define RxRejectOwnPackets 0x0200
116 1.1 tsubai #define RxHashFilterEnable 0x0800
117 1.1 tsubai #define RxAddrFilterEnable 0x1000
118 1.1 tsubai #define RXMAX 0x0640
119 1.1 tsubai #define RXMIN 0x0650
120 1.1 tsubai #define MADD2 0x0660
121 1.1 tsubai #define MADD1 0x0670
122 1.1 tsubai #define MADD0 0x0680
123 1.1 tsubai #define FRCNT 0x0690
124 1.1 tsubai #define LECNT 0x06A0
125 1.1 tsubai #define AECNT 0x06B0
126 1.1 tsubai #define FECNT 0x06C0
127 1.1 tsubai #define RXSM 0x06D0
128 1.1 tsubai #define RXCV 0x06E0
129 1.1 tsubai #define HASH3 0x0700
130 1.1 tsubai #define HASH2 0x0710
131 1.1 tsubai #define HASH1 0x0720
132 1.1 tsubai #define HASH0 0x0730
133 1.1 tsubai #define AFR2 0x0740
134 1.1 tsubai #define AFR1 0x0750
135 1.1 tsubai #define AFR0 0x0760
136 1.1 tsubai #define AFCR 0x0770
137 1.1 tsubai #define EnableAllCompares 0x0fff
138 1.1 tsubai
139 1.1 tsubai /* -------------------------------------------------------------------- */
140 1.1 tsubai /* Misc. Bit definitions for BMac Status word */
141 1.1 tsubai /* -------------------------------------------------------------------- */
142 1.1 tsubai #define RxAbortBit 0x8000 /* status bit in BMac status for rx packets */
143 1.1 tsubai #define RxLengthMask 0x3FFF /* bits that determine length of rx packets */
144 1.1 tsubai
145 1.1 tsubai #define NETWORK_BUFSIZE (ETHERMAXPACKET + ETHERCRC + 2)
146