if_mc.c revision 1.13.16.1
1 /* $NetBSD: if_mc.c,v 1.13.16.1 2008/10/05 20:11:26 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym (at) bga.com> 5 * All rights reserved. 6 * 7 * Portions of this code are based on code by Denton Gentry <denny1 (at) home.com> 8 * and Yanagisawa Takeshi <yanagisw (at) aa.ap.titech.ac.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 /* 32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra 33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940 34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem 35 * Controller) for DMA to and from the MACE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_mc.c,v 1.13.16.1 2008/10/05 20:11:26 mjf Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/socket.h> 45 #include <sys/systm.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <dev/ofw/openfirm.h> 54 55 #include <machine/bus.h> 56 #include <machine/autoconf.h> 57 #include <machine/pio.h> 58 59 #include <macppc/dev/am79c950reg.h> 60 #include <macppc/dev/if_mcvar.h> 61 62 #define MC_BUFSIZE 0x800 63 64 hide int mc_match __P((struct device *, struct cfdata *, void *)); 65 hide void mc_attach __P((struct device *, struct device *, void *)); 66 hide void mc_init __P((struct mc_softc *sc)); 67 hide void mc_putpacket __P((struct mc_softc *sc, u_int len)); 68 hide int mc_dmaintr __P((void *arg)); 69 hide void mc_reset_rxdma __P((struct mc_softc *sc)); 70 hide void mc_reset_txdma __P((struct mc_softc *sc)); 71 hide void mc_select_utp __P((struct mc_softc *sc)); 72 hide void mc_select_aui __P((struct mc_softc *sc)); 73 hide int mc_mediachange __P((struct mc_softc *sc)); 74 hide void mc_mediastatus __P((struct mc_softc *sc, struct ifmediareq *)); 75 76 int mc_supmedia[] = { 77 IFM_ETHER | IFM_10_T, 78 IFM_ETHER | IFM_10_5, 79 /*IFM_ETHER | IFM_AUTO,*/ 80 }; 81 82 #define N_SUPMEDIA (sizeof(mc_supmedia) / sizeof(int)); 83 84 CFATTACH_DECL(mc, sizeof(struct mc_softc), 85 mc_match, mc_attach, NULL, NULL); 86 87 hide int 88 mc_match(parent, cf, aux) 89 struct device *parent; 90 struct cfdata *cf; 91 void *aux; 92 { 93 struct confargs *ca = aux; 94 95 if (strcmp(ca->ca_name, "mace") != 0) 96 return 0; 97 98 /* requires 6 regs */ 99 if (ca->ca_nreg / sizeof(int) != 6) 100 return 0; 101 102 /* requires 3 intrs */ 103 if (ca->ca_nintr / sizeof(int) != 3) 104 return 0; 105 106 return 1; 107 } 108 109 hide void 110 mc_attach(parent, self, aux) 111 struct device *parent, *self; 112 void *aux; 113 { 114 struct confargs *ca = aux; 115 struct mc_softc *sc = (struct mc_softc *)self; 116 u_int8_t myaddr[ETHER_ADDR_LEN]; 117 u_int *reg; 118 119 sc->sc_node = ca->ca_node; 120 sc->sc_regt = ca->ca_tag; 121 122 reg = ca->ca_reg; 123 reg[0] += ca->ca_baseaddr; 124 reg[2] += ca->ca_baseaddr; 125 reg[4] += ca->ca_baseaddr; 126 127 sc->sc_txdma = mapiodev(reg[2], reg[3]); 128 sc->sc_rxdma = mapiodev(reg[4], reg[5]); 129 bus_space_map(sc->sc_regt, reg[0], reg[1], 0, &sc->sc_regh); 130 131 sc->sc_tail = 0; 132 sc->sc_txdmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 2); 133 sc->sc_rxdmacmd = (void *)dbdma_alloc(sizeof(dbdma_command_t) * 8); 134 memset(sc->sc_txdmacmd, 0, sizeof(dbdma_command_t) * 2); 135 memset(sc->sc_rxdmacmd, 0, sizeof(dbdma_command_t) * 8); 136 137 printf(": irq %d,%d,%d", 138 ca->ca_intr[0], ca->ca_intr[1], ca->ca_intr[2]); 139 140 if (OF_getprop(sc->sc_node, "local-mac-address", myaddr, 6) != 6) { 141 printf(": failed to get MAC address.\n"); 142 return; 143 } 144 145 /* allocate memory for transmit buffer and mark it non-cacheable */ 146 sc->sc_txbuf = malloc(PAGE_SIZE, M_DEVBUF, M_WAITOK); 147 sc->sc_txbuf_phys = kvtop(sc->sc_txbuf); 148 memset(sc->sc_txbuf, 0, PAGE_SIZE); 149 150 /* 151 * allocate memory for receive buffer and mark it non-cacheable 152 * XXX This should use the bus_dma interface, since the buffer 153 * needs to be physically contiguous. However, it seems that 154 * at least on my system, malloc() does allocate contiguous 155 * memory. If it's not, suggest reducing the number of buffers 156 * to 2, which will fit in one 4K page. 157 */ 158 sc->sc_rxbuf = malloc(MC_NPAGES * PAGE_SIZE, M_DEVBUF, M_WAITOK); 159 sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf); 160 memset(sc->sc_rxbuf, 0, MC_NPAGES * PAGE_SIZE); 161 162 if ((int)sc->sc_txbuf & PGOFSET) 163 printf("txbuf is not page-aligned\n"); 164 if ((int)sc->sc_rxbuf & PGOFSET) 165 printf("rxbuf is not page-aligned\n"); 166 167 sc->sc_bus_init = mc_init; 168 sc->sc_putpacket = mc_putpacket; 169 170 171 /* disable receive DMA */ 172 dbdma_reset(sc->sc_rxdma); 173 174 /* disable transmit DMA */ 175 dbdma_reset(sc->sc_txdma); 176 177 /* install interrupt handlers */ 178 /*intr_establish(ca->ca_intr[1], IST_EDGE, IPL_NET, mc_dmaintr, sc);*/ 179 intr_establish(ca->ca_intr[2], IST_EDGE, IPL_NET, mc_dmaintr, sc); 180 intr_establish(ca->ca_intr[0], IST_EDGE, IPL_NET, mcintr, sc); 181 182 sc->sc_biucc = XMTSP_64; 183 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 184 XMTBRST | RCVBRST; 185 /*sc->sc_plscc = PORTSEL_10BT;*/ 186 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 187 188 /* mcsetup returns 1 if something fails */ 189 if (mcsetup(sc, myaddr)) { 190 printf("mcsetup returns non zero\n"); 191 return; 192 } 193 #ifdef NOTYET 194 sc->sc_mediachange = mc_mediachange; 195 sc->sc_mediastatus = mc_mediastatus; 196 sc->sc_supmedia = mc_supmedia; 197 sc->sc_nsupmedia = N_SUPMEDIA; 198 sc->sc_defaultmedia = IFM_ETHER | IFM_10_T; 199 #endif 200 } 201 202 /* Bus-specific initialization */ 203 hide void 204 mc_init(sc) 205 struct mc_softc *sc; 206 { 207 mc_reset_rxdma(sc); 208 mc_reset_txdma(sc); 209 } 210 211 hide void 212 mc_putpacket(sc, len) 213 struct mc_softc *sc; 214 u_int len; 215 { 216 dbdma_command_t *cmd = sc->sc_txdmacmd; 217 218 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_phys, 219 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 220 221 dbdma_start(sc->sc_txdma, sc->sc_txdmacmd); 222 } 223 224 /* 225 * Interrupt handler for the MACE DMA completion interrupts 226 */ 227 int 228 mc_dmaintr(arg) 229 void *arg; 230 { 231 struct mc_softc *sc = arg; 232 int status, offset, statoff; 233 int datalen, resid; 234 int i, n; 235 dbdma_command_t *cmd; 236 237 /* We've received some packets from the MACE */ 238 239 /* Loop through, processing each of the packets */ 240 i = sc->sc_tail; 241 for (n = 0; n < MC_RXDMABUFS; n++, i++) { 242 if (i == MC_RXDMABUFS) 243 i = 0; 244 245 cmd = &sc->sc_rxdmacmd[i]; 246 /* flushcache(cmd, sizeof(dbdma_command_t)); */ 247 status = in16rb(&cmd->d_status); 248 resid = in16rb(&cmd->d_resid); 249 250 /*if ((status & D_ACTIVE) == 0)*/ 251 if ((status & 0x40) == 0) 252 continue; 253 254 #if 1 255 if (in16rb(&cmd->d_count) != ETHERMTU + 22) 256 printf("bad d_count\n"); 257 #endif 258 259 datalen = in16rb(&cmd->d_count) - resid; 260 datalen -= 4; /* 4 == status bytes */ 261 262 if (datalen < 4 + sizeof(struct ether_header)) { 263 printf("short packet len=%d\n", datalen); 264 /* continue; */ 265 goto next; 266 } 267 268 offset = i * MC_BUFSIZE; 269 statoff = offset + datalen; 270 271 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 272 __asm volatile("eieio"); 273 274 /* flushcache(sc->sc_rxbuf + offset, datalen + 4); */ 275 276 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0]; 277 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1]; 278 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2]; 279 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3]; 280 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset; 281 282 mc_rint(sc); 283 284 next: 285 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 286 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 287 __asm volatile("eieio"); 288 cmd->d_status = 0; 289 cmd->d_resid = 0; 290 sc->sc_tail = i + 1; 291 } 292 293 dbdma_continue(sc->sc_rxdma); 294 295 return 1; 296 } 297 298 hide void 299 mc_reset_rxdma(sc) 300 struct mc_softc *sc; 301 { 302 dbdma_command_t *cmd = sc->sc_rxdmacmd; 303 dbdma_regmap_t *dmareg = sc->sc_rxdma; 304 int i; 305 u_int8_t maccc; 306 307 /* Disable receiver, reset the DMA channels */ 308 maccc = NIC_GET(sc, MACE_MACCC); 309 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 310 311 dbdma_reset(dmareg); 312 313 for (i = 0; i < MC_RXDMABUFS; i++) { 314 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, ETHERMTU + 22, 315 sc->sc_rxbuf_phys + MC_BUFSIZE * i, DBDMA_INT_ALWAYS, 316 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 317 cmd++; 318 } 319 320 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 321 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 322 out32rb(&cmd->d_cmddep, kvtop((void *)sc->sc_rxdmacmd)); 323 cmd++; 324 325 dbdma_start(dmareg, sc->sc_rxdmacmd); 326 327 sc->sc_tail = 0; 328 329 /* Reenable receiver, reenable DMA */ 330 NIC_PUT(sc, MACE_MACCC, maccc); 331 } 332 333 hide void 334 mc_reset_txdma(sc) 335 struct mc_softc *sc; 336 { 337 dbdma_command_t *cmd = sc->sc_txdmacmd; 338 dbdma_regmap_t *dmareg = sc->sc_txdma; 339 u_int8_t maccc; 340 341 /* disable transmitter */ 342 maccc = NIC_GET(sc, MACE_MACCC); 343 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 344 345 dbdma_reset(dmareg); 346 347 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_phys, 348 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 349 cmd++; 350 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 351 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 352 353 out32rb(&dmareg->d_cmdptrhi, 0); 354 out32rb(&dmareg->d_cmdptrlo, kvtop((void *)sc->sc_txdmacmd)); 355 356 /* restore old value */ 357 NIC_PUT(sc, MACE_MACCC, maccc); 358 } 359 360 void 361 mc_select_utp(sc) 362 struct mc_softc *sc; 363 { 364 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 365 } 366 367 void 368 mc_select_aui(sc) 369 struct mc_softc *sc; 370 { 371 sc->sc_plscc = PORTSEL_AUI; 372 } 373 374 int 375 mc_mediachange(sc) 376 struct mc_softc *sc; 377 { 378 struct ifmedia *ifm = &sc->sc_media; 379 380 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 381 return EINVAL; 382 383 switch (IFM_SUBTYPE(ifm->ifm_media)) { 384 385 case IFM_10_T: 386 mc_select_utp(sc); 387 break; 388 389 case IFM_10_5: 390 mc_select_aui(sc); 391 break; 392 393 default: 394 return EINVAL; 395 } 396 397 return 0; 398 } 399 400 void 401 mc_mediastatus(sc, ifmr) 402 struct mc_softc *sc; 403 struct ifmediareq *ifmr; 404 { 405 if (sc->sc_plscc == PORTSEL_AUI) 406 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 407 else 408 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 409 } 410
Indexes created Mon Oct 13 01:09:56 GMT 2025