if_mc.c revision 1.16
1 /* $NetBSD: if_mc.c,v 1.16 2009/03/14 15:36:09 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym (at) bga.com> 5 * All rights reserved. 6 * 7 * Portions of this code are based on code by Denton Gentry <denny1 (at) home.com> 8 * and Yanagisawa Takeshi <yanagisw (at) aa.ap.titech.ac.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 /* 32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra 33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940 34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem 35 * Controller) for DMA to and from the MACE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_mc.c,v 1.16 2009/03/14 15:36:09 dsl Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/socket.h> 45 #include <sys/systm.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <dev/ofw/openfirm.h> 54 55 #include <machine/bus.h> 56 #include <machine/autoconf.h> 57 #include <machine/pio.h> 58 59 #include <macppc/dev/am79c950reg.h> 60 #include <macppc/dev/if_mcvar.h> 61 62 #define MC_BUFSIZE 0x800 63 64 hide int mc_match(struct device *, struct cfdata *, void *); 65 hide void mc_attach(struct device *, struct device *, void *); 66 hide void mc_init(struct mc_softc *sc); 67 hide void mc_putpacket(struct mc_softc *sc, u_int len); 68 hide int mc_dmaintr(void *arg); 69 hide void mc_reset_rxdma(struct mc_softc *sc); 70 hide void mc_reset_txdma(struct mc_softc *sc); 71 hide void mc_select_utp(struct mc_softc *sc); 72 hide void mc_select_aui(struct mc_softc *sc); 73 hide int mc_mediachange(struct mc_softc *sc); 74 hide void mc_mediastatus(struct mc_softc *sc, struct ifmediareq *); 75 76 int mc_supmedia[] = { 77 IFM_ETHER | IFM_10_T, 78 IFM_ETHER | IFM_10_5, 79 /*IFM_ETHER | IFM_AUTO,*/ 80 }; 81 82 #define N_SUPMEDIA (sizeof(mc_supmedia) / sizeof(int)); 83 84 CFATTACH_DECL(mc, sizeof(struct mc_softc), 85 mc_match, mc_attach, NULL, NULL); 86 87 hide int 88 mc_match(struct device *parent, struct cfdata *cf, void *aux) 89 { 90 struct confargs *ca = aux; 91 92 if (strcmp(ca->ca_name, "mace") != 0) 93 return 0; 94 95 /* requires 6 regs */ 96 if (ca->ca_nreg / sizeof(int) != 6) 97 return 0; 98 99 /* requires 3 intrs */ 100 if (ca->ca_nintr / sizeof(int) != 3) 101 return 0; 102 103 return 1; 104 } 105 106 hide void 107 mc_attach(parent, self, aux) 108 struct device *parent, *self; 109 void *aux; 110 { 111 struct confargs *ca = aux; 112 struct mc_softc *sc = (struct mc_softc *)self; 113 u_int8_t myaddr[ETHER_ADDR_LEN]; 114 u_int *reg; 115 116 sc->sc_node = ca->ca_node; 117 sc->sc_regt = ca->ca_tag; 118 119 reg = ca->ca_reg; 120 reg[0] += ca->ca_baseaddr; 121 reg[2] += ca->ca_baseaddr; 122 reg[4] += ca->ca_baseaddr; 123 124 sc->sc_txdma = mapiodev(reg[2], reg[3]); 125 sc->sc_rxdma = mapiodev(reg[4], reg[5]); 126 bus_space_map(sc->sc_regt, reg[0], reg[1], 0, &sc->sc_regh); 127 128 sc->sc_tail = 0; 129 sc->sc_txdmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 2); 130 sc->sc_rxdmacmd = (void *)dbdma_alloc(sizeof(dbdma_command_t) * 8); 131 memset(sc->sc_txdmacmd, 0, sizeof(dbdma_command_t) * 2); 132 memset(sc->sc_rxdmacmd, 0, sizeof(dbdma_command_t) * 8); 133 134 printf(": irq %d,%d,%d", 135 ca->ca_intr[0], ca->ca_intr[1], ca->ca_intr[2]); 136 137 if (OF_getprop(sc->sc_node, "local-mac-address", myaddr, 6) != 6) { 138 printf(": failed to get MAC address.\n"); 139 return; 140 } 141 142 /* allocate memory for transmit buffer and mark it non-cacheable */ 143 sc->sc_txbuf = malloc(PAGE_SIZE, M_DEVBUF, M_WAITOK); 144 sc->sc_txbuf_phys = kvtop(sc->sc_txbuf); 145 memset(sc->sc_txbuf, 0, PAGE_SIZE); 146 147 /* 148 * allocate memory for receive buffer and mark it non-cacheable 149 * XXX This should use the bus_dma interface, since the buffer 150 * needs to be physically contiguous. However, it seems that 151 * at least on my system, malloc() does allocate contiguous 152 * memory. If it's not, suggest reducing the number of buffers 153 * to 2, which will fit in one 4K page. 154 */ 155 sc->sc_rxbuf = malloc(MC_NPAGES * PAGE_SIZE, M_DEVBUF, M_WAITOK); 156 sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf); 157 memset(sc->sc_rxbuf, 0, MC_NPAGES * PAGE_SIZE); 158 159 if ((int)sc->sc_txbuf & PGOFSET) 160 printf("txbuf is not page-aligned\n"); 161 if ((int)sc->sc_rxbuf & PGOFSET) 162 printf("rxbuf is not page-aligned\n"); 163 164 sc->sc_bus_init = mc_init; 165 sc->sc_putpacket = mc_putpacket; 166 167 168 /* disable receive DMA */ 169 dbdma_reset(sc->sc_rxdma); 170 171 /* disable transmit DMA */ 172 dbdma_reset(sc->sc_txdma); 173 174 /* install interrupt handlers */ 175 /*intr_establish(ca->ca_intr[1], IST_EDGE, IPL_NET, mc_dmaintr, sc);*/ 176 intr_establish(ca->ca_intr[2], IST_EDGE, IPL_NET, mc_dmaintr, sc); 177 intr_establish(ca->ca_intr[0], IST_EDGE, IPL_NET, mcintr, sc); 178 179 sc->sc_biucc = XMTSP_64; 180 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 181 XMTBRST | RCVBRST; 182 /*sc->sc_plscc = PORTSEL_10BT;*/ 183 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 184 185 /* mcsetup returns 1 if something fails */ 186 if (mcsetup(sc, myaddr)) { 187 printf("mcsetup returns non zero\n"); 188 return; 189 } 190 #ifdef NOTYET 191 sc->sc_mediachange = mc_mediachange; 192 sc->sc_mediastatus = mc_mediastatus; 193 sc->sc_supmedia = mc_supmedia; 194 sc->sc_nsupmedia = N_SUPMEDIA; 195 sc->sc_defaultmedia = IFM_ETHER | IFM_10_T; 196 #endif 197 } 198 199 /* Bus-specific initialization */ 200 hide void 201 mc_init(struct mc_softc *sc) 202 { 203 mc_reset_rxdma(sc); 204 mc_reset_txdma(sc); 205 } 206 207 hide void 208 mc_putpacket(struct mc_softc *sc, u_int len) 209 { 210 dbdma_command_t *cmd = sc->sc_txdmacmd; 211 212 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_phys, 213 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 214 215 dbdma_start(sc->sc_txdma, sc->sc_txdmacmd); 216 } 217 218 /* 219 * Interrupt handler for the MACE DMA completion interrupts 220 */ 221 int 222 mc_dmaintr(void *arg) 223 { 224 struct mc_softc *sc = arg; 225 int status, offset, statoff; 226 int datalen, resid; 227 int i, n; 228 dbdma_command_t *cmd; 229 230 /* We've received some packets from the MACE */ 231 232 /* Loop through, processing each of the packets */ 233 i = sc->sc_tail; 234 for (n = 0; n < MC_RXDMABUFS; n++, i++) { 235 if (i == MC_RXDMABUFS) 236 i = 0; 237 238 cmd = &sc->sc_rxdmacmd[i]; 239 /* flushcache(cmd, sizeof(dbdma_command_t)); */ 240 status = in16rb(&cmd->d_status); 241 resid = in16rb(&cmd->d_resid); 242 243 /*if ((status & D_ACTIVE) == 0)*/ 244 if ((status & 0x40) == 0) 245 continue; 246 247 #if 1 248 if (in16rb(&cmd->d_count) != ETHERMTU + 22) 249 printf("bad d_count\n"); 250 #endif 251 252 datalen = in16rb(&cmd->d_count) - resid; 253 datalen -= 4; /* 4 == status bytes */ 254 255 if (datalen < 4 + sizeof(struct ether_header)) { 256 printf("short packet len=%d\n", datalen); 257 /* continue; */ 258 goto next; 259 } 260 261 offset = i * MC_BUFSIZE; 262 statoff = offset + datalen; 263 264 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 265 __asm volatile("eieio"); 266 267 /* flushcache(sc->sc_rxbuf + offset, datalen + 4); */ 268 269 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0]; 270 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1]; 271 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2]; 272 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3]; 273 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset; 274 275 mc_rint(sc); 276 277 next: 278 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 279 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 280 __asm volatile("eieio"); 281 cmd->d_status = 0; 282 cmd->d_resid = 0; 283 sc->sc_tail = i + 1; 284 } 285 286 dbdma_continue(sc->sc_rxdma); 287 288 return 1; 289 } 290 291 hide void 292 mc_reset_rxdma(struct mc_softc *sc) 293 { 294 dbdma_command_t *cmd = sc->sc_rxdmacmd; 295 dbdma_regmap_t *dmareg = sc->sc_rxdma; 296 int i; 297 u_int8_t maccc; 298 299 /* Disable receiver, reset the DMA channels */ 300 maccc = NIC_GET(sc, MACE_MACCC); 301 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 302 303 dbdma_reset(dmareg); 304 305 for (i = 0; i < MC_RXDMABUFS; i++) { 306 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, ETHERMTU + 22, 307 sc->sc_rxbuf_phys + MC_BUFSIZE * i, DBDMA_INT_ALWAYS, 308 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 309 cmd++; 310 } 311 312 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 313 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 314 out32rb(&cmd->d_cmddep, kvtop((void *)sc->sc_rxdmacmd)); 315 cmd++; 316 317 dbdma_start(dmareg, sc->sc_rxdmacmd); 318 319 sc->sc_tail = 0; 320 321 /* Reenable receiver, reenable DMA */ 322 NIC_PUT(sc, MACE_MACCC, maccc); 323 } 324 325 hide void 326 mc_reset_txdma(struct mc_softc *sc) 327 { 328 dbdma_command_t *cmd = sc->sc_txdmacmd; 329 dbdma_regmap_t *dmareg = sc->sc_txdma; 330 u_int8_t maccc; 331 332 /* disable transmitter */ 333 maccc = NIC_GET(sc, MACE_MACCC); 334 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 335 336 dbdma_reset(dmareg); 337 338 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_phys, 339 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 340 cmd++; 341 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 342 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 343 344 out32rb(&dmareg->d_cmdptrhi, 0); 345 out32rb(&dmareg->d_cmdptrlo, kvtop((void *)sc->sc_txdmacmd)); 346 347 /* restore old value */ 348 NIC_PUT(sc, MACE_MACCC, maccc); 349 } 350 351 void 352 mc_select_utp(struct mc_softc *sc) 353 { 354 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 355 } 356 357 void 358 mc_select_aui(struct mc_softc *sc) 359 { 360 sc->sc_plscc = PORTSEL_AUI; 361 } 362 363 int 364 mc_mediachange(struct mc_softc *sc) 365 { 366 struct ifmedia *ifm = &sc->sc_media; 367 368 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 369 return EINVAL; 370 371 switch (IFM_SUBTYPE(ifm->ifm_media)) { 372 373 case IFM_10_T: 374 mc_select_utp(sc); 375 break; 376 377 case IFM_10_5: 378 mc_select_aui(sc); 379 break; 380 381 default: 382 return EINVAL; 383 } 384 385 return 0; 386 } 387 388 void 389 mc_mediastatus(struct mc_softc *sc, struct ifmediareq *ifmr) 390 { 391 if (sc->sc_plscc == PORTSEL_AUI) 392 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 393 else 394 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 395 } 396
Indexes created Tue Oct 14 00:09:49 GMT 2025