if_mc.c revision 1.25
1 /* $NetBSD: if_mc.c,v 1.25 2019/12/04 07:03:46 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym (at) bga.com> 5 * All rights reserved. 6 * 7 * Portions of this code are based on code by Denton Gentry <denny1 (at) home.com> 8 * and Yanagisawa Takeshi <yanagisw (at) aa.ap.titech.ac.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 /* 32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra 33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940 34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem 35 * Controller) for DMA to and from the MACE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_mc.c,v 1.25 2019/12/04 07:03:46 msaitoh Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/socket.h> 45 #include <sys/systm.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <dev/ofw/openfirm.h> 52 53 #include <sys/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/pio.h> 56 57 #include <macppc/dev/am79c950reg.h> 58 #include <macppc/dev/if_mcvar.h> 59 60 #define MC_BUFSIZE 0x800 61 62 hide int mc_match(device_t, cfdata_t, void *); 63 hide void mc_attach(device_t, device_t, void *); 64 hide void mc_init(struct mc_softc *); 65 hide void mc_putpacket(struct mc_softc *, u_int); 66 hide int mc_dmaintr(void *); 67 hide void mc_reset_rxdma(struct mc_softc *); 68 hide void mc_reset_txdma(struct mc_softc *); 69 hide void mc_select_utp(struct mc_softc *); 70 hide void mc_select_aui(struct mc_softc *); 71 hide int mc_mediachange(struct mc_softc *); 72 hide void mc_mediastatus(struct mc_softc *, struct ifmediareq *); 73 74 int mc_supmedia[] = { 75 IFM_ETHER | IFM_10_T, 76 IFM_ETHER | IFM_10_5, 77 /*IFM_ETHER | IFM_AUTO,*/ 78 }; 79 80 #define N_SUPMEDIA __arraycount(mc_supmedia) 81 82 CFATTACH_DECL_NEW(mc, sizeof(struct mc_softc), 83 mc_match, mc_attach, NULL, NULL); 84 85 hide int 86 mc_match(device_t parent, cfdata_t cf, void *aux) 87 { 88 struct confargs *ca = aux; 89 90 if (strcmp(ca->ca_name, "mace") != 0) 91 return 0; 92 93 /* requires 6 regs */ 94 if (ca->ca_nreg / sizeof(int) != 6) 95 return 0; 96 97 /* requires 3 intrs */ 98 if (ca->ca_nintr / sizeof(int) != 3) 99 return 0; 100 101 return 1; 102 } 103 104 hide void 105 mc_attach(device_t parent, device_t self, void *aux) 106 { 107 struct confargs *ca = aux; 108 struct mc_softc *sc = device_private(self); 109 uint8_t myaddr[ETHER_ADDR_LEN]; 110 u_int *reg; 111 112 sc->sc_dev = self; 113 sc->sc_node = ca->ca_node; 114 sc->sc_regt = ca->ca_tag; 115 116 reg = ca->ca_reg; 117 reg[0] += ca->ca_baseaddr; 118 reg[2] += ca->ca_baseaddr; 119 reg[4] += ca->ca_baseaddr; 120 121 sc->sc_txdma = mapiodev(reg[2], reg[3], false); 122 sc->sc_rxdma = mapiodev(reg[4], reg[5], false); 123 bus_space_map(sc->sc_regt, reg[0], reg[1], 0, &sc->sc_regh); 124 125 sc->sc_tail = 0; 126 sc->sc_txdmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 2, NULL); 127 sc->sc_rxdmacmd = (void *)dbdma_alloc(sizeof(dbdma_command_t) * 8, 128 NULL); 129 memset(sc->sc_txdmacmd, 0, sizeof(dbdma_command_t) * 2); 130 memset(sc->sc_rxdmacmd, 0, sizeof(dbdma_command_t) * 8); 131 132 printf(": irq %d,%d,%d", 133 ca->ca_intr[0], ca->ca_intr[1], ca->ca_intr[2]); 134 135 if (OF_getprop(sc->sc_node, "local-mac-address", myaddr, 6) != 6) { 136 printf(": failed to get MAC address.\n"); 137 return; 138 } 139 140 /* Allocate memory for transmit buffer and mark it non-cacheable */ 141 sc->sc_txbuf = malloc(PAGE_SIZE, M_DEVBUF, M_WAITOK); 142 sc->sc_txbuf_phys = kvtop(sc->sc_txbuf); 143 memset(sc->sc_txbuf, 0, PAGE_SIZE); 144 145 /* 146 * Allocate memory for receive buffer and mark it non-cacheable 147 * XXX This should use the bus_dma interface, since the buffer 148 * needs to be physically contiguous. However, it seems that 149 * at least on my system, malloc() does allocate contiguous 150 * memory. If it's not, suggest reducing the number of buffers 151 * to 2, which will fit in one 4K page. 152 */ 153 sc->sc_rxbuf = malloc(MC_NPAGES * PAGE_SIZE, M_DEVBUF, M_WAITOK); 154 sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf); 155 memset(sc->sc_rxbuf, 0, MC_NPAGES * PAGE_SIZE); 156 157 if ((int)sc->sc_txbuf & PGOFSET) 158 printf("txbuf is not page-aligned\n"); 159 if ((int)sc->sc_rxbuf & PGOFSET) 160 printf("rxbuf is not page-aligned\n"); 161 162 sc->sc_bus_init = mc_init; 163 sc->sc_putpacket = mc_putpacket; 164 165 /* Disable receive DMA */ 166 dbdma_reset(sc->sc_rxdma); 167 168 /* Disable transmit DMA */ 169 dbdma_reset(sc->sc_txdma); 170 171 /* Install interrupt handlers */ 172 /*intr_establish(ca->ca_intr[1], IST_EDGE, IPL_NET, mc_dmaintr, sc);*/ 173 intr_establish(ca->ca_intr[2], IST_EDGE, IPL_NET, mc_dmaintr, sc); 174 intr_establish(ca->ca_intr[0], IST_EDGE, IPL_NET, mcintr, sc); 175 176 sc->sc_biucc = XMTSP_64; 177 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 178 XMTBRST | RCVBRST; 179 /*sc->sc_plscc = PORTSEL_10BT;*/ 180 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 181 182 /* mcsetup returns 1 if something fails */ 183 if (mcsetup(sc, myaddr)) { 184 printf("mcsetup returns non zero\n"); 185 return; 186 } 187 #ifdef NOTYET 188 sc->sc_mediachange = mc_mediachange; 189 sc->sc_mediastatus = mc_mediastatus; 190 sc->sc_supmedia = mc_supmedia; 191 sc->sc_nsupmedia = N_SUPMEDIA; 192 sc->sc_defaultmedia = IFM_ETHER | IFM_10_T; 193 #endif 194 } 195 196 /* Bus-specific initialization */ 197 hide void 198 mc_init(struct mc_softc *sc) 199 { 200 mc_reset_rxdma(sc); 201 mc_reset_txdma(sc); 202 } 203 204 hide void 205 mc_putpacket(struct mc_softc *sc, u_int len) 206 { 207 dbdma_command_t *cmd = sc->sc_txdmacmd; 208 209 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_phys, 210 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 211 212 dbdma_start(sc->sc_txdma, sc->sc_txdmacmd); 213 } 214 215 /* 216 * Interrupt handler for the MACE DMA completion interrupts 217 */ 218 int 219 mc_dmaintr(void *arg) 220 { 221 struct mc_softc *sc = arg; 222 int status, offset, statoff; 223 int datalen, resid; 224 int i, n; 225 dbdma_command_t *cmd; 226 227 /* We've received some packets from the MACE */ 228 229 /* Loop through, processing each of the packets */ 230 i = sc->sc_tail; 231 for (n = 0; n < MC_RXDMABUFS; n++, i++) { 232 if (i == MC_RXDMABUFS) 233 i = 0; 234 235 cmd = &sc->sc_rxdmacmd[i]; 236 /* flushcache(cmd, sizeof(dbdma_command_t)); */ 237 status = in16rb(&cmd->d_status); 238 resid = in16rb(&cmd->d_resid); 239 240 /*if ((status & D_ACTIVE) == 0)*/ 241 if ((status & 0x40) == 0) 242 continue; 243 244 #if 1 245 if (in16rb(&cmd->d_count) != ETHERMTU + 22) 246 printf("bad d_count\n"); 247 #endif 248 249 datalen = in16rb(&cmd->d_count) - resid; 250 datalen -= 4; /* 4 == status bytes */ 251 252 if (datalen < 4 + sizeof(struct ether_header)) { 253 printf("short packet len=%d\n", datalen); 254 /* continue; */ 255 goto next; 256 } 257 258 offset = i * MC_BUFSIZE; 259 statoff = offset + datalen; 260 261 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 262 __asm volatile("eieio"); 263 264 /* flushcache(sc->sc_rxbuf + offset, datalen + 4); */ 265 266 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0]; 267 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1]; 268 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2]; 269 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3]; 270 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset; 271 272 mc_rint(sc); 273 274 next: 275 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 276 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 277 __asm volatile("eieio"); 278 cmd->d_status = 0; 279 cmd->d_resid = 0; 280 sc->sc_tail = i + 1; 281 } 282 283 dbdma_continue(sc->sc_rxdma); 284 285 return 1; 286 } 287 288 hide void 289 mc_reset_rxdma(struct mc_softc *sc) 290 { 291 dbdma_command_t *cmd = sc->sc_rxdmacmd; 292 dbdma_regmap_t *dmareg = sc->sc_rxdma; 293 int i; 294 uint8_t maccc; 295 296 /* Disable receiver, reset the DMA channels */ 297 maccc = NIC_GET(sc, MACE_MACCC); 298 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 299 300 dbdma_reset(dmareg); 301 302 for (i = 0; i < MC_RXDMABUFS; i++) { 303 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, ETHERMTU + 22, 304 sc->sc_rxbuf_phys + MC_BUFSIZE * i, DBDMA_INT_ALWAYS, 305 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 306 cmd++; 307 } 308 309 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 310 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 311 out32rb(&cmd->d_cmddep, kvtop((void *)sc->sc_rxdmacmd)); 312 cmd++; 313 314 dbdma_start(dmareg, sc->sc_rxdmacmd); 315 316 sc->sc_tail = 0; 317 318 /* Reenable receiver, reenable DMA */ 319 NIC_PUT(sc, MACE_MACCC, maccc); 320 } 321 322 hide void 323 mc_reset_txdma(struct mc_softc *sc) 324 { 325 dbdma_command_t *cmd = sc->sc_txdmacmd; 326 dbdma_regmap_t *dmareg = sc->sc_txdma; 327 uint8_t maccc; 328 329 /* Disable transmitter */ 330 maccc = NIC_GET(sc, MACE_MACCC); 331 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 332 333 dbdma_reset(dmareg); 334 335 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_phys, 336 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 337 cmd++; 338 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 339 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 340 341 out32rb(&dmareg->d_cmdptrhi, 0); 342 out32rb(&dmareg->d_cmdptrlo, kvtop((void *)sc->sc_txdmacmd)); 343 344 /* Restore old value */ 345 NIC_PUT(sc, MACE_MACCC, maccc); 346 } 347 348 void 349 mc_select_utp(struct mc_softc *sc) 350 { 351 352 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 353 } 354 355 void 356 mc_select_aui(struct mc_softc *sc) 357 { 358 359 sc->sc_plscc = PORTSEL_AUI; 360 } 361 362 int 363 mc_mediachange(struct mc_softc *sc) 364 { 365 struct ifmedia_entry *ife = sc->sc_media.ifm_cur; 366 367 if (IFM_TYPE(ife->ifm_media) != IFM_ETHER) 368 return EINVAL; 369 370 switch (IFM_SUBTYPE(ife->ifm_media)) { 371 372 case IFM_10_T: 373 mc_select_utp(sc); 374 break; 375 376 case IFM_10_5: 377 mc_select_aui(sc); 378 break; 379 380 default: 381 return EINVAL; 382 } 383 384 return 0; 385 } 386 387 void 388 mc_mediastatus(struct mc_softc *sc, struct ifmediareq *ifmr) 389 { 390 391 if (sc->sc_plscc == PORTSEL_AUI) 392 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 393 else 394 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 395 } 396
Indexes created Mon Oct 13 08:09:50 GMT 2025