if_mc.c revision 1.8.2.1
1 /* $NetBSD: if_mc.c,v 1.8.2.1 2004/08/03 10:37:20 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym (at) bga.com> 5 * All rights reserved. 6 * 7 * Portions of this code are based on code by Denton Gentry <denny1 (at) home.com> 8 * and Yanagisawa Takeshi <yanagisw (at) aa.ap.titech.ac.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 /* 32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra 33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940 34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem 35 * Controller) for DMA to and from the MACE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_mc.c,v 1.8.2.1 2004/08/03 10:37:20 skrll Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/socket.h> 45 #include <sys/systm.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <dev/ofw/openfirm.h> 54 55 #include <machine/pio.h> 56 #include <machine/bus.h> 57 #include <machine/autoconf.h> 58 59 #include <macppc/dev/am79c950reg.h> 60 #include <macppc/dev/if_mcvar.h> 61 62 #define MC_BUFSIZE 0x800 63 64 hide int mc_match __P((struct device *, struct cfdata *, void *)); 65 hide void mc_attach __P((struct device *, struct device *, void *)); 66 hide void mc_init __P((struct mc_softc *sc)); 67 hide void mc_putpacket __P((struct mc_softc *sc, u_int len)); 68 hide int mc_dmaintr __P((void *arg)); 69 hide void mc_reset_rxdma __P((struct mc_softc *sc)); 70 hide void mc_reset_txdma __P((struct mc_softc *sc)); 71 hide void mc_select_utp __P((struct mc_softc *sc)); 72 hide void mc_select_aui __P((struct mc_softc *sc)); 73 hide int mc_mediachange __P((struct mc_softc *sc)); 74 hide void mc_mediastatus __P((struct mc_softc *sc, struct ifmediareq *)); 75 76 int mc_supmedia[] = { 77 IFM_ETHER | IFM_10_T, 78 IFM_ETHER | IFM_10_5, 79 /*IFM_ETHER | IFM_AUTO,*/ 80 }; 81 82 #define N_SUPMEDIA (sizeof(mc_supmedia) / sizeof(int)); 83 84 CFATTACH_DECL(mc, sizeof(struct mc_softc), 85 mc_match, mc_attach, NULL, NULL); 86 87 hide int 88 mc_match(parent, cf, aux) 89 struct device *parent; 90 struct cfdata *cf; 91 void *aux; 92 { 93 struct confargs *ca = aux; 94 95 if (strcmp(ca->ca_name, "mace") != 0) 96 return 0; 97 98 /* requires 6 regs */ 99 if (ca->ca_nreg / sizeof(int) != 6) 100 return 0; 101 102 /* requires 3 intrs */ 103 if (ca->ca_nintr / sizeof(int) != 3) 104 return 0; 105 106 return 1; 107 } 108 109 hide void 110 mc_attach(parent, self, aux) 111 struct device *parent, *self; 112 void *aux; 113 { 114 struct confargs *ca = aux; 115 struct mc_softc *sc = (struct mc_softc *)self; 116 u_int8_t myaddr[ETHER_ADDR_LEN]; 117 u_int *reg; 118 119 sc->sc_node = ca->ca_node; 120 121 reg = ca->ca_reg; 122 reg[0] += ca->ca_baseaddr; 123 reg[2] += ca->ca_baseaddr; 124 reg[4] += ca->ca_baseaddr; 125 126 sc->sc_txdma = mapiodev(reg[2], reg[3]); 127 sc->sc_rxdma = mapiodev(reg[4], reg[5]); 128 bus_space_map(sc->sc_regt, reg[0], reg[1], 0, &sc->sc_regh); 129 /* XXX sc_regt is uninitialized */ 130 sc->sc_tail = 0; 131 sc->sc_txdmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 2); 132 sc->sc_rxdmacmd = (void *)dbdma_alloc(sizeof(dbdma_command_t) * 8); 133 memset(sc->sc_txdmacmd, 0, sizeof(dbdma_command_t) * 2); 134 memset(sc->sc_rxdmacmd, 0, sizeof(dbdma_command_t) * 8); 135 136 printf(": irq %d,%d,%d", 137 ca->ca_intr[0], ca->ca_intr[1], ca->ca_intr[2]); 138 139 if (OF_getprop(sc->sc_node, "local-mac-address", myaddr, 6) != 6) { 140 printf(": failed to get MAC address.\n"); 141 return; 142 } 143 144 /* allocate memory for transmit buffer and mark it non-cacheable */ 145 sc->sc_txbuf = malloc(PAGE_SIZE, M_DEVBUF, M_WAITOK); 146 sc->sc_txbuf_phys = kvtop(sc->sc_txbuf); 147 memset(sc->sc_txbuf, 0, PAGE_SIZE); 148 149 /* 150 * allocate memory for receive buffer and mark it non-cacheable 151 * XXX This should use the bus_dma interface, since the buffer 152 * needs to be physically contiguous. However, it seems that 153 * at least on my system, malloc() does allocate contiguous 154 * memory. If it's not, suggest reducing the number of buffers 155 * to 2, which will fit in one 4K page. 156 */ 157 sc->sc_rxbuf = malloc(MC_NPAGES * PAGE_SIZE, M_DEVBUF, M_WAITOK); 158 sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf); 159 memset(sc->sc_rxbuf, 0, MC_NPAGES * PAGE_SIZE); 160 161 if ((int)sc->sc_txbuf & PGOFSET) 162 printf("txbuf is not page-aligned\n"); 163 if ((int)sc->sc_rxbuf & PGOFSET) 164 printf("rxbuf is not page-aligned\n"); 165 166 sc->sc_bus_init = mc_init; 167 sc->sc_putpacket = mc_putpacket; 168 169 170 /* disable receive DMA */ 171 dbdma_reset(sc->sc_rxdma); 172 173 /* disable transmit DMA */ 174 dbdma_reset(sc->sc_txdma); 175 176 /* install interrupt handlers */ 177 /*intr_establish(ca->ca_intr[1], IST_LEVEL, IPL_NET, mc_dmaintr, sc);*/ 178 intr_establish(ca->ca_intr[2], IST_LEVEL, IPL_NET, mc_dmaintr, sc); 179 intr_establish(ca->ca_intr[0], IST_LEVEL, IPL_NET, mcintr, sc); 180 181 sc->sc_biucc = XMTSP_64; 182 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 183 XMTBRST | RCVBRST; 184 /*sc->sc_plscc = PORTSEL_10BT;*/ 185 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 186 187 /* mcsetup returns 1 if something fails */ 188 if (mcsetup(sc, myaddr)) { 189 printf("mcsetup returns non zero\n"); 190 return; 191 } 192 #ifdef NOTYET 193 sc->sc_mediachange = mc_mediachange; 194 sc->sc_mediastatus = mc_mediastatus; 195 sc->sc_supmedia = mc_supmedia; 196 sc->sc_nsupmedia = N_SUPMEDIA; 197 sc->sc_defaultmedia = IFM_ETHER | IFM_10_T; 198 #endif 199 } 200 201 /* Bus-specific initialization */ 202 hide void 203 mc_init(sc) 204 struct mc_softc *sc; 205 { 206 mc_reset_rxdma(sc); 207 mc_reset_txdma(sc); 208 } 209 210 hide void 211 mc_putpacket(sc, len) 212 struct mc_softc *sc; 213 u_int len; 214 { 215 dbdma_command_t *cmd = sc->sc_txdmacmd; 216 217 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_phys, 218 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 219 220 dbdma_start(sc->sc_txdma, sc->sc_txdmacmd); 221 } 222 223 /* 224 * Interrupt handler for the MACE DMA completion interrupts 225 */ 226 int 227 mc_dmaintr(arg) 228 void *arg; 229 { 230 struct mc_softc *sc = arg; 231 int status, offset, statoff; 232 int datalen, resid; 233 int i, n; 234 dbdma_command_t *cmd; 235 236 /* We've received some packets from the MACE */ 237 238 /* Loop through, processing each of the packets */ 239 i = sc->sc_tail; 240 for (n = 0; n < MC_RXDMABUFS; n++, i++) { 241 if (i == MC_RXDMABUFS) 242 i = 0; 243 244 cmd = &sc->sc_rxdmacmd[i]; 245 /* flushcache(cmd, sizeof(dbdma_command_t)); */ 246 status = dbdma_ld16(&cmd->d_status); 247 resid = dbdma_ld16(&cmd->d_resid); 248 249 /*if ((status & D_ACTIVE) == 0)*/ 250 if ((status & 0x40) == 0) 251 continue; 252 253 #if 1 254 if (dbdma_ld16(&cmd->d_count) != ETHERMTU + 22) 255 printf("bad d_count\n"); 256 #endif 257 258 datalen = dbdma_ld16(&cmd->d_count) - resid; 259 datalen -= 4; /* 4 == status bytes */ 260 261 if (datalen < 4 + sizeof(struct ether_header)) { 262 printf("short packet len=%d\n", datalen); 263 /* continue; */ 264 goto next; 265 } 266 267 offset = i * MC_BUFSIZE; 268 statoff = offset + datalen; 269 270 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 271 __asm __volatile("eieio"); 272 273 /* flushcache(sc->sc_rxbuf + offset, datalen + 4); */ 274 275 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0]; 276 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1]; 277 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2]; 278 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3]; 279 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset; 280 281 mc_rint(sc); 282 283 next: 284 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 285 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 286 __asm __volatile("eieio"); 287 cmd->d_status = 0; 288 cmd->d_resid = 0; 289 sc->sc_tail = i + 1; 290 } 291 292 dbdma_continue(sc->sc_rxdma); 293 294 return 1; 295 } 296 297 hide void 298 mc_reset_rxdma(sc) 299 struct mc_softc *sc; 300 { 301 dbdma_command_t *cmd = sc->sc_rxdmacmd; 302 dbdma_regmap_t *dmareg = sc->sc_rxdma; 303 int i; 304 u_int8_t maccc; 305 306 /* Disable receiver, reset the DMA channels */ 307 maccc = NIC_GET(sc, MACE_MACCC); 308 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 309 310 dbdma_reset(dmareg); 311 312 for (i = 0; i < MC_RXDMABUFS; i++) { 313 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, ETHERMTU + 22, 314 sc->sc_rxbuf_phys + MC_BUFSIZE * i, DBDMA_INT_ALWAYS, 315 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 316 cmd++; 317 } 318 319 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 320 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 321 dbdma_st32(&cmd->d_cmddep, kvtop((caddr_t)sc->sc_rxdmacmd)); 322 cmd++; 323 324 dbdma_start(dmareg, sc->sc_rxdmacmd); 325 326 sc->sc_tail = 0; 327 328 /* Reenable receiver, reenable DMA */ 329 NIC_PUT(sc, MACE_MACCC, maccc); 330 } 331 332 hide void 333 mc_reset_txdma(sc) 334 struct mc_softc *sc; 335 { 336 dbdma_command_t *cmd = sc->sc_txdmacmd; 337 dbdma_regmap_t *dmareg = sc->sc_txdma; 338 u_int8_t maccc; 339 340 /* disable transmitter */ 341 maccc = NIC_GET(sc, MACE_MACCC); 342 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 343 344 dbdma_reset(dmareg); 345 346 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_phys, 347 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 348 cmd++; 349 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 350 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 351 352 out32rb(&dmareg->d_cmdptrhi, 0); 353 out32rb(&dmareg->d_cmdptrlo, kvtop((caddr_t)sc->sc_txdmacmd)); 354 355 /* restore old value */ 356 NIC_PUT(sc, MACE_MACCC, maccc); 357 } 358 359 void 360 mc_select_utp(sc) 361 struct mc_softc *sc; 362 { 363 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 364 } 365 366 void 367 mc_select_aui(sc) 368 struct mc_softc *sc; 369 { 370 sc->sc_plscc = PORTSEL_AUI; 371 } 372 373 int 374 mc_mediachange(sc) 375 struct mc_softc *sc; 376 { 377 struct ifmedia *ifm = &sc->sc_media; 378 379 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 380 return EINVAL; 381 382 switch (IFM_SUBTYPE(ifm->ifm_media)) { 383 384 case IFM_10_T: 385 mc_select_utp(sc); 386 break; 387 388 case IFM_10_5: 389 mc_select_aui(sc); 390 break; 391 392 default: 393 return EINVAL; 394 } 395 396 return 0; 397 } 398 399 void 400 mc_mediastatus(sc, ifmr) 401 struct mc_softc *sc; 402 struct ifmediareq *ifmr; 403 { 404 if (sc->sc_plscc == PORTSEL_AUI) 405 ifmr->ifm_active = IFM_ETHER | IFM_10_5; 406 else 407 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 408 } 409
Indexes created Mon Oct 13 01:09:56 GMT 2025