if_admsw.c revision 1.22
1 /* $NetBSD: if_admsw.c,v 1.22 2019/04/26 06:33:33 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2001 Wasabi Systems, Inc. 35 * All rights reserved. 36 * 37 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed for the NetBSD Project by 50 * Wasabi Systems, Inc. 51 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 52 * or promote products derived from this software without specific prior 53 * written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 70 * Access Controller. 71 * 72 * TODO: 73 * 74 * Better Rx buffer management; we want to get new Rx buffers 75 * to the chip more quickly than we currently do. 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: if_admsw.c,v 1.22 2019/04/26 06:33:33 msaitoh Exp $"); 80 81 82 #include <sys/param.h> 83 #include <sys/bus.h> 84 #include <sys/callout.h> 85 #include <sys/device.h> 86 #include <sys/endian.h> 87 #include <sys/errno.h> 88 #include <sys/intr.h> 89 #include <sys/ioctl.h> 90 #include <sys/kernel.h> 91 #include <sys/malloc.h> 92 #include <sys/mbuf.h> 93 #include <sys/socket.h> 94 #include <sys/systm.h> 95 96 #include <prop/proplib.h> 97 98 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 #include <net/bpf.h> 105 106 #include <sys/gpio.h> 107 #include <dev/gpio/gpiovar.h> 108 109 #include <mips/adm5120/include/adm5120reg.h> 110 #include <mips/adm5120/include/adm5120var.h> 111 #include <mips/adm5120/include/adm5120_obiovar.h> 112 #include <mips/adm5120/dev/if_admswreg.h> 113 #include <mips/adm5120/dev/if_admswvar.h> 114 115 static uint8_t vlan_matrix[SW_DEVS] = { 116 (1 << 6) | (1 << 0), /* CPU + port0 */ 117 (1 << 6) | (1 << 1), /* CPU + port1 */ 118 (1 << 6) | (1 << 2), /* CPU + port2 */ 119 (1 << 6) | (1 << 3), /* CPU + port3 */ 120 (1 << 6) | (1 << 4), /* CPU + port4 */ 121 (1 << 6) | (1 << 5), /* CPU + port5 */ 122 }; 123 124 #ifdef ADMSW_EVENT_COUNTERS 125 #define ADMSW_EVCNT_INCR(ev) (ev)->ev_count++ 126 #else 127 #define ADMSW_EVCNT_INCR(ev) /* nothing */ 128 #endif 129 130 static void admsw_start(struct ifnet *); 131 static void admsw_watchdog(struct ifnet *); 132 static int admsw_ioctl(struct ifnet *, u_long, void *); 133 static int admsw_init(struct ifnet *); 134 static void admsw_stop(struct ifnet *, int); 135 136 static void admsw_shutdown(void *); 137 138 static void admsw_reset(struct admsw_softc *); 139 static void admsw_set_filter(struct admsw_softc *); 140 141 static int admsw_intr(void *); 142 static void admsw_txintr(struct admsw_softc *, int); 143 static void admsw_rxintr(struct admsw_softc *, int); 144 static int admsw_add_rxbuf(struct admsw_softc *, int, int); 145 #define admsw_add_rxhbuf(sc, idx) admsw_add_rxbuf(sc, idx, 1) 146 #define admsw_add_rxlbuf(sc, idx) admsw_add_rxbuf(sc, idx, 0) 147 148 static int admsw_mediachange(struct ifnet *); 149 static void admsw_mediastatus(struct ifnet *, struct ifmediareq *); 150 151 static int admsw_match(device_t, cfdata_t, void *); 152 static void admsw_attach(device_t, device_t, void *); 153 154 CFATTACH_DECL_NEW(admsw, sizeof(struct admsw_softc), 155 admsw_match, admsw_attach, NULL, NULL); 156 157 static int 158 admsw_match(device_t parent, cfdata_t cf, void *aux) 159 { 160 struct obio_attach_args *aa = aux; 161 162 return strcmp(aa->oba_name, cf->cf_name) == 0; 163 } 164 165 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o)) 166 #define REG_WRITE(o,v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v)) 167 168 169 static void 170 admsw_init_bufs(struct admsw_softc *sc) 171 { 172 int i; 173 struct admsw_desc *desc; 174 175 for (i = 0; i < ADMSW_NTXHDESC; i++) { 176 if (sc->sc_txhsoft[i].ds_mbuf != NULL) { 177 m_freem(sc->sc_txhsoft[i].ds_mbuf); 178 sc->sc_txhsoft[i].ds_mbuf = NULL; 179 } 180 desc = &sc->sc_txhdescs[i]; 181 desc->data = 0; 182 desc->cntl = 0; 183 desc->len = MAC_BUFLEN; 184 desc->status = 0; 185 ADMSW_CDTXHSYNC(sc, i, 186 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 187 } 188 sc->sc_txhdescs[ADMSW_NTXHDESC - 1].data |= ADM5120_DMA_RINGEND; 189 ADMSW_CDTXHSYNC(sc, ADMSW_NTXHDESC - 1, 190 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 191 192 for (i = 0; i < ADMSW_NRXHDESC; i++) { 193 if (sc->sc_rxhsoft[i].ds_mbuf == NULL) { 194 if (admsw_add_rxhbuf(sc, i) != 0) 195 panic("admsw_init_bufs\n"); 196 } else 197 ADMSW_INIT_RXHDESC(sc, i); 198 } 199 200 for (i = 0; i < ADMSW_NTXLDESC; i++) { 201 if (sc->sc_txlsoft[i].ds_mbuf != NULL) { 202 m_freem(sc->sc_txlsoft[i].ds_mbuf); 203 sc->sc_txlsoft[i].ds_mbuf = NULL; 204 } 205 desc = &sc->sc_txldescs[i]; 206 desc->data = 0; 207 desc->cntl = 0; 208 desc->len = MAC_BUFLEN; 209 desc->status = 0; 210 ADMSW_CDTXLSYNC(sc, i, 211 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 212 } 213 sc->sc_txldescs[ADMSW_NTXLDESC - 1].data |= ADM5120_DMA_RINGEND; 214 ADMSW_CDTXLSYNC(sc, ADMSW_NTXLDESC - 1, 215 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 216 217 for (i = 0; i < ADMSW_NRXLDESC; i++) { 218 if (sc->sc_rxlsoft[i].ds_mbuf == NULL) { 219 if (admsw_add_rxlbuf(sc, i) != 0) 220 panic("admsw_init_bufs\n"); 221 } else 222 ADMSW_INIT_RXLDESC(sc, i); 223 } 224 225 REG_WRITE(SEND_HBADDR_REG, ADMSW_CDTXHADDR(sc, 0)); 226 REG_WRITE(SEND_LBADDR_REG, ADMSW_CDTXLADDR(sc, 0)); 227 REG_WRITE(RECV_HBADDR_REG, ADMSW_CDRXHADDR(sc, 0)); 228 REG_WRITE(RECV_LBADDR_REG, ADMSW_CDRXLADDR(sc, 0)); 229 230 sc->sc_txfree = ADMSW_NTXLDESC; 231 sc->sc_txnext = 0; 232 sc->sc_txdirty = 0; 233 sc->sc_rxptr = 0; 234 } 235 236 static void 237 admsw_setvlan(struct admsw_softc *sc, char matrix[6]) 238 { 239 uint32_t i; 240 241 i = matrix[0] + (matrix[1] << 8) + (matrix[2] << 16) 242 + (matrix[3] << 24); 243 REG_WRITE(VLAN_G1_REG, i); 244 i = matrix[4] + (matrix[5] << 8); 245 REG_WRITE(VLAN_G2_REG, i); 246 } 247 248 static void 249 admsw_reset(struct admsw_softc *sc) 250 { 251 uint32_t wdog1; 252 int i; 253 254 REG_WRITE(PORT_CONF0_REG, 255 REG_READ(PORT_CONF0_REG) | PORT_CONF0_DP_MASK); 256 REG_WRITE(CPUP_CONF_REG, 257 REG_READ(CPUP_CONF_REG) | CPUP_CONF_DCPUP); 258 259 /* Wait for DMA to complete. Overkill. In 3ms, we can 260 * send at least two entire 1500-byte packets at 10 Mb/s. 261 */ 262 DELAY(3000); 263 264 /* The datasheet recommends that we move all PHYs to reset 265 * state prior to software reset. 266 */ 267 REG_WRITE(PHY_CNTL2_REG, 268 REG_READ(PHY_CNTL2_REG) & ~PHY_CNTL2_PHYR_MASK); 269 270 /* Reset the switch. */ 271 REG_WRITE(ADMSW_SW_RES, 0x1); 272 273 DELAY(100 * 1000); 274 275 REG_WRITE(ADMSW_BOOT_DONE, ADMSW_BOOT_DONE_BO); 276 277 /* begin old code */ 278 REG_WRITE(CPUP_CONF_REG, 279 CPUP_CONF_DCPUP | CPUP_CONF_CRCP | CPUP_CONF_DUNP_MASK | 280 CPUP_CONF_DMCP_MASK); 281 282 REG_WRITE(PORT_CONF0_REG, PORT_CONF0_EMCP_MASK | PORT_CONF0_EMBP_MASK); 283 284 REG_WRITE(PHY_CNTL2_REG, 285 REG_READ(PHY_CNTL2_REG) | PHY_CNTL2_ANE_MASK | 286 PHY_CNTL2_PHYR_MASK | PHY_CNTL2_AMDIX_MASK); 287 288 REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT); 289 290 REG_WRITE(ADMSW_INT_MASK, INT_MASK); 291 REG_WRITE(ADMSW_INT_ST, INT_MASK); 292 293 /* 294 * While in DDB, we stop servicing interrupts, RX ring 295 * fills up and when free block counter falls behind FC 296 * threshold, the switch starts to emit 802.3x PAUSE 297 * frames. This can upset peer switches. 298 * 299 * Stop this from happening by disabling FC and D2 300 * thresholds. 301 */ 302 REG_WRITE(FC_TH_REG, 303 REG_READ(FC_TH_REG) & ~(FC_TH_FCS_MASK | FC_TH_D2S_MASK)); 304 305 admsw_setvlan(sc, vlan_matrix); 306 307 for (i = 0; i < SW_DEVS; i++) { 308 REG_WRITE(MAC_WT1_REG, 309 sc->sc_enaddr[2] | 310 (sc->sc_enaddr[3]<<8) | 311 (sc->sc_enaddr[4]<<16) | 312 ((sc->sc_enaddr[5]+i)<<24)); 313 REG_WRITE(MAC_WT0_REG, (i<<MAC_WT0_VLANID_SHIFT) | 314 (sc->sc_enaddr[0]<<16) | (sc->sc_enaddr[1]<<24) | 315 MAC_WT0_WRITE | MAC_WT0_VLANID_EN); 316 317 while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE)); 318 } 319 wdog1 = REG_READ(ADM5120_WDOG1); 320 REG_WRITE(ADM5120_WDOG1, wdog1 & ~ADM5120_WDOG1_WDE); 321 } 322 323 static void 324 admsw_attach(device_t parent, device_t self, void *aux) 325 { 326 uint8_t enaddr[ETHER_ADDR_LEN]; 327 struct admsw_softc *sc = device_private(self); 328 struct obio_attach_args *aa = aux; 329 struct ifnet *ifp; 330 bus_dma_segment_t seg; 331 int error, i, rseg; 332 prop_data_t pd; 333 334 printf(": ADM5120 Switch Engine, %d ports\n", SW_DEVS); 335 336 sc->sc_dev = self; 337 sc->sc_dmat = aa->oba_dt; 338 sc->sc_st = aa->oba_st; 339 340 pd = prop_dictionary_get(device_properties(self), "mac-address"); 341 342 if (pd == NULL) { 343 enaddr[0] = 0x02; 344 enaddr[1] = 0xaa; 345 enaddr[2] = 0xbb; 346 enaddr[3] = 0xcc; 347 enaddr[4] = 0xdd; 348 enaddr[5] = 0xee; 349 } else 350 memcpy(enaddr, prop_data_data_nocopy(pd), sizeof(enaddr)); 351 352 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 353 354 printf("%s: base Ethernet address %s\n", device_xname(sc->sc_dev), 355 ether_sprintf(enaddr)); 356 357 /* Map the device. */ 358 if (bus_space_map(sc->sc_st, aa->oba_addr, 512, 0, &sc->sc_ioh) != 0) { 359 printf("%s: unable to map device\n", device_xname(sc->sc_dev)); 360 return; 361 } 362 363 /* Hook up the interrupt handler. */ 364 sc->sc_ih = adm5120_intr_establish(aa->oba_irq, INTR_IRQ, admsw_intr, sc); 365 366 if (sc->sc_ih == NULL) { 367 printf("%s: unable to register interrupt handler\n", 368 device_xname(sc->sc_dev)); 369 return; 370 } 371 372 /* 373 * Allocate the control data structures, and create and load the 374 * DMA map for it. 375 */ 376 if ((error = bus_dmamem_alloc(sc->sc_dmat, 377 sizeof(struct admsw_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 378 0)) != 0) { 379 printf("%s: unable to allocate control data, error = %d\n", 380 device_xname(sc->sc_dev), error); 381 return; 382 } 383 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 384 sizeof(struct admsw_control_data), (void *)&sc->sc_control_data, 385 0)) != 0) { 386 printf("%s: unable to map control data, error = %d\n", 387 device_xname(sc->sc_dev), error); 388 return; 389 } 390 if ((error = bus_dmamap_create(sc->sc_dmat, 391 sizeof(struct admsw_control_data), 1, 392 sizeof(struct admsw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 393 printf("%s: unable to create control data DMA map, " 394 "error = %d\n", device_xname(sc->sc_dev), error); 395 return; 396 } 397 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 398 sc->sc_control_data, sizeof(struct admsw_control_data), NULL, 399 0)) != 0) { 400 printf("%s: unable to load control data DMA map, error = %d\n", 401 device_xname(sc->sc_dev), error); 402 return; 403 } 404 405 /* 406 * Create the transmit buffer DMA maps. 407 */ 408 for (i = 0; i < ADMSW_NTXHDESC; i++) { 409 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 410 2, MCLBYTES, 0, 0, 411 &sc->sc_txhsoft[i].ds_dmamap)) != 0) { 412 printf("%s: unable to create txh DMA map %d, " 413 "error = %d\n", device_xname(sc->sc_dev), i, error); 414 return; 415 } 416 sc->sc_txhsoft[i].ds_mbuf = NULL; 417 } 418 for (i = 0; i < ADMSW_NTXLDESC; i++) { 419 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 420 2, MCLBYTES, 0, 0, 421 &sc->sc_txlsoft[i].ds_dmamap)) != 0) { 422 printf("%s: unable to create txl DMA map %d, " 423 "error = %d\n", device_xname(sc->sc_dev), i, error); 424 return; 425 } 426 sc->sc_txlsoft[i].ds_mbuf = NULL; 427 } 428 429 /* 430 * Create the receive buffer DMA maps. 431 */ 432 for (i = 0; i < ADMSW_NRXHDESC; i++) { 433 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 434 MCLBYTES, 0, 0, &sc->sc_rxhsoft[i].ds_dmamap)) != 0) { 435 printf("%s: unable to create rxh DMA map %d, " 436 "error = %d\n", device_xname(sc->sc_dev), i, error); 437 return; 438 } 439 sc->sc_rxhsoft[i].ds_mbuf = NULL; 440 } 441 for (i = 0; i < ADMSW_NRXLDESC; i++) { 442 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 443 MCLBYTES, 0, 0, &sc->sc_rxlsoft[i].ds_dmamap)) != 0) { 444 printf("%s: unable to create rxl DMA map %d, " 445 "error = %d\n", device_xname(sc->sc_dev), i, error); 446 return; 447 } 448 sc->sc_rxlsoft[i].ds_mbuf = NULL; 449 } 450 451 admsw_init_bufs(sc); 452 453 admsw_reset(sc); 454 455 for (i = 0; i < SW_DEVS; i++) { 456 ifmedia_init(&sc->sc_ifmedia[i], 0, admsw_mediachange, admsw_mediastatus); 457 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_10_T, 0, NULL); 458 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 459 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_100_TX, 0, NULL); 460 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 461 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_AUTO, 0, NULL); 462 ifmedia_set(&sc->sc_ifmedia[i], IFM_ETHER|IFM_AUTO); 463 464 ifp = &sc->sc_ethercom[i].ec_if; 465 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 466 ifp->if_xname[5] += i; 467 ifp->if_softc = sc; 468 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 469 ifp->if_ioctl = admsw_ioctl; 470 ifp->if_start = admsw_start; 471 ifp->if_watchdog = admsw_watchdog; 472 ifp->if_init = admsw_init; 473 ifp->if_stop = admsw_stop; 474 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 475 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(ADMSW_NTXLDESC, IFQ_MAXLEN)); 476 IFQ_SET_READY(&ifp->if_snd); 477 478 /* Attach the interface. */ 479 if_attach(ifp); 480 if_deferred_start_init(ifp, NULL); 481 ether_ifattach(ifp, enaddr); 482 enaddr[5]++; 483 } 484 485 #ifdef ADMSW_EVENT_COUNTERS 486 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 487 NULL, device_xname(sc->sc_dev), "txstall"); 488 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 489 NULL, device_xname(sc->sc_dev), "rxstall"); 490 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 491 NULL, device_xname(sc->sc_dev), "txintr"); 492 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 493 NULL, device_xname(sc->sc_dev), "rxintr"); 494 #if 1 495 evcnt_attach_dynamic(&sc->sc_ev_rxsync, EVCNT_TYPE_MISC, 496 NULL, device_xname(sc->sc_dev), "rxsync"); 497 #endif 498 #endif 499 500 admwdog_attach(sc); 501 502 /* Make sure the interface is shutdown during reboot. */ 503 sc->sc_sdhook = shutdownhook_establish(admsw_shutdown, sc); 504 if (sc->sc_sdhook == NULL) 505 printf("%s: WARNING: unable to establish shutdown hook\n", 506 device_xname(sc->sc_dev)); 507 508 /* leave interrupts and cpu port disabled */ 509 return; 510 } 511 512 513 /* 514 * admsw_shutdown: 515 * 516 * Make sure the interface is stopped at reboot time. 517 */ 518 static void 519 admsw_shutdown(void *arg) 520 { 521 struct admsw_softc *sc = arg; 522 int i; 523 524 for (i = 0; i < SW_DEVS; i++) 525 admsw_stop(&sc->sc_ethercom[i].ec_if, 1); 526 } 527 528 /* 529 * admsw_start: [ifnet interface function] 530 * 531 * Start packet transmission on the interface. 532 */ 533 static void 534 admsw_start(struct ifnet *ifp) 535 { 536 struct admsw_softc *sc = ifp->if_softc; 537 struct mbuf *m0, *m; 538 struct admsw_descsoft *ds; 539 struct admsw_desc *desc; 540 bus_dmamap_t dmamap; 541 struct ether_header *eh; 542 int error, nexttx, len, i; 543 static int vlan = 0; 544 545 /* 546 * Loop through the send queues, setting up transmit descriptors 547 * unitl we drain the queues, or use up all available transmit 548 * descriptors. 549 */ 550 for (;;) { 551 vlan++; 552 if (vlan == SW_DEVS) 553 vlan = 0; 554 i = vlan; 555 for (;;) { 556 ifp = &sc->sc_ethercom[i].ec_if; 557 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) == 558 IFF_RUNNING) { 559 /* Grab a packet off the queue. */ 560 IFQ_POLL(&ifp->if_snd, m0); 561 if (m0 != NULL) 562 break; 563 } 564 i++; 565 if (i == SW_DEVS) 566 i = 0; 567 if (i == vlan) 568 return; 569 } 570 vlan = i; 571 m = NULL; 572 573 /* Get a spare descriptor. */ 574 if (sc->sc_txfree == 0) { 575 /* No more slots left; notify upper layer. */ 576 ifp->if_flags |= IFF_OACTIVE; 577 ADMSW_EVCNT_INCR(&sc->sc_ev_txstall); 578 break; 579 } 580 nexttx = sc->sc_txnext; 581 desc = &sc->sc_txldescs[nexttx]; 582 ds = &sc->sc_txlsoft[nexttx]; 583 dmamap = ds->ds_dmamap; 584 585 /* 586 * Load the DMA map. If this fails, the packet either 587 * didn't fit in the alloted number of segments, or we 588 * were short on resources. In this case, we'll copy 589 * and try again. 590 */ 591 if (m0->m_pkthdr.len < ETHER_MIN_LEN || 592 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 593 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 594 MGETHDR(m, M_DONTWAIT, MT_DATA); 595 if (m == NULL) { 596 printf("%s: unable to allocate Tx mbuf\n", 597 device_xname(sc->sc_dev)); 598 break; 599 } 600 if (m0->m_pkthdr.len > MHLEN) { 601 MCLGET(m, M_DONTWAIT); 602 if ((m->m_flags & M_EXT) == 0) { 603 printf("%s: unable to allocate Tx " 604 "cluster\n", device_xname(sc->sc_dev)); 605 m_freem(m); 606 break; 607 } 608 } 609 m->m_pkthdr.csum_flags = m0->m_pkthdr.csum_flags; 610 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 611 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 612 if (m->m_pkthdr.len < ETHER_MIN_LEN) { 613 if (M_TRAILINGSPACE(m) < ETHER_MIN_LEN - m->m_pkthdr.len) 614 panic("admsw_start: M_TRAILINGSPACE\n"); 615 memset(mtod(m, uint8_t *) + m->m_pkthdr.len, 0, 616 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 617 m->m_pkthdr.len = m->m_len = ETHER_MIN_LEN; 618 } 619 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 620 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 621 if (error) { 622 printf("%s: unable to load Tx buffer, error = " 623 "%d\n", device_xname(sc->sc_dev), error); 624 break; 625 } 626 } 627 628 IFQ_DEQUEUE(&ifp->if_snd, m0); 629 if (m != NULL) { 630 m_freem(m0); 631 m0 = m; 632 } 633 634 /* 635 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 636 */ 637 638 /* Sync the DMA map. */ 639 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 640 BUS_DMASYNC_PREWRITE); 641 642 if (dmamap->dm_nsegs != 1 && dmamap->dm_nsegs != 2) 643 panic("admsw_start: dm_nsegs == %d\n", dmamap->dm_nsegs); 644 desc->data = dmamap->dm_segs[0].ds_addr; 645 desc->len = len = dmamap->dm_segs[0].ds_len; 646 if (dmamap->dm_nsegs > 1) { 647 len += dmamap->dm_segs[1].ds_len; 648 desc->cntl = dmamap->dm_segs[1].ds_addr 649 | ADM5120_DMA_BUF2ENABLE; 650 } else 651 desc->cntl = 0; 652 desc->status = (len << ADM5120_DMA_LENSHIFT) | (1 << vlan); 653 eh = mtod(m0, struct ether_header *); 654 if (ntohs(eh->ether_type) == ETHERTYPE_IP && 655 m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 656 desc->status |= ADM5120_DMA_CSUM; 657 if (nexttx == ADMSW_NTXLDESC - 1) 658 desc->data |= ADM5120_DMA_RINGEND; 659 desc->data |= ADM5120_DMA_OWN; 660 661 /* Sync the descriptor. */ 662 ADMSW_CDTXLSYNC(sc, nexttx, 663 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 664 665 REG_WRITE(SEND_TRIG_REG, 1); 666 /* printf("send slot %d\n",nexttx); */ 667 668 /* 669 * Store a pointer to the packet so we can free it later. 670 */ 671 ds->ds_mbuf = m0; 672 673 /* Advance the Tx pointer. */ 674 sc->sc_txfree--; 675 sc->sc_txnext = ADMSW_NEXTTXL(nexttx); 676 677 /* Pass the packet to any BPF listeners. */ 678 bpf_mtap(ifp, m0, BPF_D_OUT); 679 680 /* Set a watchdog timer in case the chip flakes out. */ 681 sc->sc_ethercom[0].ec_if.if_timer = 5; 682 } 683 } 684 685 /* 686 * admsw_watchdog: [ifnet interface function] 687 * 688 * Watchdog timer handler. 689 */ 690 static void 691 admsw_watchdog(struct ifnet *ifp) 692 { 693 struct admsw_softc *sc = ifp->if_softc; 694 int vlan; 695 696 #if 1 697 /* Check if an interrupt was lost. */ 698 if (sc->sc_txfree == ADMSW_NTXLDESC) { 699 printf("%s: watchdog false alarm\n", device_xname(sc->sc_dev)); 700 return; 701 } 702 if (sc->sc_ethercom[0].ec_if.if_timer != 0) 703 printf("%s: watchdog timer is %d!\n", device_xname(sc->sc_dev), 704 sc->sc_ethercom[0].ec_if.if_timer); 705 admsw_txintr(sc, 0); 706 if (sc->sc_txfree == ADMSW_NTXLDESC) { 707 printf("%s: tx IRQ lost (queue empty)\n", 708 device_xname(sc->sc_dev)); 709 return; 710 } 711 if (sc->sc_ethercom[0].ec_if.if_timer != 0) { 712 printf("%s: tx IRQ lost (timer recharged)\n", 713 device_xname(sc->sc_dev)); 714 return; 715 } 716 #endif 717 718 printf("%s: device timeout, txfree = %d\n", 719 device_xname(sc->sc_dev), sc->sc_txfree); 720 for (vlan = 0; vlan < SW_DEVS; vlan++) 721 admsw_stop(&sc->sc_ethercom[vlan].ec_if, 0); 722 for (vlan = 0; vlan < SW_DEVS; vlan++) 723 (void)admsw_init(&sc->sc_ethercom[vlan].ec_if); 724 725 /* Try to get more packets going. */ 726 admsw_start(ifp); 727 } 728 729 /* 730 * admsw_ioctl: [ifnet interface function] 731 * 732 * Handle control requests from the operator. 733 */ 734 static int 735 admsw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 736 { 737 struct admsw_softc *sc = ifp->if_softc; 738 struct ifdrv *ifd; 739 int s, error, port; 740 741 s = splnet(); 742 743 switch (cmd) { 744 case SIOCSIFCAP: 745 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 746 error = 0; 747 break; 748 case SIOCSIFMEDIA: 749 case SIOCGIFMEDIA: 750 port = (struct ethercom *)ifp - sc->sc_ethercom; /* XXX */ 751 if (port >= SW_DEVS) 752 error = EOPNOTSUPP; 753 else 754 error = ifmedia_ioctl(ifp, (struct ifreq *)data, 755 &sc->sc_ifmedia[port], cmd); 756 break; 757 758 case SIOCGDRVSPEC: 759 case SIOCSDRVSPEC: 760 ifd = (struct ifdrv *) data; 761 if (ifd->ifd_cmd != 0 || ifd->ifd_len != sizeof(vlan_matrix)) { 762 error = EINVAL; 763 break; 764 } 765 if (cmd == SIOCGDRVSPEC) { 766 error = copyout(vlan_matrix, ifd->ifd_data, 767 sizeof(vlan_matrix)); 768 } else { 769 error = copyin(ifd->ifd_data, vlan_matrix, 770 sizeof(vlan_matrix)); 771 admsw_setvlan(sc, vlan_matrix); 772 } 773 break; 774 775 default: 776 error = ether_ioctl(ifp, cmd, data); 777 if (error == ENETRESET) { 778 /* 779 * Multicast list has changed; set the hardware filter 780 * accordingly. 781 */ 782 admsw_set_filter(sc); 783 error = 0; 784 } 785 break; 786 } 787 788 /* Try to get more packets going. */ 789 admsw_start(ifp); 790 791 splx(s); 792 return error; 793 } 794 795 796 /* 797 * admsw_intr: 798 * 799 * Interrupt service routine. 800 */ 801 static int 802 admsw_intr(void *arg) 803 { 804 struct admsw_softc *sc = arg; 805 uint32_t pending; 806 char buf[64]; 807 808 pending = REG_READ(ADMSW_INT_ST); 809 810 if ((pending & ~(ADMSW_INTR_RHD | ADMSW_INTR_RLD | ADMSW_INTR_SHD | 811 ADMSW_INTR_SLD | ADMSW_INTR_W1TE | ADMSW_INTR_W0TE)) != 0) { 812 snprintb(buf, sizeof(buf), ADMSW_INT_FMT, pending); 813 printf("%s: pending=%s\n", __func__, buf); 814 } 815 REG_WRITE(ADMSW_INT_ST, pending); 816 817 if (sc->ndevs == 0) 818 return 0; 819 820 if ((pending & ADMSW_INTR_RHD) != 0) 821 admsw_rxintr(sc, 1); 822 823 if ((pending & ADMSW_INTR_RLD) != 0) 824 admsw_rxintr(sc, 0); 825 826 if ((pending & ADMSW_INTR_SHD) != 0) 827 admsw_txintr(sc, 1); 828 829 if ((pending & ADMSW_INTR_SLD) != 0) 830 admsw_txintr(sc, 0); 831 832 return 1; 833 } 834 835 /* 836 * admsw_txintr: 837 * 838 * Helper; handle transmit interrupts. 839 */ 840 static void 841 admsw_txintr(struct admsw_softc *sc, int prio) 842 { 843 struct ifnet *ifp; 844 struct admsw_desc *desc; 845 struct admsw_descsoft *ds; 846 int i, vlan; 847 int gotone = 0; 848 849 /* printf("txintr: txdirty: %d, txfree: %d\n",sc->sc_txdirty, sc->sc_txfree); */ 850 for (i = sc->sc_txdirty; sc->sc_txfree != ADMSW_NTXLDESC; 851 i = ADMSW_NEXTTXL(i)) { 852 853 ADMSW_CDTXLSYNC(sc, i, 854 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 855 856 desc = &sc->sc_txldescs[i]; 857 ds = &sc->sc_txlsoft[i]; 858 if (desc->data & ADM5120_DMA_OWN) { 859 ADMSW_CDTXLSYNC(sc, i, 860 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 861 break; 862 } 863 864 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 865 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 866 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 867 m_freem(ds->ds_mbuf); 868 ds->ds_mbuf = NULL; 869 870 vlan = ffs(desc->status & 0x3f) - 1; 871 if (vlan < 0 || vlan >= SW_DEVS) 872 panic("admsw_txintr: bad vlan\n"); 873 ifp = &sc->sc_ethercom[vlan].ec_if; 874 gotone = 1; 875 /* printf("clear tx slot %d\n",i); */ 876 877 ifp->if_opackets++; 878 879 sc->sc_txfree++; 880 } 881 882 if (gotone) { 883 sc->sc_txdirty = i; 884 #ifdef ADMSW_EVENT_COUNTERS 885 ADMSW_EVCNT_INCR(&sc->sc_ev_txintr); 886 #endif 887 for (vlan = 0; vlan < SW_DEVS; vlan++) 888 sc->sc_ethercom[vlan].ec_if.if_flags &= ~IFF_OACTIVE; 889 890 ifp = &sc->sc_ethercom[0].ec_if; 891 892 /* Try to queue more packets. */ 893 if_schedule_deferred_start(ifp); 894 895 /* 896 * If there are no more pending transmissions, 897 * cancel the watchdog timer. 898 */ 899 if (sc->sc_txfree == ADMSW_NTXLDESC) 900 ifp->if_timer = 0; 901 902 } 903 904 /* printf("txintr end: txdirty: %d, txfree: %d\n",sc->sc_txdirty, sc->sc_txfree); */ 905 } 906 907 /* 908 * admsw_rxintr: 909 * 910 * Helper; handle receive interrupts. 911 */ 912 static void 913 admsw_rxintr(struct admsw_softc *sc, int high) 914 { 915 struct ifnet *ifp; 916 struct admsw_descsoft *ds; 917 struct mbuf *m; 918 uint32_t stat; 919 int i, len, port, vlan; 920 921 /* printf("rxintr\n"); */ 922 if (high) 923 panic("admsw_rxintr: high priority packet\n"); 924 925 #ifdef ADMSW_EVENT_COUNTERS 926 int pkts = 0; 927 #endif 928 929 #if 1 930 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 931 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 932 if ((sc->sc_rxldescs[sc->sc_rxptr].data & ADM5120_DMA_OWN) == 0) 933 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 934 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 935 else { 936 i = sc->sc_rxptr; 937 do { 938 ADMSW_CDRXLSYNC(sc, i, 939 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 940 i = ADMSW_NEXTRXL(i); 941 /* the ring is empty, just return. */ 942 if (i == sc->sc_rxptr) 943 return; 944 ADMSW_CDRXLSYNC(sc, i, 945 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 946 } while (sc->sc_rxldescs[i].data & ADM5120_DMA_OWN); 947 ADMSW_CDRXLSYNC(sc, i, 948 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 949 950 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 951 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 952 if ((sc->sc_rxldescs[sc->sc_rxptr].data & ADM5120_DMA_OWN) == 0) 953 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 954 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 955 else { 956 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 957 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 958 /* We've fallen behind the chip: catch it. */ 959 printf("%s: RX ring resync, base=%x, work=%x, %d -> %d\n", 960 device_xname(sc->sc_dev), REG_READ(RECV_LBADDR_REG), 961 REG_READ(RECV_LWADDR_REG), sc->sc_rxptr, i); 962 sc->sc_rxptr = i; 963 ADMSW_EVCNT_INCR(&sc->sc_ev_rxsync); 964 } 965 } 966 #endif 967 for (i = sc->sc_rxptr;; i = ADMSW_NEXTRXL(i)) { 968 ds = &sc->sc_rxlsoft[i]; 969 970 ADMSW_CDRXLSYNC(sc, i, 971 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 972 973 if (sc->sc_rxldescs[i].data & ADM5120_DMA_OWN) { 974 ADMSW_CDRXLSYNC(sc, i, 975 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 976 break; 977 } 978 979 /* printf("process slot %d\n",i); */ 980 981 #ifdef ADMSW_EVENT_COUNTERS 982 pkts++; 983 #endif 984 985 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 986 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 987 988 stat = sc->sc_rxldescs[i].status; 989 len = (stat & ADM5120_DMA_LEN) >> ADM5120_DMA_LENSHIFT; 990 len -= ETHER_CRC_LEN; 991 port = (stat & ADM5120_DMA_PORTID) >> ADM5120_DMA_PORTSHIFT; 992 for (vlan = 0; vlan < SW_DEVS; vlan++) 993 if ((1 << port) & vlan_matrix[vlan]) 994 break; 995 if (vlan == SW_DEVS) 996 vlan = 0; 997 ifp = &sc->sc_ethercom[vlan].ec_if; 998 999 m = ds->ds_mbuf; 1000 if (admsw_add_rxlbuf(sc, i) != 0) { 1001 ifp->if_ierrors++; 1002 ADMSW_INIT_RXLDESC(sc, i); 1003 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1004 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1005 continue; 1006 } 1007 1008 m_set_rcvif(m, ifp); 1009 m->m_pkthdr.len = m->m_len = len; 1010 if ((stat & ADM5120_DMA_TYPE) == ADM5120_DMA_TYPE_IP) { 1011 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1012 if (stat & ADM5120_DMA_CSUMFAIL) 1013 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1014 } 1015 1016 /* Pass it on. */ 1017 if_percpuq_enqueue(ifp->if_percpuq, m); 1018 } 1019 #ifdef ADMSW_EVENT_COUNTERS 1020 if (pkts) 1021 ADMSW_EVCNT_INCR(&sc->sc_ev_rxintr); 1022 1023 if (pkts == ADMSW_NRXLDESC) 1024 ADMSW_EVCNT_INCR(&sc->sc_ev_rxstall); 1025 #endif 1026 1027 /* Update the receive pointer. */ 1028 sc->sc_rxptr = i; 1029 } 1030 1031 /* 1032 * admsw_init: [ifnet interface function] 1033 * 1034 * Initialize the interface. Must be called at splnet(). 1035 */ 1036 static int 1037 admsw_init(struct ifnet *ifp) 1038 { 1039 struct admsw_softc *sc = ifp->if_softc; 1040 1041 /* printf("admsw_init called\n"); */ 1042 1043 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1044 if (sc->ndevs == 0) { 1045 admsw_init_bufs(sc); 1046 admsw_reset(sc); 1047 REG_WRITE(CPUP_CONF_REG, 1048 CPUP_CONF_CRCP | CPUP_CONF_DUNP_MASK | 1049 CPUP_CONF_DMCP_MASK); 1050 /* Clear all pending interrupts */ 1051 REG_WRITE(ADMSW_INT_ST, INT_MASK); 1052 1053 /* Enable needed interrupts */ 1054 REG_WRITE(ADMSW_INT_MASK, REG_READ(ADMSW_INT_MASK) & 1055 ~(ADMSW_INTR_SHD | ADMSW_INTR_SLD | ADMSW_INTR_RHD | 1056 ADMSW_INTR_RLD | ADMSW_INTR_HDF | ADMSW_INTR_LDF)); 1057 } 1058 sc->ndevs++; 1059 } 1060 1061 /* Set the receive filter. */ 1062 admsw_set_filter(sc); 1063 1064 /* Mark iface as running */ 1065 ifp->if_flags |= IFF_RUNNING; 1066 ifp->if_flags &= ~IFF_OACTIVE; 1067 1068 return 0; 1069 } 1070 1071 /* 1072 * admsw_stop: [ifnet interface function] 1073 * 1074 * Stop transmission on the interface. 1075 */ 1076 static void 1077 admsw_stop(struct ifnet *ifp, int disable) 1078 { 1079 struct admsw_softc *sc = ifp->if_softc; 1080 1081 /* printf("admsw_stop: %d\n",disable); */ 1082 1083 if (!(ifp->if_flags & IFF_RUNNING)) 1084 return; 1085 1086 if (--sc->ndevs == 0) { 1087 /* printf("debug: de-initializing hardware\n"); */ 1088 1089 /* Disable cpu port */ 1090 REG_WRITE(CPUP_CONF_REG, 1091 CPUP_CONF_DCPUP | CPUP_CONF_CRCP | 1092 CPUP_CONF_DUNP_MASK | CPUP_CONF_DMCP_MASK); 1093 1094 /* XXX We should disable, then clear? --dyoung */ 1095 /* Clear all pending interrupts */ 1096 REG_WRITE(ADMSW_INT_ST, INT_MASK); 1097 1098 /* Disable interrupts */ 1099 REG_WRITE(ADMSW_INT_MASK, INT_MASK); 1100 } 1101 1102 /* Mark the interface as down and cancel the watchdog timer. */ 1103 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1104 ifp->if_timer = 0; 1105 1106 return; 1107 } 1108 1109 /* 1110 * admsw_set_filter: 1111 * 1112 * Set up the receive filter. 1113 */ 1114 static void 1115 admsw_set_filter(struct admsw_softc *sc) 1116 { 1117 int i; 1118 uint32_t allmc, anymc, conf, promisc; 1119 struct ether_multi *enm; 1120 struct ethercom *ec; 1121 struct ifnet *ifp; 1122 struct ether_multistep step; 1123 1124 /* Find which ports should be operated in promisc mode. */ 1125 allmc = anymc = promisc = 0; 1126 for (i = 0; i < SW_DEVS; i++) { 1127 ec = &sc->sc_ethercom[i]; 1128 ifp = &ec->ec_if; 1129 if (ifp->if_flags & IFF_PROMISC) 1130 promisc |= vlan_matrix[i]; 1131 1132 ifp->if_flags &= ~IFF_ALLMULTI; 1133 1134 ETHER_FIRST_MULTI(step, ec, enm); 1135 while (enm != NULL) { 1136 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1137 ETHER_ADDR_LEN) != 0) { 1138 printf("%s: punting on mcast range\n", 1139 __func__); 1140 ifp->if_flags |= IFF_ALLMULTI; 1141 allmc |= vlan_matrix[i]; 1142 break; 1143 } 1144 1145 anymc |= vlan_matrix[i]; 1146 1147 #if 0 1148 /* XXX extract subroutine --dyoung */ 1149 REG_WRITE(MAC_WT1_REG, 1150 enm->enm_addrlo[2] | 1151 (enm->enm_addrlo[3] << 8) | 1152 (enm->enm_addrlo[4] << 16) | 1153 (enm->enm_addrlo[5] << 24)); 1154 REG_WRITE(MAC_WT0_REG, 1155 (i << MAC_WT0_VLANID_SHIFT) | 1156 (enm->enm_addrlo[0] << 16) | 1157 (enm->enm_addrlo[1] << 24) | 1158 MAC_WT0_WRITE | MAC_WT0_VLANID_EN); 1159 /* Timeout? */ 1160 while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE)) 1161 ; 1162 #endif 1163 1164 /* Load h/w with mcast address, port = CPU */ 1165 ETHER_NEXT_MULTI(step, enm); 1166 } 1167 } 1168 1169 conf = REG_READ(CPUP_CONF_REG); 1170 /* 1 Disable forwarding of unknown & multicast packets to 1171 * CPU on all ports. 1172 * 2 Enable forwarding of unknown & multicast packets to 1173 * CPU on ports where IFF_PROMISC or IFF_ALLMULTI is set. 1174 */ 1175 conf |= CPUP_CONF_DUNP_MASK | CPUP_CONF_DMCP_MASK; 1176 /* Enable forwarding of unknown packets to CPU on selected ports. */ 1177 conf ^= ((promisc << CPUP_CONF_DUNP_SHIFT) & CPUP_CONF_DUNP_MASK); 1178 conf ^= ((allmc << CPUP_CONF_DMCP_SHIFT) & CPUP_CONF_DMCP_MASK); 1179 conf ^= ((anymc << CPUP_CONF_DMCP_SHIFT) & CPUP_CONF_DMCP_MASK); 1180 REG_WRITE(CPUP_CONF_REG, conf); 1181 } 1182 1183 /* 1184 * admsw_add_rxbuf: 1185 * 1186 * Add a receive buffer to the indicated descriptor. 1187 */ 1188 int 1189 admsw_add_rxbuf(struct admsw_softc *sc, int idx, int high) 1190 { 1191 struct admsw_descsoft *ds; 1192 struct mbuf *m; 1193 int error; 1194 1195 if (high) 1196 ds = &sc->sc_rxhsoft[idx]; 1197 else 1198 ds = &sc->sc_rxlsoft[idx]; 1199 1200 MGETHDR(m, M_DONTWAIT, MT_DATA); 1201 if (m == NULL) 1202 return ENOBUFS; 1203 1204 MCLGET(m, M_DONTWAIT); 1205 if ((m->m_flags & M_EXT) == 0) { 1206 m_freem(m); 1207 return ENOBUFS; 1208 } 1209 1210 if (ds->ds_mbuf != NULL) 1211 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1212 1213 ds->ds_mbuf = m; 1214 1215 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1216 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1217 BUS_DMA_READ | BUS_DMA_NOWAIT); 1218 if (error) { 1219 printf("%s: can't load rx DMA map %d, error = %d\n", 1220 device_xname(sc->sc_dev), idx, error); 1221 panic("admsw_add_rxbuf"); /* XXX */ 1222 } 1223 1224 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1225 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1226 1227 if (high) 1228 ADMSW_INIT_RXHDESC(sc, idx); 1229 else 1230 ADMSW_INIT_RXLDESC(sc, idx); 1231 1232 return 0; 1233 } 1234 1235 int 1236 admsw_mediachange(struct ifnet *ifp) 1237 { 1238 struct admsw_softc *sc = ifp->if_softc; 1239 int port = (struct ethercom *)ifp - sc->sc_ethercom; /* XXX */ 1240 struct ifmedia *ifm = &sc->sc_ifmedia[port]; 1241 int old, new, val; 1242 1243 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1244 return EINVAL; 1245 1246 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1247 val = PHY_CNTL2_AUTONEG|PHY_CNTL2_100M|PHY_CNTL2_FDX; 1248 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1249 if ((ifm->ifm_media & IFM_FDX) != 0) 1250 val = PHY_CNTL2_100M|PHY_CNTL2_FDX; 1251 else 1252 val = PHY_CNTL2_100M; 1253 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1254 if ((ifm->ifm_media & IFM_FDX) != 0) 1255 val = PHY_CNTL2_FDX; 1256 else 1257 val = 0; 1258 } else 1259 return EINVAL; 1260 1261 old = REG_READ(PHY_CNTL2_REG); 1262 new = old & ~((PHY_CNTL2_AUTONEG|PHY_CNTL2_100M|PHY_CNTL2_FDX) << port); 1263 new |= (val << port); 1264 1265 if (new != old) 1266 REG_WRITE(PHY_CNTL2_REG, new); 1267 1268 return 0; 1269 } 1270 1271 void 1272 admsw_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1273 { 1274 struct admsw_softc *sc = ifp->if_softc; 1275 int port = (struct ethercom *)ifp - sc->sc_ethercom; /* XXX */ 1276 int status; 1277 1278 ifmr->ifm_status = IFM_AVALID; 1279 ifmr->ifm_active = IFM_ETHER; 1280 1281 status = REG_READ(PHY_ST_REG) >> port; 1282 1283 if ((status & PHY_ST_LINKUP) == 0) { 1284 ifmr->ifm_active |= IFM_NONE; 1285 return; 1286 } 1287 1288 ifmr->ifm_status |= IFM_ACTIVE; 1289 ifmr->ifm_active |= (status & PHY_ST_100M) ? IFM_100_TX : IFM_10_T; 1290 if (status & PHY_ST_FDX) 1291 ifmr->ifm_active |= IFM_FDX; 1292 else 1293 ifmr->ifm_active |= IFM_HDX; 1294 } 1295
Indexes created Mon Sep 29 21:09:56 GMT 2025