if_admsw.c revision 1.24
1 /* $NetBSD: if_admsw.c,v 1.24 2019/05/28 07:41:47 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2001 Wasabi Systems, Inc. 35 * All rights reserved. 36 * 37 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed for the NetBSD Project by 50 * Wasabi Systems, Inc. 51 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 52 * or promote products derived from this software without specific prior 53 * written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 70 * Access Controller. 71 * 72 * TODO: 73 * 74 * Better Rx buffer management; we want to get new Rx buffers 75 * to the chip more quickly than we currently do. 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: if_admsw.c,v 1.24 2019/05/28 07:41:47 msaitoh Exp $"); 80 81 82 #include <sys/param.h> 83 #include <sys/bus.h> 84 #include <sys/callout.h> 85 #include <sys/device.h> 86 #include <sys/endian.h> 87 #include <sys/errno.h> 88 #include <sys/intr.h> 89 #include <sys/ioctl.h> 90 #include <sys/kernel.h> 91 #include <sys/malloc.h> 92 #include <sys/mbuf.h> 93 #include <sys/socket.h> 94 #include <sys/systm.h> 95 96 #include <prop/proplib.h> 97 98 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 #include <net/bpf.h> 105 106 #include <sys/gpio.h> 107 #include <dev/gpio/gpiovar.h> 108 109 #include <mips/adm5120/include/adm5120reg.h> 110 #include <mips/adm5120/include/adm5120var.h> 111 #include <mips/adm5120/include/adm5120_obiovar.h> 112 #include <mips/adm5120/dev/if_admswreg.h> 113 #include <mips/adm5120/dev/if_admswvar.h> 114 115 static uint8_t vlan_matrix[SW_DEVS] = { 116 (1 << 6) | (1 << 0), /* CPU + port0 */ 117 (1 << 6) | (1 << 1), /* CPU + port1 */ 118 (1 << 6) | (1 << 2), /* CPU + port2 */ 119 (1 << 6) | (1 << 3), /* CPU + port3 */ 120 (1 << 6) | (1 << 4), /* CPU + port4 */ 121 (1 << 6) | (1 << 5), /* CPU + port5 */ 122 }; 123 124 #ifdef ADMSW_EVENT_COUNTERS 125 #define ADMSW_EVCNT_INCR(ev) (ev)->ev_count++ 126 #else 127 #define ADMSW_EVCNT_INCR(ev) /* nothing */ 128 #endif 129 130 static void admsw_start(struct ifnet *); 131 static void admsw_watchdog(struct ifnet *); 132 static int admsw_ioctl(struct ifnet *, u_long, void *); 133 static int admsw_init(struct ifnet *); 134 static void admsw_stop(struct ifnet *, int); 135 136 static void admsw_shutdown(void *); 137 138 static void admsw_reset(struct admsw_softc *); 139 static void admsw_set_filter(struct admsw_softc *); 140 141 static int admsw_intr(void *); 142 static void admsw_txintr(struct admsw_softc *, int); 143 static void admsw_rxintr(struct admsw_softc *, int); 144 static int admsw_add_rxbuf(struct admsw_softc *, int, int); 145 #define admsw_add_rxhbuf(sc, idx) admsw_add_rxbuf(sc, idx, 1) 146 #define admsw_add_rxlbuf(sc, idx) admsw_add_rxbuf(sc, idx, 0) 147 148 static int admsw_mediachange(struct ifnet *); 149 static void admsw_mediastatus(struct ifnet *, struct ifmediareq *); 150 151 static int admsw_match(device_t, cfdata_t, void *); 152 static void admsw_attach(device_t, device_t, void *); 153 154 CFATTACH_DECL_NEW(admsw, sizeof(struct admsw_softc), 155 admsw_match, admsw_attach, NULL, NULL); 156 157 static int 158 admsw_match(device_t parent, cfdata_t cf, void *aux) 159 { 160 struct obio_attach_args *aa = aux; 161 162 return strcmp(aa->oba_name, cf->cf_name) == 0; 163 } 164 165 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o)) 166 #define REG_WRITE(o, v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v)) 167 168 169 static void 170 admsw_init_bufs(struct admsw_softc *sc) 171 { 172 int i; 173 struct admsw_desc *desc; 174 175 for (i = 0; i < ADMSW_NTXHDESC; i++) { 176 if (sc->sc_txhsoft[i].ds_mbuf != NULL) { 177 m_freem(sc->sc_txhsoft[i].ds_mbuf); 178 sc->sc_txhsoft[i].ds_mbuf = NULL; 179 } 180 desc = &sc->sc_txhdescs[i]; 181 desc->data = 0; 182 desc->cntl = 0; 183 desc->len = MAC_BUFLEN; 184 desc->status = 0; 185 ADMSW_CDTXHSYNC(sc, i, 186 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 187 } 188 sc->sc_txhdescs[ADMSW_NTXHDESC - 1].data |= ADM5120_DMA_RINGEND; 189 ADMSW_CDTXHSYNC(sc, ADMSW_NTXHDESC - 1, 190 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 191 192 for (i = 0; i < ADMSW_NRXHDESC; i++) { 193 if (sc->sc_rxhsoft[i].ds_mbuf == NULL) { 194 if (admsw_add_rxhbuf(sc, i) != 0) 195 panic("admsw_init_bufs\n"); 196 } else 197 ADMSW_INIT_RXHDESC(sc, i); 198 } 199 200 for (i = 0; i < ADMSW_NTXLDESC; i++) { 201 if (sc->sc_txlsoft[i].ds_mbuf != NULL) { 202 m_freem(sc->sc_txlsoft[i].ds_mbuf); 203 sc->sc_txlsoft[i].ds_mbuf = NULL; 204 } 205 desc = &sc->sc_txldescs[i]; 206 desc->data = 0; 207 desc->cntl = 0; 208 desc->len = MAC_BUFLEN; 209 desc->status = 0; 210 ADMSW_CDTXLSYNC(sc, i, 211 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 212 } 213 sc->sc_txldescs[ADMSW_NTXLDESC - 1].data |= ADM5120_DMA_RINGEND; 214 ADMSW_CDTXLSYNC(sc, ADMSW_NTXLDESC - 1, 215 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 216 217 for (i = 0; i < ADMSW_NRXLDESC; i++) { 218 if (sc->sc_rxlsoft[i].ds_mbuf == NULL) { 219 if (admsw_add_rxlbuf(sc, i) != 0) 220 panic("admsw_init_bufs\n"); 221 } else 222 ADMSW_INIT_RXLDESC(sc, i); 223 } 224 225 REG_WRITE(SEND_HBADDR_REG, ADMSW_CDTXHADDR(sc, 0)); 226 REG_WRITE(SEND_LBADDR_REG, ADMSW_CDTXLADDR(sc, 0)); 227 REG_WRITE(RECV_HBADDR_REG, ADMSW_CDRXHADDR(sc, 0)); 228 REG_WRITE(RECV_LBADDR_REG, ADMSW_CDRXLADDR(sc, 0)); 229 230 sc->sc_txfree = ADMSW_NTXLDESC; 231 sc->sc_txnext = 0; 232 sc->sc_txdirty = 0; 233 sc->sc_rxptr = 0; 234 } 235 236 static void 237 admsw_setvlan(struct admsw_softc *sc, char matrix[6]) 238 { 239 uint32_t i; 240 241 i = matrix[0] + (matrix[1] << 8) + (matrix[2] << 16) 242 + (matrix[3] << 24); 243 REG_WRITE(VLAN_G1_REG, i); 244 i = matrix[4] + (matrix[5] << 8); 245 REG_WRITE(VLAN_G2_REG, i); 246 } 247 248 static void 249 admsw_reset(struct admsw_softc *sc) 250 { 251 uint32_t wdog1; 252 int i; 253 254 REG_WRITE(PORT_CONF0_REG, 255 REG_READ(PORT_CONF0_REG) | PORT_CONF0_DP_MASK); 256 REG_WRITE(CPUP_CONF_REG, 257 REG_READ(CPUP_CONF_REG) | CPUP_CONF_DCPUP); 258 259 /* Wait for DMA to complete. Overkill. In 3ms, we can 260 * send at least two entire 1500-byte packets at 10 Mb/s. 261 */ 262 DELAY(3000); 263 264 /* The datasheet recommends that we move all PHYs to reset 265 * state prior to software reset. 266 */ 267 REG_WRITE(PHY_CNTL2_REG, 268 REG_READ(PHY_CNTL2_REG) & ~PHY_CNTL2_PHYR_MASK); 269 270 /* Reset the switch. */ 271 REG_WRITE(ADMSW_SW_RES, 0x1); 272 273 DELAY(100 * 1000); 274 275 REG_WRITE(ADMSW_BOOT_DONE, ADMSW_BOOT_DONE_BO); 276 277 /* begin old code */ 278 REG_WRITE(CPUP_CONF_REG, 279 CPUP_CONF_DCPUP | CPUP_CONF_CRCP | CPUP_CONF_DUNP_MASK | 280 CPUP_CONF_DMCP_MASK); 281 282 REG_WRITE(PORT_CONF0_REG, PORT_CONF0_EMCP_MASK | PORT_CONF0_EMBP_MASK); 283 284 REG_WRITE(PHY_CNTL2_REG, 285 REG_READ(PHY_CNTL2_REG) | PHY_CNTL2_ANE_MASK | 286 PHY_CNTL2_PHYR_MASK | PHY_CNTL2_AMDIX_MASK); 287 288 REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT); 289 290 REG_WRITE(ADMSW_INT_MASK, INT_MASK); 291 REG_WRITE(ADMSW_INT_ST, INT_MASK); 292 293 /* 294 * While in DDB, we stop servicing interrupts, RX ring 295 * fills up and when free block counter falls behind FC 296 * threshold, the switch starts to emit 802.3x PAUSE 297 * frames. This can upset peer switches. 298 * 299 * Stop this from happening by disabling FC and D2 300 * thresholds. 301 */ 302 REG_WRITE(FC_TH_REG, 303 REG_READ(FC_TH_REG) & ~(FC_TH_FCS_MASK | FC_TH_D2S_MASK)); 304 305 admsw_setvlan(sc, vlan_matrix); 306 307 for (i = 0; i < SW_DEVS; i++) { 308 REG_WRITE(MAC_WT1_REG, 309 sc->sc_enaddr[2] | 310 (sc->sc_enaddr[3]<<8) | 311 (sc->sc_enaddr[4]<<16) | 312 ((sc->sc_enaddr[5]+i)<<24)); 313 REG_WRITE(MAC_WT0_REG, (i<<MAC_WT0_VLANID_SHIFT) | 314 (sc->sc_enaddr[0]<<16) | (sc->sc_enaddr[1]<<24) | 315 MAC_WT0_WRITE | MAC_WT0_VLANID_EN); 316 317 while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE)) 318 ; 319 } 320 wdog1 = REG_READ(ADM5120_WDOG1); 321 REG_WRITE(ADM5120_WDOG1, wdog1 & ~ADM5120_WDOG1_WDE); 322 } 323 324 static void 325 admsw_attach(device_t parent, device_t self, void *aux) 326 { 327 uint8_t enaddr[ETHER_ADDR_LEN]; 328 struct admsw_softc *sc = device_private(self); 329 struct obio_attach_args *aa = aux; 330 struct ifnet *ifp; 331 bus_dma_segment_t seg; 332 int error, i, rseg; 333 prop_data_t pd; 334 335 printf(": ADM5120 Switch Engine, %d ports\n", SW_DEVS); 336 337 sc->sc_dev = self; 338 sc->sc_dmat = aa->oba_dt; 339 sc->sc_st = aa->oba_st; 340 341 pd = prop_dictionary_get(device_properties(self), "mac-address"); 342 343 if (pd == NULL) { 344 enaddr[0] = 0x02; 345 enaddr[1] = 0xaa; 346 enaddr[2] = 0xbb; 347 enaddr[3] = 0xcc; 348 enaddr[4] = 0xdd; 349 enaddr[5] = 0xee; 350 } else 351 memcpy(enaddr, prop_data_data_nocopy(pd), sizeof(enaddr)); 352 353 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 354 355 printf("%s: base Ethernet address %s\n", device_xname(sc->sc_dev), 356 ether_sprintf(enaddr)); 357 358 /* Map the device. */ 359 if (bus_space_map(sc->sc_st, aa->oba_addr, 512, 0, &sc->sc_ioh) != 0) { 360 printf("%s: unable to map device\n", device_xname(sc->sc_dev)); 361 return; 362 } 363 364 /* Hook up the interrupt handler. */ 365 sc->sc_ih = adm5120_intr_establish(aa->oba_irq, INTR_IRQ, admsw_intr, sc); 366 367 if (sc->sc_ih == NULL) { 368 printf("%s: unable to register interrupt handler\n", 369 device_xname(sc->sc_dev)); 370 return; 371 } 372 373 /* 374 * Allocate the control data structures, and create and load the 375 * DMA map for it. 376 */ 377 if ((error = bus_dmamem_alloc(sc->sc_dmat, 378 sizeof(struct admsw_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 379 0)) != 0) { 380 printf("%s: unable to allocate control data, error = %d\n", 381 device_xname(sc->sc_dev), error); 382 return; 383 } 384 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 385 sizeof(struct admsw_control_data), (void *)&sc->sc_control_data, 386 0)) != 0) { 387 printf("%s: unable to map control data, error = %d\n", 388 device_xname(sc->sc_dev), error); 389 return; 390 } 391 if ((error = bus_dmamap_create(sc->sc_dmat, 392 sizeof(struct admsw_control_data), 1, 393 sizeof(struct admsw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 394 printf("%s: unable to create control data DMA map, " 395 "error = %d\n", device_xname(sc->sc_dev), error); 396 return; 397 } 398 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 399 sc->sc_control_data, sizeof(struct admsw_control_data), NULL, 400 0)) != 0) { 401 printf("%s: unable to load control data DMA map, error = %d\n", 402 device_xname(sc->sc_dev), error); 403 return; 404 } 405 406 /* 407 * Create the transmit buffer DMA maps. 408 */ 409 for (i = 0; i < ADMSW_NTXHDESC; i++) { 410 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 411 2, MCLBYTES, 0, 0, 412 &sc->sc_txhsoft[i].ds_dmamap)) != 0) { 413 printf("%s: unable to create txh DMA map %d, " 414 "error = %d\n", device_xname(sc->sc_dev), i, error); 415 return; 416 } 417 sc->sc_txhsoft[i].ds_mbuf = NULL; 418 } 419 for (i = 0; i < ADMSW_NTXLDESC; i++) { 420 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 421 2, MCLBYTES, 0, 0, 422 &sc->sc_txlsoft[i].ds_dmamap)) != 0) { 423 printf("%s: unable to create txl DMA map %d, " 424 "error = %d\n", device_xname(sc->sc_dev), i, error); 425 return; 426 } 427 sc->sc_txlsoft[i].ds_mbuf = NULL; 428 } 429 430 /* 431 * Create the receive buffer DMA maps. 432 */ 433 for (i = 0; i < ADMSW_NRXHDESC; i++) { 434 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 435 MCLBYTES, 0, 0, &sc->sc_rxhsoft[i].ds_dmamap)) != 0) { 436 printf("%s: unable to create rxh DMA map %d, " 437 "error = %d\n", device_xname(sc->sc_dev), i, error); 438 return; 439 } 440 sc->sc_rxhsoft[i].ds_mbuf = NULL; 441 } 442 for (i = 0; i < ADMSW_NRXLDESC; i++) { 443 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 444 MCLBYTES, 0, 0, &sc->sc_rxlsoft[i].ds_dmamap)) != 0) { 445 printf("%s: unable to create rxl DMA map %d, " 446 "error = %d\n", device_xname(sc->sc_dev), i, error); 447 return; 448 } 449 sc->sc_rxlsoft[i].ds_mbuf = NULL; 450 } 451 452 admsw_init_bufs(sc); 453 454 admsw_reset(sc); 455 456 for (i = 0; i < SW_DEVS; i++) { 457 ifmedia_init(&sc->sc_ifmedia[i], 0, admsw_mediachange, admsw_mediastatus); 458 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_10_T, 0, NULL); 459 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 460 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_100_TX, 0, NULL); 461 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 462 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_AUTO, 0, NULL); 463 ifmedia_set(&sc->sc_ifmedia[i], IFM_ETHER|IFM_AUTO); 464 465 ifp = &sc->sc_ethercom[i].ec_if; 466 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 467 ifp->if_xname[5] += i; 468 ifp->if_softc = sc; 469 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 470 ifp->if_ioctl = admsw_ioctl; 471 ifp->if_start = admsw_start; 472 ifp->if_watchdog = admsw_watchdog; 473 ifp->if_init = admsw_init; 474 ifp->if_stop = admsw_stop; 475 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 476 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(ADMSW_NTXLDESC, IFQ_MAXLEN)); 477 IFQ_SET_READY(&ifp->if_snd); 478 479 /* Attach the interface. */ 480 if_attach(ifp); 481 if_deferred_start_init(ifp, NULL); 482 ether_ifattach(ifp, enaddr); 483 enaddr[5]++; 484 } 485 486 #ifdef ADMSW_EVENT_COUNTERS 487 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 488 NULL, device_xname(sc->sc_dev), "txstall"); 489 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 490 NULL, device_xname(sc->sc_dev), "rxstall"); 491 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 492 NULL, device_xname(sc->sc_dev), "txintr"); 493 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 494 NULL, device_xname(sc->sc_dev), "rxintr"); 495 #if 1 496 evcnt_attach_dynamic(&sc->sc_ev_rxsync, EVCNT_TYPE_MISC, 497 NULL, device_xname(sc->sc_dev), "rxsync"); 498 #endif 499 #endif 500 501 admwdog_attach(sc); 502 503 /* Make sure the interface is shutdown during reboot. */ 504 sc->sc_sdhook = shutdownhook_establish(admsw_shutdown, sc); 505 if (sc->sc_sdhook == NULL) 506 printf("%s: WARNING: unable to establish shutdown hook\n", 507 device_xname(sc->sc_dev)); 508 509 /* leave interrupts and cpu port disabled */ 510 return; 511 } 512 513 514 /* 515 * admsw_shutdown: 516 * 517 * Make sure the interface is stopped at reboot time. 518 */ 519 static void 520 admsw_shutdown(void *arg) 521 { 522 struct admsw_softc *sc = arg; 523 int i; 524 525 for (i = 0; i < SW_DEVS; i++) 526 admsw_stop(&sc->sc_ethercom[i].ec_if, 1); 527 } 528 529 /* 530 * admsw_start: [ifnet interface function] 531 * 532 * Start packet transmission on the interface. 533 */ 534 static void 535 admsw_start(struct ifnet *ifp) 536 { 537 struct admsw_softc *sc = ifp->if_softc; 538 struct mbuf *m0, *m; 539 struct admsw_descsoft *ds; 540 struct admsw_desc *desc; 541 bus_dmamap_t dmamap; 542 struct ether_header *eh; 543 int error, nexttx, len, i; 544 static int vlan = 0; 545 546 /* 547 * Loop through the send queues, setting up transmit descriptors 548 * unitl we drain the queues, or use up all available transmit 549 * descriptors. 550 */ 551 for (;;) { 552 vlan++; 553 if (vlan == SW_DEVS) 554 vlan = 0; 555 i = vlan; 556 for (;;) { 557 ifp = &sc->sc_ethercom[i].ec_if; 558 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) == 559 IFF_RUNNING) { 560 /* Grab a packet off the queue. */ 561 IFQ_POLL(&ifp->if_snd, m0); 562 if (m0 != NULL) 563 break; 564 } 565 i++; 566 if (i == SW_DEVS) 567 i = 0; 568 if (i == vlan) 569 return; 570 } 571 vlan = i; 572 m = NULL; 573 574 /* Get a spare descriptor. */ 575 if (sc->sc_txfree == 0) { 576 /* No more slots left; notify upper layer. */ 577 ifp->if_flags |= IFF_OACTIVE; 578 ADMSW_EVCNT_INCR(&sc->sc_ev_txstall); 579 break; 580 } 581 nexttx = sc->sc_txnext; 582 desc = &sc->sc_txldescs[nexttx]; 583 ds = &sc->sc_txlsoft[nexttx]; 584 dmamap = ds->ds_dmamap; 585 586 /* 587 * Load the DMA map. If this fails, the packet either 588 * didn't fit in the alloted number of segments, or we 589 * were short on resources. In this case, we'll copy 590 * and try again. 591 */ 592 if (m0->m_pkthdr.len < ETHER_MIN_LEN || 593 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 594 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 595 MGETHDR(m, M_DONTWAIT, MT_DATA); 596 if (m == NULL) { 597 printf("%s: unable to allocate Tx mbuf\n", 598 device_xname(sc->sc_dev)); 599 break; 600 } 601 if (m0->m_pkthdr.len > MHLEN) { 602 MCLGET(m, M_DONTWAIT); 603 if ((m->m_flags & M_EXT) == 0) { 604 printf("%s: unable to allocate Tx " 605 "cluster\n", device_xname(sc->sc_dev)); 606 m_freem(m); 607 break; 608 } 609 } 610 m->m_pkthdr.csum_flags = m0->m_pkthdr.csum_flags; 611 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 612 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 613 if (m->m_pkthdr.len < ETHER_MIN_LEN) { 614 if (M_TRAILINGSPACE(m) < ETHER_MIN_LEN - m->m_pkthdr.len) 615 panic("admsw_start: M_TRAILINGSPACE\n"); 616 memset(mtod(m, uint8_t *) + m->m_pkthdr.len, 0, 617 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 618 m->m_pkthdr.len = m->m_len = ETHER_MIN_LEN; 619 } 620 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 621 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 622 if (error) { 623 printf("%s: unable to load Tx buffer, error = " 624 "%d\n", device_xname(sc->sc_dev), error); 625 break; 626 } 627 } 628 629 IFQ_DEQUEUE(&ifp->if_snd, m0); 630 if (m != NULL) { 631 m_freem(m0); 632 m0 = m; 633 } 634 635 /* 636 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 637 */ 638 639 /* Sync the DMA map. */ 640 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 641 BUS_DMASYNC_PREWRITE); 642 643 if (dmamap->dm_nsegs != 1 && dmamap->dm_nsegs != 2) 644 panic("admsw_start: dm_nsegs == %d\n", 645 dmamap->dm_nsegs); 646 desc->data = dmamap->dm_segs[0].ds_addr; 647 desc->len = len = dmamap->dm_segs[0].ds_len; 648 if (dmamap->dm_nsegs > 1) { 649 len += dmamap->dm_segs[1].ds_len; 650 desc->cntl = dmamap->dm_segs[1].ds_addr 651 | ADM5120_DMA_BUF2ENABLE; 652 } else 653 desc->cntl = 0; 654 desc->status = (len << ADM5120_DMA_LENSHIFT) | (1 << vlan); 655 eh = mtod(m0, struct ether_header *); 656 if (ntohs(eh->ether_type) == ETHERTYPE_IP && 657 m0->m_pkthdr.csum_flags & M_CSUM_IPv4) 658 desc->status |= ADM5120_DMA_CSUM; 659 if (nexttx == ADMSW_NTXLDESC - 1) 660 desc->data |= ADM5120_DMA_RINGEND; 661 desc->data |= ADM5120_DMA_OWN; 662 663 /* Sync the descriptor. */ 664 ADMSW_CDTXLSYNC(sc, nexttx, 665 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 666 667 REG_WRITE(SEND_TRIG_REG, 1); 668 /* printf("send slot %d\n", nexttx); */ 669 670 /* 671 * Store a pointer to the packet so we can free it later. 672 */ 673 ds->ds_mbuf = m0; 674 675 /* Advance the Tx pointer. */ 676 sc->sc_txfree--; 677 sc->sc_txnext = ADMSW_NEXTTXL(nexttx); 678 679 /* Pass the packet to any BPF listeners. */ 680 bpf_mtap(ifp, m0, BPF_D_OUT); 681 682 /* Set a watchdog timer in case the chip flakes out. */ 683 sc->sc_ethercom[0].ec_if.if_timer = 5; 684 } 685 } 686 687 /* 688 * admsw_watchdog: [ifnet interface function] 689 * 690 * Watchdog timer handler. 691 */ 692 static void 693 admsw_watchdog(struct ifnet *ifp) 694 { 695 struct admsw_softc *sc = ifp->if_softc; 696 int vlan; 697 698 #if 1 699 /* Check if an interrupt was lost. */ 700 if (sc->sc_txfree == ADMSW_NTXLDESC) { 701 printf("%s: watchdog false alarm\n", device_xname(sc->sc_dev)); 702 return; 703 } 704 if (sc->sc_ethercom[0].ec_if.if_timer != 0) 705 printf("%s: watchdog timer is %d!\n", device_xname(sc->sc_dev), 706 sc->sc_ethercom[0].ec_if.if_timer); 707 admsw_txintr(sc, 0); 708 if (sc->sc_txfree == ADMSW_NTXLDESC) { 709 printf("%s: tx IRQ lost (queue empty)\n", 710 device_xname(sc->sc_dev)); 711 return; 712 } 713 if (sc->sc_ethercom[0].ec_if.if_timer != 0) { 714 printf("%s: tx IRQ lost (timer recharged)\n", 715 device_xname(sc->sc_dev)); 716 return; 717 } 718 #endif 719 720 printf("%s: device timeout, txfree = %d\n", 721 device_xname(sc->sc_dev), sc->sc_txfree); 722 for (vlan = 0; vlan < SW_DEVS; vlan++) 723 admsw_stop(&sc->sc_ethercom[vlan].ec_if, 0); 724 for (vlan = 0; vlan < SW_DEVS; vlan++) 725 (void)admsw_init(&sc->sc_ethercom[vlan].ec_if); 726 727 /* Try to get more packets going. */ 728 admsw_start(ifp); 729 } 730 731 /* 732 * admsw_ioctl: [ifnet interface function] 733 * 734 * Handle control requests from the operator. 735 */ 736 static int 737 admsw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 738 { 739 struct admsw_softc *sc = ifp->if_softc; 740 struct ifdrv *ifd; 741 int s, error, port; 742 743 s = splnet(); 744 745 switch (cmd) { 746 case SIOCSIFCAP: 747 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 748 error = 0; 749 break; 750 case SIOCSIFMEDIA: 751 case SIOCGIFMEDIA: 752 port = (struct ethercom *)ifp - sc->sc_ethercom; /* XXX */ 753 if (port >= SW_DEVS) 754 error = EOPNOTSUPP; 755 else 756 error = ifmedia_ioctl(ifp, (struct ifreq *)data, 757 &sc->sc_ifmedia[port], cmd); 758 break; 759 760 case SIOCGDRVSPEC: 761 case SIOCSDRVSPEC: 762 ifd = (struct ifdrv *) data; 763 if (ifd->ifd_cmd != 0 || ifd->ifd_len != sizeof(vlan_matrix)) { 764 error = EINVAL; 765 break; 766 } 767 if (cmd == SIOCGDRVSPEC) { 768 error = copyout(vlan_matrix, ifd->ifd_data, 769 sizeof(vlan_matrix)); 770 } else { 771 error = copyin(ifd->ifd_data, vlan_matrix, 772 sizeof(vlan_matrix)); 773 admsw_setvlan(sc, vlan_matrix); 774 } 775 break; 776 777 default: 778 error = ether_ioctl(ifp, cmd, data); 779 if (error == ENETRESET) { 780 /* 781 * Multicast list has changed; set the hardware filter 782 * accordingly. 783 */ 784 admsw_set_filter(sc); 785 error = 0; 786 } 787 break; 788 } 789 790 /* Try to get more packets going. */ 791 admsw_start(ifp); 792 793 splx(s); 794 return error; 795 } 796 797 798 /* 799 * admsw_intr: 800 * 801 * Interrupt service routine. 802 */ 803 static int 804 admsw_intr(void *arg) 805 { 806 struct admsw_softc *sc = arg; 807 uint32_t pending; 808 char buf[64]; 809 810 pending = REG_READ(ADMSW_INT_ST); 811 812 if ((pending & ~(ADMSW_INTR_RHD | ADMSW_INTR_RLD | ADMSW_INTR_SHD | 813 ADMSW_INTR_SLD | ADMSW_INTR_W1TE | ADMSW_INTR_W0TE)) != 0) { 814 snprintb(buf, sizeof(buf), ADMSW_INT_FMT, pending); 815 printf("%s: pending=%s\n", __func__, buf); 816 } 817 REG_WRITE(ADMSW_INT_ST, pending); 818 819 if (sc->ndevs == 0) 820 return 0; 821 822 if ((pending & ADMSW_INTR_RHD) != 0) 823 admsw_rxintr(sc, 1); 824 825 if ((pending & ADMSW_INTR_RLD) != 0) 826 admsw_rxintr(sc, 0); 827 828 if ((pending & ADMSW_INTR_SHD) != 0) 829 admsw_txintr(sc, 1); 830 831 if ((pending & ADMSW_INTR_SLD) != 0) 832 admsw_txintr(sc, 0); 833 834 return 1; 835 } 836 837 /* 838 * admsw_txintr: 839 * 840 * Helper; handle transmit interrupts. 841 */ 842 static void 843 admsw_txintr(struct admsw_softc *sc, int prio) 844 { 845 struct ifnet *ifp; 846 struct admsw_desc *desc; 847 struct admsw_descsoft *ds; 848 int i, vlan; 849 int gotone = 0; 850 851 /* printf("txintr: txdirty: %d, txfree: %d\n", sc->sc_txdirty, sc->sc_txfree); */ 852 for (i = sc->sc_txdirty; sc->sc_txfree != ADMSW_NTXLDESC; 853 i = ADMSW_NEXTTXL(i)) { 854 855 ADMSW_CDTXLSYNC(sc, i, 856 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 857 858 desc = &sc->sc_txldescs[i]; 859 ds = &sc->sc_txlsoft[i]; 860 if (desc->data & ADM5120_DMA_OWN) { 861 ADMSW_CDTXLSYNC(sc, i, 862 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 863 break; 864 } 865 866 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 867 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 868 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 869 m_freem(ds->ds_mbuf); 870 ds->ds_mbuf = NULL; 871 872 vlan = ffs(desc->status & 0x3f) - 1; 873 if (vlan < 0 || vlan >= SW_DEVS) 874 panic("admsw_txintr: bad vlan\n"); 875 ifp = &sc->sc_ethercom[vlan].ec_if; 876 gotone = 1; 877 /* printf("clear tx slot %d\n", i); */ 878 879 ifp->if_opackets++; 880 881 sc->sc_txfree++; 882 } 883 884 if (gotone) { 885 sc->sc_txdirty = i; 886 #ifdef ADMSW_EVENT_COUNTERS 887 ADMSW_EVCNT_INCR(&sc->sc_ev_txintr); 888 #endif 889 for (vlan = 0; vlan < SW_DEVS; vlan++) 890 sc->sc_ethercom[vlan].ec_if.if_flags &= ~IFF_OACTIVE; 891 892 ifp = &sc->sc_ethercom[0].ec_if; 893 894 /* Try to queue more packets. */ 895 if_schedule_deferred_start(ifp); 896 897 /* 898 * If there are no more pending transmissions, 899 * cancel the watchdog timer. 900 */ 901 if (sc->sc_txfree == ADMSW_NTXLDESC) 902 ifp->if_timer = 0; 903 904 } 905 906 /* printf("txintr end: txdirty: %d, txfree: %d\n", sc->sc_txdirty, sc->sc_txfree); */ 907 } 908 909 /* 910 * admsw_rxintr: 911 * 912 * Helper; handle receive interrupts. 913 */ 914 static void 915 admsw_rxintr(struct admsw_softc *sc, int high) 916 { 917 struct ifnet *ifp; 918 struct admsw_descsoft *ds; 919 struct mbuf *m; 920 uint32_t stat; 921 int i, len, port, vlan; 922 923 /* printf("rxintr\n"); */ 924 if (high) 925 panic("admsw_rxintr: high priority packet\n"); 926 927 #ifdef ADMSW_EVENT_COUNTERS 928 int pkts = 0; 929 #endif 930 931 #if 1 932 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 933 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 934 if ((sc->sc_rxldescs[sc->sc_rxptr].data & ADM5120_DMA_OWN) == 0) 935 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 936 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 937 else { 938 i = sc->sc_rxptr; 939 do { 940 ADMSW_CDRXLSYNC(sc, i, 941 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 942 i = ADMSW_NEXTRXL(i); 943 /* the ring is empty, just return. */ 944 if (i == sc->sc_rxptr) 945 return; 946 ADMSW_CDRXLSYNC(sc, i, 947 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 948 } while (sc->sc_rxldescs[i].data & ADM5120_DMA_OWN); 949 ADMSW_CDRXLSYNC(sc, i, 950 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 951 952 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 953 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 954 if ((sc->sc_rxldescs[sc->sc_rxptr].data & ADM5120_DMA_OWN) == 0) 955 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 956 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 957 else { 958 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr, 959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 960 /* We've fallen behind the chip: catch it. */ 961 printf("%s: RX ring resync, base=%x, work=%x, %d -> %d\n", 962 device_xname(sc->sc_dev), REG_READ(RECV_LBADDR_REG), 963 REG_READ(RECV_LWADDR_REG), sc->sc_rxptr, i); 964 sc->sc_rxptr = i; 965 ADMSW_EVCNT_INCR(&sc->sc_ev_rxsync); 966 } 967 } 968 #endif 969 for (i = sc->sc_rxptr;; i = ADMSW_NEXTRXL(i)) { 970 ds = &sc->sc_rxlsoft[i]; 971 972 ADMSW_CDRXLSYNC(sc, i, 973 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 974 975 if (sc->sc_rxldescs[i].data & ADM5120_DMA_OWN) { 976 ADMSW_CDRXLSYNC(sc, i, 977 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 978 break; 979 } 980 981 /* printf("process slot %d\n", i); */ 982 983 #ifdef ADMSW_EVENT_COUNTERS 984 pkts++; 985 #endif 986 987 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 988 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 989 990 stat = sc->sc_rxldescs[i].status; 991 len = (stat & ADM5120_DMA_LEN) >> ADM5120_DMA_LENSHIFT; 992 len -= ETHER_CRC_LEN; 993 port = (stat & ADM5120_DMA_PORTID) >> ADM5120_DMA_PORTSHIFT; 994 for (vlan = 0; vlan < SW_DEVS; vlan++) 995 if ((1 << port) & vlan_matrix[vlan]) 996 break; 997 if (vlan == SW_DEVS) 998 vlan = 0; 999 ifp = &sc->sc_ethercom[vlan].ec_if; 1000 1001 m = ds->ds_mbuf; 1002 if (admsw_add_rxlbuf(sc, i) != 0) { 1003 ifp->if_ierrors++; 1004 ADMSW_INIT_RXLDESC(sc, i); 1005 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1006 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1007 continue; 1008 } 1009 1010 m_set_rcvif(m, ifp); 1011 m->m_pkthdr.len = m->m_len = len; 1012 if ((stat & ADM5120_DMA_TYPE) == ADM5120_DMA_TYPE_IP) { 1013 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1014 if (stat & ADM5120_DMA_CSUMFAIL) 1015 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1016 } 1017 1018 /* Pass it on. */ 1019 if_percpuq_enqueue(ifp->if_percpuq, m); 1020 } 1021 #ifdef ADMSW_EVENT_COUNTERS 1022 if (pkts) 1023 ADMSW_EVCNT_INCR(&sc->sc_ev_rxintr); 1024 1025 if (pkts == ADMSW_NRXLDESC) 1026 ADMSW_EVCNT_INCR(&sc->sc_ev_rxstall); 1027 #endif 1028 1029 /* Update the receive pointer. */ 1030 sc->sc_rxptr = i; 1031 } 1032 1033 /* 1034 * admsw_init: [ifnet interface function] 1035 * 1036 * Initialize the interface. Must be called at splnet(). 1037 */ 1038 static int 1039 admsw_init(struct ifnet *ifp) 1040 { 1041 struct admsw_softc *sc = ifp->if_softc; 1042 1043 /* printf("admsw_init called\n"); */ 1044 1045 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1046 if (sc->ndevs == 0) { 1047 admsw_init_bufs(sc); 1048 admsw_reset(sc); 1049 REG_WRITE(CPUP_CONF_REG, 1050 CPUP_CONF_CRCP | CPUP_CONF_DUNP_MASK | 1051 CPUP_CONF_DMCP_MASK); 1052 /* Clear all pending interrupts */ 1053 REG_WRITE(ADMSW_INT_ST, INT_MASK); 1054 1055 /* Enable needed interrupts */ 1056 REG_WRITE(ADMSW_INT_MASK, REG_READ(ADMSW_INT_MASK) & 1057 ~(ADMSW_INTR_SHD | ADMSW_INTR_SLD | 1058 ADMSW_INTR_RHD | ADMSW_INTR_RLD | 1059 ADMSW_INTR_HDF | ADMSW_INTR_LDF)); 1060 } 1061 sc->ndevs++; 1062 } 1063 1064 /* Set the receive filter. */ 1065 admsw_set_filter(sc); 1066 1067 /* Mark iface as running */ 1068 ifp->if_flags |= IFF_RUNNING; 1069 ifp->if_flags &= ~IFF_OACTIVE; 1070 1071 return 0; 1072 } 1073 1074 /* 1075 * admsw_stop: [ifnet interface function] 1076 * 1077 * Stop transmission on the interface. 1078 */ 1079 static void 1080 admsw_stop(struct ifnet *ifp, int disable) 1081 { 1082 struct admsw_softc *sc = ifp->if_softc; 1083 1084 /* printf("admsw_stop: %d\n", disable); */ 1085 1086 if (!(ifp->if_flags & IFF_RUNNING)) 1087 return; 1088 1089 if (--sc->ndevs == 0) { 1090 /* printf("debug: de-initializing hardware\n"); */ 1091 1092 /* Disable cpu port */ 1093 REG_WRITE(CPUP_CONF_REG, 1094 CPUP_CONF_DCPUP | CPUP_CONF_CRCP | 1095 CPUP_CONF_DUNP_MASK | CPUP_CONF_DMCP_MASK); 1096 1097 /* XXX We should disable, then clear? --dyoung */ 1098 /* Clear all pending interrupts */ 1099 REG_WRITE(ADMSW_INT_ST, INT_MASK); 1100 1101 /* Disable interrupts */ 1102 REG_WRITE(ADMSW_INT_MASK, INT_MASK); 1103 } 1104 1105 /* Mark the interface as down and cancel the watchdog timer. */ 1106 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1107 ifp->if_timer = 0; 1108 1109 return; 1110 } 1111 1112 /* 1113 * admsw_set_filter: 1114 * 1115 * Set up the receive filter. 1116 */ 1117 static void 1118 admsw_set_filter(struct admsw_softc *sc) 1119 { 1120 int i; 1121 uint32_t allmc, anymc, conf, promisc; 1122 struct ether_multi *enm; 1123 struct ethercom *ec; 1124 struct ifnet *ifp; 1125 struct ether_multistep step; 1126 1127 /* Find which ports should be operated in promisc mode. */ 1128 allmc = anymc = promisc = 0; 1129 for (i = 0; i < SW_DEVS; i++) { 1130 ec = &sc->sc_ethercom[i]; 1131 ifp = &ec->ec_if; 1132 if (ifp->if_flags & IFF_PROMISC) 1133 promisc |= vlan_matrix[i]; 1134 1135 ifp->if_flags &= ~IFF_ALLMULTI; 1136 1137 ETHER_LOCK(ec); 1138 ETHER_FIRST_MULTI(step, ec, enm); 1139 while (enm != NULL) { 1140 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1141 ETHER_ADDR_LEN) != 0) { 1142 printf("%s: punting on mcast range\n", 1143 __func__); 1144 ifp->if_flags |= IFF_ALLMULTI; 1145 allmc |= vlan_matrix[i]; 1146 break; 1147 } 1148 1149 anymc |= vlan_matrix[i]; 1150 1151 #if 0 1152 /* XXX extract subroutine --dyoung */ 1153 REG_WRITE(MAC_WT1_REG, 1154 enm->enm_addrlo[2] | 1155 (enm->enm_addrlo[3] << 8) | 1156 (enm->enm_addrlo[4] << 16) | 1157 (enm->enm_addrlo[5] << 24)); 1158 REG_WRITE(MAC_WT0_REG, 1159 (i << MAC_WT0_VLANID_SHIFT) | 1160 (enm->enm_addrlo[0] << 16) | 1161 (enm->enm_addrlo[1] << 24) | 1162 MAC_WT0_WRITE | MAC_WT0_VLANID_EN); 1163 /* Timeout? */ 1164 while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE)) 1165 ; 1166 #endif 1167 1168 /* Load h/w with mcast address, port = CPU */ 1169 ETHER_NEXT_MULTI(step, enm); 1170 } 1171 ETHER_UNLOCK(ec); 1172 } 1173 1174 conf = REG_READ(CPUP_CONF_REG); 1175 /* 1 Disable forwarding of unknown & multicast packets to 1176 * CPU on all ports. 1177 * 2 Enable forwarding of unknown & multicast packets to 1178 * CPU on ports where IFF_PROMISC or IFF_ALLMULTI is set. 1179 */ 1180 conf |= CPUP_CONF_DUNP_MASK | CPUP_CONF_DMCP_MASK; 1181 /* Enable forwarding of unknown packets to CPU on selected ports. */ 1182 conf ^= ((promisc << CPUP_CONF_DUNP_SHIFT) & CPUP_CONF_DUNP_MASK); 1183 conf ^= ((allmc << CPUP_CONF_DMCP_SHIFT) & CPUP_CONF_DMCP_MASK); 1184 conf ^= ((anymc << CPUP_CONF_DMCP_SHIFT) & CPUP_CONF_DMCP_MASK); 1185 REG_WRITE(CPUP_CONF_REG, conf); 1186 } 1187 1188 /* 1189 * admsw_add_rxbuf: 1190 * 1191 * Add a receive buffer to the indicated descriptor. 1192 */ 1193 int 1194 admsw_add_rxbuf(struct admsw_softc *sc, int idx, int high) 1195 { 1196 struct admsw_descsoft *ds; 1197 struct mbuf *m; 1198 int error; 1199 1200 if (high) 1201 ds = &sc->sc_rxhsoft[idx]; 1202 else 1203 ds = &sc->sc_rxlsoft[idx]; 1204 1205 MGETHDR(m, M_DONTWAIT, MT_DATA); 1206 if (m == NULL) 1207 return ENOBUFS; 1208 1209 MCLGET(m, M_DONTWAIT); 1210 if ((m->m_flags & M_EXT) == 0) { 1211 m_freem(m); 1212 return ENOBUFS; 1213 } 1214 1215 if (ds->ds_mbuf != NULL) 1216 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1217 1218 ds->ds_mbuf = m; 1219 1220 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1221 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1222 BUS_DMA_READ | BUS_DMA_NOWAIT); 1223 if (error) { 1224 printf("%s: can't load rx DMA map %d, error = %d\n", 1225 device_xname(sc->sc_dev), idx, error); 1226 panic("admsw_add_rxbuf"); /* XXX */ 1227 } 1228 1229 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1230 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1231 1232 if (high) 1233 ADMSW_INIT_RXHDESC(sc, idx); 1234 else 1235 ADMSW_INIT_RXLDESC(sc, idx); 1236 1237 return 0; 1238 } 1239 1240 int 1241 admsw_mediachange(struct ifnet *ifp) 1242 { 1243 struct admsw_softc *sc = ifp->if_softc; 1244 int port = (struct ethercom *)ifp - sc->sc_ethercom; /* XXX */ 1245 struct ifmedia *ifm = &sc->sc_ifmedia[port]; 1246 int old, new, val; 1247 1248 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1249 return EINVAL; 1250 1251 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1252 val = PHY_CNTL2_AUTONEG | PHY_CNTL2_100M | PHY_CNTL2_FDX; 1253 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1254 if ((ifm->ifm_media & IFM_FDX) != 0) 1255 val = PHY_CNTL2_100M | PHY_CNTL2_FDX; 1256 else 1257 val = PHY_CNTL2_100M; 1258 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1259 if ((ifm->ifm_media & IFM_FDX) != 0) 1260 val = PHY_CNTL2_FDX; 1261 else 1262 val = 0; 1263 } else 1264 return EINVAL; 1265 1266 old = REG_READ(PHY_CNTL2_REG); 1267 new = old & ~((PHY_CNTL2_AUTONEG | PHY_CNTL2_100M | PHY_CNTL2_FDX) 1268 << port); 1269 new |= (val << port); 1270 1271 if (new != old) 1272 REG_WRITE(PHY_CNTL2_REG, new); 1273 1274 return 0; 1275 } 1276 1277 void 1278 admsw_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1279 { 1280 struct admsw_softc *sc = ifp->if_softc; 1281 int port = (struct ethercom *)ifp - sc->sc_ethercom; /* XXX */ 1282 int status; 1283 1284 ifmr->ifm_status = IFM_AVALID; 1285 ifmr->ifm_active = IFM_ETHER; 1286 1287 status = REG_READ(PHY_ST_REG) >> port; 1288 1289 if ((status & PHY_ST_LINKUP) == 0) { 1290 ifmr->ifm_active |= IFM_NONE; 1291 return; 1292 } 1293 1294 ifmr->ifm_status |= IFM_ACTIVE; 1295 ifmr->ifm_active |= (status & PHY_ST_100M) ? IFM_100_TX : IFM_10_T; 1296 if (status & PHY_ST_FDX) 1297 ifmr->ifm_active |= IFM_FDX; 1298 else 1299 ifmr->ifm_active |= IFM_HDX; 1300 } 1301
Indexes created Mon Sep 29 21:09:56 GMT 2025