1 1.1 dyoung /* $NetBSD: uart.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */ 2 1.1 dyoung 3 1.1 dyoung /*- 4 1.1 dyoung * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 1.1 dyoung * All rights reserved. 6 1.1 dyoung * 7 1.1 dyoung * Redistribution and use in source and binary forms, with or 8 1.1 dyoung * without modification, are permitted provided that the following 9 1.1 dyoung * conditions are met: 10 1.1 dyoung * 1. Redistributions of source code must retain the above copyright 11 1.1 dyoung * notice, this list of conditions and the following disclaimer. 12 1.1 dyoung * 2. Redistributions in binary form must reproduce the above 13 1.1 dyoung * copyright notice, this list of conditions and the following 14 1.1 dyoung * disclaimer in the documentation and/or other materials provided 15 1.1 dyoung * with the distribution. 16 1.1 dyoung * 3. The names of the authors may not be used to endorse or promote 17 1.1 dyoung * products derived from this software without specific prior 18 1.1 dyoung * written permission. 19 1.1 dyoung * 20 1.1 dyoung * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 1.1 dyoung * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 1.1 dyoung * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 1.1 dyoung * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 1.1 dyoung * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 1.1 dyoung * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 1.1 dyoung * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 1.1 dyoung * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.1 dyoung * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 1.1 dyoung * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 1.1 dyoung * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 1.1 dyoung * OF SUCH DAMAGE. 32 1.1 dyoung */ 33 1.1 dyoung #ifndef _ADMUART_H 34 1.1 dyoung #define _ADMUART_H 35 1.1 dyoung /* UART registers */ 36 1.1 dyoung #define UART_DR_REG 0x00 37 1.1 dyoung #define UART_RSR_REG 0x04 38 1.1 dyoung #define UART_RSR_FE 0x01 39 1.1 dyoung #define UART_RSR_PE 0x02 40 1.1 dyoung #define UART_RSR_BE 0x04 41 1.1 dyoung #define UART_RSR_OE 0x08 42 1.1 dyoung #define UART_ECR_REG 0x04 43 1.1 dyoung #define UART_ECR_RSR 0x80 44 1.1 dyoung #define UART_LCR_H_REG 0x08 45 1.1 dyoung #define UART_LCR_M_REG 0x0c 46 1.1 dyoung #define UART_LCR_L_REG 0x10 47 1.1 dyoung #define UART_CR_REG 0x14 48 1.1 dyoung #define UART_CR_PORT_EN 0x01 49 1.1 dyoung #define UART_CR_SIREN 0x02 50 1.1 dyoung #define UART_CR_SIRLP 0x04 51 1.1 dyoung #define UART_CR_MODEM_STATUS_INT_EN 0x08 52 1.1 dyoung #define UART_CR_RX_INT_EN 0x10 53 1.1 dyoung #define UART_CR_TX_INT_EN 0x20 54 1.1 dyoung #define UART_CR_RX_TIMEOUT_INT_EN 0x40 55 1.1 dyoung #define UART_CR_LOOPBACK_EN 0x80 56 1.1 dyoung #define UART_FR_REG 0x18 57 1.1 dyoung #define UART_FR_CTS 0x01 58 1.1 dyoung #define UART_FR_DSR 0x02 59 1.1 dyoung #define UART_FR_DCD 0x04 60 1.1 dyoung #define UART_FR_BUSY 0x08 61 1.1 dyoung #define UART_FR_RX_FIFO_EMPTY 0x10 62 1.1 dyoung #define UART_FR_TX_FIFO_FULL 0x20 63 1.1 dyoung #define UART_FR_RX_FIFO_FULL 0x40 64 1.1 dyoung #define UART_FR_TX_FIFO_EMPTY 0x80 65 1.1 dyoung #define UART_IR_REG 0x1c 66 1.1 dyoung #define UART_IR_MODEM_STATUS_INT 0x01 67 1.1 dyoung #define UART_IR_RX_INT 0x02 68 1.1 dyoung #define UART_IR_TX_INT 0x04 69 1.1 dyoung #define UART_IR_RX_TIMEOUT_INT 0x08 70 1.1 dyoung #define UART_IR_INT_MASK 0x0f 71 1.1 dyoung #define UART_ILPR_REG 0x20 72 1.1 dyoung 73 1.1 dyoung /* UART interrupts */ 74 1.1 dyoung 75 1.1 dyoung int uart_cnattach(void); 76 1.1 dyoung #endif /* _ADMUART_H */ 77
Indexes created Sun Sep 21 14:09:52 GMT 2025