adm5120reg.h revision 1.1
1 /* $NetBSD: adm5120reg.h,v 1.1 2007/03/20 08:52:03 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (c) 2001 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Jason R. Thorpe. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 #ifndef _ADM5120REG_H_ 70 #define _ADM5120REG_H_ 71 72 /* 73 * Memory map and register definitions for the Alchemy Semiconductor Pb1000. 74 */ 75 76 /* Last byte of physical address space. */ 77 #define ADM5120_TOP 0x1fffffff 78 #define ADM5120_BOTTOM 0x0 79 80 /* Flash addresses */ 81 #define ADM5120_BASE_SRAM0 0x1fc00000 82 83 /* UARTs */ 84 #define ADM5120_BASE_UART1 0x12800000 85 #define ADM5120_BASE_UART0 0x12600000 86 87 /* ICU */ 88 #define ADM5120_BASE_ICU 0x12200000 89 #define ICU_STATUS_REG 0x00 90 #define ICU_RAW_STATUS_REG 0x04 91 #define ICU_ENABLE_REG 0x08 92 #define ICU_DISABLE_REG 0x0c 93 #define ICU_SOFT_REG 0x10 94 #define ICU_MODE_REG 0x14 95 #define ICU_FIQ_STATUS_REG 0x18 96 #define ICU_TESTSRC_REG 0x1c 97 #define ICU_SRCSEL_REG 0x20 98 #define ICU_LEVEL_REG 0x24 99 #define ICU_INT_MASK 0x3ff 100 101 /* Switch */ 102 #define ADM5120_BASE_SWITCH 0x12000000 103 #define SW_CODE_REG 0x00 104 #define CLKS_MASK 0x00300000 105 #define CLKS_175MHZ 0x00000000 106 #define CLKS_200MHZ 0x00100000 107 #define SW_SFTRES_REG 0x04 108 #define SW_MEMCONT_REG 0x1c 109 #define SDRAM_SIZE_4MBYTES 0x0001 110 #define SDRAM_SIZE_8MBYTES 0x0002 111 #define SDRAM_SIZE_16MBYTES 0x0003 112 #define SDRAM_SIZE_64MBYTES 0x0004 113 #define SDRAM_SIZE_128MBYTES 0x0005 114 #define SDRAM_SIZE_MASK 0x0007 115 #define SRAM0_SIZE_SHIFT 8 116 #define SRAM1_SIZE_SHIFT 16 117 #define SRAM_MASK 0x0007 118 #define SRAM_SSIZE 0x40000 119 120 #define ADM5120_BASE_PCI_CONFDATA 0x115ffff8 121 #define ADM5120_BASE_PCI_CONFADDR 0x115ffff0 122 #define ADM5120_BASE_PCI_IO 0x11500000 123 #define ADM5120_BASE_PCI_MEM 0x11400000 124 #define ADM5120_BASE_USB 0x11200000 125 #define ADM5120_BASE_MPMC 0x11000000 126 #define ADM5120_BASE_EXTIO1 0x10e00000 127 #define ADM5120_BASE_EXTIO0 0x10c00000 128 #define ADM5120_BASE_RSVD0 0x10800000 129 #define ADM5120_BASE_SRAM1 0x10000000 130 131 #define _REG_READ(b, o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((b) + (o))) 132 #define SW_READ(o) _REG_READ(ADM5120_BASE_SWITCH, o) 133 134 #define _REG_WRITE(b, o, v) (_REG_READ(b, o)) = (v) 135 #define SW_WRITE(o, v) _REG_WRITE(ADM5120_BASE_SWITCH,o, v) 136 137 /* USB */ 138 139 /* Watchdog Timers: base address is switch controller */ 140 141 #define ADM5120_WDOG0 0x00c0 142 #define ADM5120_WDOG1 0x00c4 143 144 #define ADM5120_WDOG0_WTTR __BIT(31) /* 0: do not reset, 145 * 1: reset on wdog expiration 146 */ 147 #define ADM5120_WDOG1_WDE __BIT(31) /* 0: deactivate, 148 * 1: drop all CPU-bound 149 * packets, disable flow 150 * control on all ports. 151 */ 152 #define ADM5120_WDOG_WTS_MASK __BITS(30, 16) /* Watchdog Timer Set: 153 * timer expires when it 154 * reaches WTS. Units of 155 * 10ms. 156 */ 157 #define ADM5120_WDOG_RSVD __BIT(15) 158 #define ADM5120_WDOG_WT_MASK __BITS(14, 0) /* Watchdog Timer: 159 * counts up, write to clear. 160 */ 161 162 /* GPIO: base address is switch controller */ 163 #define ADM5120_GPIO0 0x00b8 164 165 #define ADM5120_GPIO0_OV __BITS(31, 24) /* rw: output value */ 166 #define ADM5120_GPIO0_OE __BITS(23, 16) /* rw: output enable, 167 * bit[n] = 0 -> input 168 * bit[n] = 1 -> output 169 */ 170 #define ADM5120_GPIO0_IV __BITS(15, 8) /* ro: input value */ 171 #define ADM5120_GPIO0_RSVD __BITS(7, 0) /* rw: reserved */ 172 173 #define ADM5120_GPIO2 0x00bc 174 #define ADM5120_GPIO2_EW __BIT(6) /* 1: enable wait state pin, 175 * pin GPIO[0], for GPIO[1] 176 * or GPIO[3] Chip Select: 177 * memory controller waits for 178 * WAIT# inactive (high). 179 */ 180 #define ADM5120_GPIO2_CSX1 __BIT(5) /* 1: GPIO[3:4] act as 181 * Chip Select for 182 * External I/O 1 (CSX1) 183 * and External Interrupt 1 184 * (INTX1), respectively. 185 * 0: CSX1/INTX1 disabled 186 */ 187 #define ADM5120_GPIO2_CSX0 __BIT(4) /* 1: GPIO[1:2] act as 188 * Chip Select for 189 * External I/O 0 (CSX0) 190 * and External Interrupt 0 191 * (INTX0), respectively. 192 * 0: CSX0/INTX0 disabled 193 */ 194 195 /* MultiPort Memory Controller (MPMC) */ 196 197 #define ADM5120_MPMC_CONTROL 0x000 198 #define ADM5120_MPMC_CONTROL_DWB __BIT(3) /* write 1 to 199 * drain write 200 * buffers. write 0 201 * for normal buffer 202 * operation. 203 */ 204 #define ADM5120_MPMC_CONTROL_LPM __BIT(2) /* 1: activate low-power 205 * mode. SDRAM is 206 * still refreshed. 207 */ 208 #define ADM5120_MPMC_CONTROL_AM __BIT(1) /* 1: address mirror: 209 * static memory 210 * chip select 0 211 * is mapped to chip 212 * select 1. 213 */ 214 #define ADM5120_MPMC_CONTROL_ME __BIT(0) /* 0: disable MPMC. 215 * DRAM is not 216 * refreshed. 217 * 1: enable MPMC. 218 */ 219 220 #define ADM5120_MPMC_STATUS 0x004 221 #define ADM5120_MPMC_STATUS_SRA __BIT(2) /* read-only 222 * MPMC operating mode 223 * indication, 224 * 1: self-refresh 225 * acknowledge 226 * 0: normal mode 227 */ 228 #define ADM5120_MPMC_STATUS_WBS __BIT(1) /* read-only 229 * write-buffer status, 230 * 0: buffers empty 231 * 1: contain data 232 */ 233 #define ADM5120_MPMC_STATUS_BU __BIT(0) /* read-only MPMC 234 * "busy" indication, 235 * 0: MPMC idle 236 * 1: MPMC is performing 237 * memory transactions 238 */ 239 240 #define ADM5120_MPMC_SEW 0x080 241 #define ADM5120_MPMC_SEW_RSVD __BITS(31, 10) 242 #define ADM5120_MPMC_SEW_EWTO __BITS(9, 0) /* timeout access after 243 * 16 * (n + 1) clock cycles 244 * (XXX which clock?) 245 */ 246 247 #define ADM5120_MPMC_SC(__i) (0x200 + 0x020 * (__i)) 248 #define ADM5120_MPMC_SC_RSVD0 __BITS(31, 21) 249 #define ADM5120_MPMC_SC_WP __BIT(20) /* 1: write protect */ 250 #define ADM5120_MPMC_SC_BE __BIT(20) /* 1: enable write buffer */ 251 #define ADM5120_MPMC_SC_RSVD1 __BITS(18, 9) 252 #define ADM5120_MPMC_SC_EW __BIT(8) /* 1: enable extended wait; 253 */ 254 #define ADM5120_MPMC_SC_BLS __BIT(7) /* 0: byte line state pins 255 * are active high on read, 256 * active low on write. 257 * 258 * 1: byte line state pins 259 * are active low on read and 260 * on write. 261 */ 262 #define ADM5120_MPMC_SC_CCP __BIT(6) /* 0: chip select is active low, 263 * 1: active high 264 */ 265 #define ADM5120_MPMC_SC_RSVD2 __BITS(5, 4) 266 #define ADM5120_MPMC_SC_PM __BIT(3) /* 0: page mode disabled, 267 * 1: enable asynchronous 268 * page mode four 269 */ 270 #define ADM5120_MPMC_SC_RSVD3 __BIT(2) 271 #define ADM5120_MPMC_SC_MW_MASK __BITS(1, 0) /* memory width, bits */ 272 #define ADM5120_MPMC_SC_MW_8B __SHIFTIN(0, ADM5120_MPMC_SC_MW_MASK) 273 #define ADM5120_MPMC_SC_MW_16B __SHIFTIN(1, ADM5120_MPMC_SC_MW_MASK) 274 #define ADM5120_MPMC_SC_MW_32B __SHIFTIN(2, ADM5120_MPMC_SC_MW_MASK) 275 #define ADM5120_MPMC_SC_MW_RSVD __SHIFTIN(3, ADM5120_MPMC_SC_MW_MASK) 276 277 #define ADM5120_MPMC_SWW(__i) (0x204 + 0x020 * (__i)) 278 #define ADM5120_MPMC_SWW_RSVD __BITS(31, 4) 279 #define ADM5120_MPMC_SWW_WWE __BITS(3, 0) /* delay (n + 1) * HCLK cycles 280 * after asserting chip select 281 * (CS) before asserting write 282 * enable (WE) 283 */ 284 285 #define ADM5120_MPMC_SWO(__i) (0x208 + 0x020 * (__i)) 286 #define ADM5120_MPMC_SWO_RSVD __BITS(31, 4) 287 #define ADM5120_MPMC_SWO_WOE __BITS(3, 0) /* delay n * HCLK cycles 288 * after asserting chip select 289 * before asserting output 290 * enable (OE) 291 */ 292 293 #define ADM5120_MPMC_SWR(__i) (0x20c + 0x020 * (__i)) 294 #define ADM5120_MPMC_SWR_RSVD __BITS(31, 5) 295 #define ADM5120_MPMC_SWR_NMRW __BITS(4, 0) /* read wait states for 296 * either first page-mode 297 * access or for non-page mode 298 * read, (n + 1) * HCLK cycles 299 */ 300 301 #define ADM5120_MPMC_SWP(__i) (0x210 + 0x020 * (__i)) 302 #define ADM5120_MPMC_SWP_RSVD __BITS(31, 5) 303 #define ADM5120_MPMC_SWP_WPS __BITS(4, 0) /* read wait states for 304 * second and subsequent 305 * page-mode read, 306 * (n + 1) * HCLK cycles 307 */ 308 309 #define ADM5120_MPMC_SWWR(__i) (0x214 + 0x020 * (__i)) 310 #define ADM5120_MPMC_SWWR_RSVD __BITS(31, 5) 311 #define ADM5120_MPMC_SWWR_WWS __BITS(4, 0) /* write wait states after 312 * the first read (??), 313 * (n + 2) * HCLK cycles 314 */ 315 316 #define ADM5120_MPMC_SWT(__i) (0x218 + 0x020 * (__i)) 317 #define ADM5120_MPMC_SWT_RSVD __BITS(31, 4) 318 #define ADM5120_MPMC_SWT_WAITTURN __BITS(3, 0) /* bus turnaround time, 319 * (n + 1) * HCLK cycles 320 */ 321 322 #endif /* _ADM5120REG_H_ */ 323
Indexes created Tue Sep 30 11:09:46 GMT 2025