au_icu.c revision 1.18
1 /* $NetBSD: au_icu.c,v 1.18 2006/02/23 01:50:55 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 2001 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Jason R. Thorpe. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the NetBSD 52 * Foundation, Inc. and its contributors. 53 * 4. Neither the name of The NetBSD Foundation nor the names of its 54 * contributors may be used to endorse or promote products derived 55 * from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs. 72 * 73 * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal 74 * interrupt controllers. 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.18 2006/02/23 01:50:55 gdamore Exp $"); 79 80 #include "opt_ddb.h" 81 82 #include <sys/param.h> 83 #include <sys/queue.h> 84 #include <sys/malloc.h> 85 #include <sys/systm.h> 86 #include <sys/device.h> 87 #include <sys/kernel.h> 88 89 #include <machine/bus.h> 90 #include <machine/intr.h> 91 92 #include <mips/locore.h> 93 #include <mips/alchemy/include/aureg.h> 94 #include <mips/alchemy/include/auvar.h> 95 96 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 97 98 /* 99 * This is a mask of bits to clear in the SR when we go to a 100 * given hardware interrupt priority level. 101 */ 102 103 const uint32_t ipl_sr_bits[_IPL_N] = { 104 0, /* 0: IPL_NONE */ 105 106 MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFT */ 107 108 MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTCLOCK */ 109 110 MIPS_SOFT_INT_MASK_0, /* 3: IPL_SOFTNET */ 111 112 MIPS_SOFT_INT_MASK_0, /* 4: IPL_SOFTSERIAL */ 113 114 MIPS_SOFT_INT_MASK_0| 115 MIPS_SOFT_INT_MASK_1| 116 MIPS_INT_MASK_0, /* 5: IPL_BIO */ 117 118 MIPS_SOFT_INT_MASK_0| 119 MIPS_SOFT_INT_MASK_1| 120 MIPS_INT_MASK_0, /* 6: IPL_NET */ 121 122 MIPS_SOFT_INT_MASK_0| 123 MIPS_SOFT_INT_MASK_1| 124 MIPS_INT_MASK_0, /* 7: IPL_{SERIAL,TTY} */ 125 126 MIPS_SOFT_INT_MASK_0| 127 MIPS_SOFT_INT_MASK_1| 128 MIPS_INT_MASK_0| 129 MIPS_INT_MASK_1| 130 MIPS_INT_MASK_2| 131 MIPS_INT_MASK_3| 132 MIPS_INT_MASK_4| 133 MIPS_INT_MASK_5, /* 8: IPL_{CLOCK,HIGH} */ 134 }; 135 136 /* 137 * This is a mask of bits to clear in the SR when we go to a 138 * given software interrupt priority level. 139 * Hardware ipls are port/board specific. 140 */ 141 const uint32_t mips_ipl_si_to_sr[_IPL_NSOFT] = { 142 MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */ 143 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */ 144 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTNET */ 145 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTSERIAL */ 146 }; 147 148 #define NIRQS 64 149 150 struct au_icu_intrhead { 151 struct evcnt intr_count; 152 int intr_refcnt; 153 }; 154 struct au_icu_intrhead au_icu_intrtab[NIRQS]; 155 156 #define NINTRS 4 /* MIPS INT0 - INT3 */ 157 158 struct au_intrhand { 159 LIST_ENTRY(au_intrhand) ih_q; 160 int (*ih_func)(void *); 161 void *ih_arg; 162 int ih_irq; 163 }; 164 165 struct au_cpuintr { 166 LIST_HEAD(, au_intrhand) cintr_list; 167 struct evcnt cintr_count; 168 }; 169 170 struct au_cpuintr au_cpuintrs[NINTRS]; 171 const char *au_cpuintrnames[NINTRS] = { 172 "icu 0, req 0", 173 "icu 0, req 1", 174 "icu 1, req 0", 175 "icu 1, req 1", 176 }; 177 178 static bus_addr_t ic0_base, ic1_base; 179 180 void 181 au_intr_init(void) 182 { 183 int i; 184 struct au_chipdep *chip; 185 186 for (i = 0; i < NINTRS; i++) { 187 LIST_INIT(&au_cpuintrs[i].cintr_list); 188 evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count, 189 EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]); 190 } 191 192 chip = au_chipdep(); 193 KASSERT(chip != NULL); 194 195 ic0_base = chip->icus[0]; 196 ic1_base = chip->icus[1]; 197 198 for (i = 0; i < NIRQS; i++) { 199 au_icu_intrtab[i].intr_refcnt = 0; 200 evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count, 201 EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]); 202 } 203 } 204 205 void * 206 au_intr_establish(int irq, int req, int level, int type, 207 int (*func)(void *), void *arg) 208 { 209 struct au_intrhand *ih; 210 uint32_t icu_base; 211 int cpu_int, s; 212 struct au_chipdep *chip; 213 214 chip = au_chipdep(); 215 KASSERT(chip != NULL); 216 217 if (irq >= NIRQS) 218 panic("au_intr_establish: bogus IRQ %d", irq); 219 if (req > 1) 220 panic("au_intr_establish: bogus request %d", req); 221 222 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 223 if (ih == NULL) 224 return (NULL); 225 226 ih->ih_func = func; 227 ih->ih_arg = arg; 228 ih->ih_irq = irq; 229 230 s = splhigh(); 231 232 /* 233 * First, link it into the tables. 234 * XXX do we want a separate list (really, should only be one item, not 235 * a list anyway) per irq, not per CPU interrupt? 236 */ 237 cpu_int = (irq < 32 ? 0 : 2); 238 LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q); 239 240 /* 241 * Now enable it. 242 */ 243 if (au_icu_intrtab[irq].intr_refcnt++ == 0) { 244 icu_base = (irq < 32) ? ic0_base : ic1_base; 245 246 irq &= 31; /* throw away high bit if set */ 247 irq = 1 << irq; /* only used as a mask from here on */ 248 249 /* XXX Only level interrupts for now */ 250 switch (type) { 251 case IST_NONE: 252 case IST_PULSE: 253 case IST_EDGE: 254 panic("unsupported irq type %d", type); 255 /* NOTREACHED */ 256 case IST_LEVEL: 257 case IST_LEVEL_HIGH: 258 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 259 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 260 REGVAL(icu_base + IC_CONFIG0_SET) = irq; 261 break; 262 case IST_LEVEL_LOW: 263 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 264 REGVAL(icu_base + IC_CONFIG1_SET) = irq; 265 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 266 break; 267 } 268 wbflush(); 269 270 /* XXX handle GPIO interrupts - not done at all yet */ 271 if (cpu_int & 0x1) 272 REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq; 273 else 274 REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq; 275 276 /* Associate interrupt with peripheral */ 277 REGVAL(icu_base + IC_SOURCE_SET) = irq; 278 279 /* Actually enable the interrupt */ 280 REGVAL(icu_base + IC_MASK_SET) = irq; 281 282 /* And allow the interrupt to interrupt idle */ 283 REGVAL(icu_base + IC_WAKEUP_SET) = irq; 284 285 wbflush(); 286 } 287 splx(s); 288 289 return (ih); 290 } 291 292 void 293 au_intr_disestablish(void *cookie) 294 { 295 struct au_intrhand *ih = cookie; 296 uint32_t icu_base; 297 int irq, s; 298 299 irq = ih->ih_irq; 300 301 s = splhigh(); 302 303 /* 304 * First, remove it from the table. 305 */ 306 LIST_REMOVE(ih, ih_q); 307 308 /* 309 * Now, disable it, if there is nothing remaining on the 310 * list. 311 */ 312 if (au_icu_intrtab[irq].intr_refcnt-- == 1) { 313 icu_base = (irq < 32) ? ic0_base : ic1_base; 314 315 irq &= 31; /* throw away high bit if set */ 316 irq = 1 << irq; /* only used as a mask from here on */ 317 318 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq; 319 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 320 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 321 322 /* disable with MASK_CLEAR and WAKEUP_CLEAR */ 323 REGVAL(icu_base + IC_MASK_CLEAR) = irq; 324 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq; 325 wbflush(); 326 } 327 328 splx(s); 329 330 free(ih, M_DEVBUF); 331 } 332 333 void 334 au_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 335 { 336 struct au_intrhand *ih; 337 int level; 338 uint32_t icu_base, irqstat, irqmask; 339 340 icu_base = irqstat = 0; /* XXX gcc */ 341 342 for (level = 3; level >= 0; level--) { 343 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 344 continue; 345 346 /* 347 * XXX the following may well be slow to execute. 348 * investigate and possibly speed up. 349 * 350 * is something like: 351 * 352 * irqstat = REGVAL( 353 * (level & 4 == 0) ? IC0_BASE ? IC1_BASE + 354 * (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT); 355 * 356 * be any better? 357 * 358 */ 359 switch (level) { 360 case 0: 361 icu_base = ic0_base; 362 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 363 break; 364 case 1: 365 icu_base = ic0_base; 366 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 367 break; 368 case 2: 369 icu_base = ic1_base; 370 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 371 break; 372 case 3: 373 icu_base = ic1_base; 374 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 375 break; 376 } 377 irqmask = REGVAL(icu_base + IC_MASK_READ); 378 au_cpuintrs[level].cintr_count.ev_count++; 379 LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) { 380 int irq = (1 << ih->ih_irq); 381 382 if ((irq & irqmask) && (irq & irqstat)) { 383 au_icu_intrtab[ih->ih_irq].intr_count.ev_count++; 384 (*ih->ih_func)(ih->ih_arg); 385 386 if (REGVAL(icu_base + IC_MASK_READ) & irq) { 387 REGVAL(icu_base + IC_MASK_CLEAR) = irq; 388 REGVAL(icu_base + IC_MASK_SET) = irq; 389 wbflush(); 390 } 391 } 392 } 393 cause &= ~(MIPS_INT_MASK_0 << level); 394 } 395 396 /* Re-enable anything that we have processed. */ 397 _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK)); 398 } 399 400 /* 401 * Some devices (e.g. PCMCIA) want to be able to mask interrupts at 402 * the ICU, and leave them masked off until some later time 403 * (e.g. reenabled by a soft interrupt). 404 */ 405 406 void 407 au_intr_enable(int irq) 408 { 409 int s; 410 uint32_t icu_base, mask; 411 412 if (irq >= NIRQS) 413 panic("au_intr_enable: bogus IRQ %d", irq); 414 415 icu_base = (irq < 32) ? ic0_base : ic1_base; 416 mask = irq & 31; 417 mask = 1 << mask; 418 419 s = splhigh(); 420 /* only enable the interrupt if we have a handler */ 421 if (au_icu_intrtab[irq].intr_refcnt) { 422 REGVAL(icu_base + IC_MASK_SET) = mask; 423 REGVAL(icu_base + IC_WAKEUP_SET) = mask; 424 wbflush(); 425 } 426 splx(s); 427 } 428 429 void 430 au_intr_disable(int irq) 431 { 432 int s; 433 uint32_t icu_base, mask; 434 435 if (irq >= NIRQS) 436 panic("au_intr_disable: bogus IRQ %d", irq); 437 438 icu_base = (irq < 32) ? ic0_base : ic1_base; 439 mask = irq & 31; 440 mask = 1 << mask; 441 442 s = splhigh(); 443 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 444 REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask; 445 wbflush(); 446 splx(s); 447 } 448
Indexes created Mon Sep 29 21:09:56 GMT 2025