au_icu.c revision 1.19
1 /* $NetBSD: au_icu.c,v 1.19 2006/03/25 07:23:05 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 2001 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Jason R. Thorpe. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the NetBSD 52 * Foundation, Inc. and its contributors. 53 * 4. Neither the name of The NetBSD Foundation nor the names of its 54 * contributors may be used to endorse or promote products derived 55 * from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs. 72 * 73 * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal 74 * interrupt controllers. 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.19 2006/03/25 07:23:05 gdamore Exp $"); 79 80 #include "opt_ddb.h" 81 82 #include <sys/param.h> 83 #include <sys/queue.h> 84 #include <sys/malloc.h> 85 #include <sys/systm.h> 86 #include <sys/device.h> 87 #include <sys/kernel.h> 88 89 #include <machine/bus.h> 90 #include <machine/intr.h> 91 92 #include <mips/locore.h> 93 #include <mips/alchemy/include/aureg.h> 94 #include <mips/alchemy/include/auvar.h> 95 96 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 97 98 /* 99 * This is a mask of bits to clear in the SR when we go to a 100 * given hardware interrupt priority level. 101 */ 102 103 const uint32_t ipl_sr_bits[_IPL_N] = { 104 0, /* 0: IPL_NONE */ 105 106 MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFT */ 107 108 MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTCLOCK */ 109 110 MIPS_SOFT_INT_MASK_0, /* 3: IPL_SOFTNET */ 111 112 MIPS_SOFT_INT_MASK_0, /* 4: IPL_SOFTSERIAL */ 113 114 MIPS_SOFT_INT_MASK_0| 115 MIPS_SOFT_INT_MASK_1| 116 MIPS_INT_MASK_0, /* 5: IPL_BIO */ 117 118 MIPS_SOFT_INT_MASK_0| 119 MIPS_SOFT_INT_MASK_1| 120 MIPS_INT_MASK_0, /* 6: IPL_NET */ 121 122 MIPS_SOFT_INT_MASK_0| 123 MIPS_SOFT_INT_MASK_1| 124 MIPS_INT_MASK_0, /* 7: IPL_{SERIAL,TTY} */ 125 126 MIPS_SOFT_INT_MASK_0| 127 MIPS_SOFT_INT_MASK_1| 128 MIPS_INT_MASK_0| 129 MIPS_INT_MASK_1| 130 MIPS_INT_MASK_2| 131 MIPS_INT_MASK_3| 132 MIPS_INT_MASK_4| 133 MIPS_INT_MASK_5, /* 8: IPL_{CLOCK,HIGH} */ 134 }; 135 136 /* 137 * This is a mask of bits to clear in the SR when we go to a 138 * given software interrupt priority level. 139 * Hardware ipls are port/board specific. 140 */ 141 const uint32_t mips_ipl_si_to_sr[_IPL_NSOFT] = { 142 MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */ 143 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */ 144 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTNET */ 145 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTSERIAL */ 146 }; 147 148 #define NIRQS 64 149 150 struct au_icu_intrhead { 151 struct evcnt intr_count; 152 int intr_refcnt; 153 }; 154 struct au_icu_intrhead au_icu_intrtab[NIRQS]; 155 156 #define NINTRS 4 /* MIPS INT0 - INT3 */ 157 158 struct au_intrhand { 159 LIST_ENTRY(au_intrhand) ih_q; 160 int (*ih_func)(void *); 161 void *ih_arg; 162 int ih_irq; 163 int ih_mask; 164 }; 165 166 struct au_cpuintr { 167 LIST_HEAD(, au_intrhand) cintr_list; 168 struct evcnt cintr_count; 169 }; 170 171 struct au_cpuintr au_cpuintrs[NINTRS]; 172 const char *au_cpuintrnames[NINTRS] = { 173 "icu 0, req 0", 174 "icu 0, req 1", 175 "icu 1, req 0", 176 "icu 1, req 1", 177 }; 178 179 static bus_addr_t ic0_base, ic1_base; 180 181 void 182 au_intr_init(void) 183 { 184 int i; 185 struct au_chipdep *chip; 186 187 for (i = 0; i < NINTRS; i++) { 188 LIST_INIT(&au_cpuintrs[i].cintr_list); 189 evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count, 190 EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]); 191 } 192 193 chip = au_chipdep(); 194 KASSERT(chip != NULL); 195 196 ic0_base = chip->icus[0]; 197 ic1_base = chip->icus[1]; 198 199 for (i = 0; i < NIRQS; i++) { 200 au_icu_intrtab[i].intr_refcnt = 0; 201 evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count, 202 EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]); 203 } 204 205 /* start with all interrupts masked */ 206 REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff; 207 REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff; 208 REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff; 209 REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff; 210 REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff; 211 REGVAL(ic0_base + IC_TEST_BIT) = 0; 212 213 REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff; 214 REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff; 215 REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff; 216 REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff; 217 REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff; 218 REGVAL(ic1_base + IC_TEST_BIT) = 0; 219 } 220 221 void * 222 au_intr_establish(int irq, int req, int level, int type, 223 int (*func)(void *), void *arg) 224 { 225 struct au_intrhand *ih; 226 uint32_t icu_base; 227 int cpu_int, s; 228 struct au_chipdep *chip; 229 230 chip = au_chipdep(); 231 KASSERT(chip != NULL); 232 233 if (irq >= NIRQS) 234 panic("au_intr_establish: bogus IRQ %d", irq); 235 if (req > 1) 236 panic("au_intr_establish: bogus request %d", req); 237 238 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 239 if (ih == NULL) 240 return (NULL); 241 242 ih->ih_func = func; 243 ih->ih_arg = arg; 244 ih->ih_irq = irq; 245 ih->ih_mask = (1 << (irq & 31)); 246 247 s = splhigh(); 248 249 /* 250 * First, link it into the tables. 251 * XXX do we want a separate list (really, should only be one item, not 252 * a list anyway) per irq, not per CPU interrupt? 253 */ 254 cpu_int = (irq < 32 ? 0 : 2); 255 LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q); 256 257 /* 258 * Now enable it. 259 */ 260 if (au_icu_intrtab[irq].intr_refcnt++ == 0) { 261 icu_base = (irq < 32) ? ic0_base : ic1_base; 262 263 irq &= 31; /* throw away high bit if set */ 264 irq = 1 << irq; /* only used as a mask from here on */ 265 266 /* XXX Only level interrupts for now */ 267 switch (type) { 268 case IST_NONE: 269 case IST_PULSE: 270 case IST_EDGE: 271 panic("unsupported irq type %d", type); 272 /* NOTREACHED */ 273 case IST_LEVEL: 274 case IST_LEVEL_HIGH: 275 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 276 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 277 REGVAL(icu_base + IC_CONFIG0_SET) = irq; 278 break; 279 case IST_LEVEL_LOW: 280 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 281 REGVAL(icu_base + IC_CONFIG1_SET) = irq; 282 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 283 break; 284 } 285 wbflush(); 286 287 /* XXX handle GPIO interrupts - not done at all yet */ 288 if (cpu_int & 0x1) 289 REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq; 290 else 291 REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq; 292 293 /* Associate interrupt with peripheral */ 294 REGVAL(icu_base + IC_SOURCE_SET) = irq; 295 296 /* Actually enable the interrupt */ 297 REGVAL(icu_base + IC_MASK_SET) = irq; 298 299 /* And allow the interrupt to interrupt idle */ 300 REGVAL(icu_base + IC_WAKEUP_SET) = irq; 301 302 wbflush(); 303 } 304 splx(s); 305 306 return (ih); 307 } 308 309 void 310 au_intr_disestablish(void *cookie) 311 { 312 struct au_intrhand *ih = cookie; 313 uint32_t icu_base; 314 int irq, s; 315 316 irq = ih->ih_irq; 317 318 s = splhigh(); 319 320 /* 321 * First, remove it from the table. 322 */ 323 LIST_REMOVE(ih, ih_q); 324 325 /* 326 * Now, disable it, if there is nothing remaining on the 327 * list. 328 */ 329 if (au_icu_intrtab[irq].intr_refcnt-- == 1) { 330 icu_base = (irq < 32) ? ic0_base : ic1_base; 331 332 irq &= 31; /* throw away high bit if set */ 333 irq = 1 << irq; /* only used as a mask from here on */ 334 335 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq; 336 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 337 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 338 339 /* disable with MASK_CLEAR and WAKEUP_CLEAR */ 340 REGVAL(icu_base + IC_MASK_CLEAR) = irq; 341 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq; 342 wbflush(); 343 } 344 345 splx(s); 346 347 free(ih, M_DEVBUF); 348 } 349 350 void 351 au_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 352 { 353 struct au_intrhand *ih; 354 int level; 355 uint32_t icu_base, irqstat, irqmask; 356 357 icu_base = irqstat = 0; 358 359 for (level = 3; level >= 0; level--) { 360 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 361 continue; 362 363 /* 364 * XXX the following may well be slow to execute. 365 * investigate and possibly speed up. 366 * 367 * is something like: 368 * 369 * irqstat = REGVAL( 370 * (level & 4 == 0) ? IC0_BASE ? IC1_BASE + 371 * (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT); 372 * 373 * be any better? 374 * 375 */ 376 switch (level) { 377 case 0: 378 icu_base = ic0_base; 379 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 380 break; 381 case 1: 382 icu_base = ic0_base; 383 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 384 break; 385 case 2: 386 icu_base = ic1_base; 387 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 388 break; 389 case 3: 390 icu_base = ic1_base; 391 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 392 break; 393 } 394 irqmask = REGVAL(icu_base + IC_MASK_READ); 395 au_cpuintrs[level].cintr_count.ev_count++; 396 LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) { 397 int mask = ih->ih_mask; 398 399 if (mask & irqmask & irqstat) { 400 au_icu_intrtab[ih->ih_irq].intr_count.ev_count++; 401 (*ih->ih_func)(ih->ih_arg); 402 403 if (REGVAL(icu_base + IC_MASK_READ) & mask) { 404 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 405 REGVAL(icu_base + IC_MASK_SET) = mask; 406 wbflush(); 407 } 408 } 409 } 410 cause &= ~(MIPS_INT_MASK_0 << level); 411 } 412 413 /* Re-enable anything that we have processed. */ 414 _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK)); 415 } 416 417 /* 418 * Some devices (e.g. PCMCIA) want to be able to mask interrupts at 419 * the ICU, and leave them masked off until some later time 420 * (e.g. reenabled by a soft interrupt). 421 */ 422 423 void 424 au_intr_enable(int irq) 425 { 426 int s; 427 uint32_t icu_base, mask; 428 429 if (irq >= NIRQS) 430 panic("au_intr_enable: bogus IRQ %d", irq); 431 432 icu_base = (irq < 32) ? ic0_base : ic1_base; 433 mask = irq & 31; 434 mask = 1 << mask; 435 436 s = splhigh(); 437 /* only enable the interrupt if we have a handler */ 438 if (au_icu_intrtab[irq].intr_refcnt) { 439 REGVAL(icu_base + IC_MASK_SET) = mask; 440 REGVAL(icu_base + IC_WAKEUP_SET) = mask; 441 wbflush(); 442 } 443 splx(s); 444 } 445 446 void 447 au_intr_disable(int irq) 448 { 449 int s; 450 uint32_t icu_base, mask; 451 452 if (irq >= NIRQS) 453 panic("au_intr_disable: bogus IRQ %d", irq); 454 455 icu_base = (irq < 32) ? ic0_base : ic1_base; 456 mask = irq & 31; 457 mask = 1 << mask; 458 459 s = splhigh(); 460 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 461 REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask; 462 wbflush(); 463 splx(s); 464 } 465
Indexes created Sun Sep 28 16:09:52 GMT 2025