au_icu.c revision 1.21.30.1
1 /* $NetBSD: au_icu.c,v 1.21.30.1 2007/12/08 18:17:22 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 2001 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Jason R. Thorpe. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the NetBSD 52 * Foundation, Inc. and its contributors. 53 * 4. Neither the name of The NetBSD Foundation nor the names of its 54 * contributors may be used to endorse or promote products derived 55 * from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 /* 71 * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs. 72 * 73 * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal 74 * interrupt controllers. 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.21.30.1 2007/12/08 18:17:22 mjf Exp $"); 79 80 #include "opt_ddb.h" 81 82 #include <sys/param.h> 83 #include <sys/queue.h> 84 #include <sys/malloc.h> 85 #include <sys/systm.h> 86 #include <sys/device.h> 87 #include <sys/kernel.h> 88 89 #include <machine/bus.h> 90 #include <machine/intr.h> 91 92 #include <mips/locore.h> 93 #include <mips/alchemy/include/aureg.h> 94 #include <mips/alchemy/include/auvar.h> 95 96 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 97 98 /* 99 * This is a mask of bits to clear in the SR when we go to a 100 * given hardware interrupt priority level. 101 */ 102 103 const uint32_t ipl_sr_bits[_IPL_N] = { 104 0, /* 0: IPL_NONE */ 105 MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFTCLOCK */ 106 MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTNET */ 107 MIPS_SOFT_INT_MASK_0| 108 MIPS_SOFT_INT_MASK_1| 109 MIPS_INT_MASK_0, /* 3: IPL_VM */ 110 MIPS_SOFT_INT_MASK_0| 111 MIPS_SOFT_INT_MASK_1| 112 MIPS_INT_MASK_0| 113 MIPS_INT_MASK_1| 114 MIPS_INT_MASK_2| 115 MIPS_INT_MASK_3| 116 MIPS_INT_MASK_4| 117 MIPS_INT_MASK_5, /* 4: IPL_{SCHED,HIGH} */ 118 }; 119 120 #define NIRQS 64 121 122 struct au_icu_intrhead { 123 struct evcnt intr_count; 124 int intr_refcnt; 125 }; 126 struct au_icu_intrhead au_icu_intrtab[NIRQS]; 127 128 #define NINTRS 4 /* MIPS INT0 - INT3 */ 129 130 struct au_intrhand { 131 LIST_ENTRY(au_intrhand) ih_q; 132 int (*ih_func)(void *); 133 void *ih_arg; 134 int ih_irq; 135 int ih_mask; 136 }; 137 138 struct au_cpuintr { 139 LIST_HEAD(, au_intrhand) cintr_list; 140 struct evcnt cintr_count; 141 }; 142 143 struct au_cpuintr au_cpuintrs[NINTRS]; 144 const char *au_cpuintrnames[NINTRS] = { 145 "icu 0, req 0", 146 "icu 0, req 1", 147 "icu 1, req 0", 148 "icu 1, req 1", 149 }; 150 151 static bus_addr_t ic0_base, ic1_base; 152 153 void 154 au_intr_init(void) 155 { 156 int i; 157 struct au_chipdep *chip; 158 159 for (i = 0; i < NINTRS; i++) { 160 LIST_INIT(&au_cpuintrs[i].cintr_list); 161 evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count, 162 EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]); 163 } 164 165 chip = au_chipdep(); 166 KASSERT(chip != NULL); 167 168 ic0_base = chip->icus[0]; 169 ic1_base = chip->icus[1]; 170 171 for (i = 0; i < NIRQS; i++) { 172 au_icu_intrtab[i].intr_refcnt = 0; 173 evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count, 174 EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]); 175 } 176 177 /* start with all interrupts masked */ 178 REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff; 179 REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff; 180 REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff; 181 REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff; 182 REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff; 183 REGVAL(ic0_base + IC_TEST_BIT) = 0; 184 185 REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff; 186 REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff; 187 REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff; 188 REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff; 189 REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff; 190 REGVAL(ic1_base + IC_TEST_BIT) = 0; 191 } 192 193 void * 194 au_intr_establish(int irq, int req, int level, int type, 195 int (*func)(void *), void *arg) 196 { 197 struct au_intrhand *ih; 198 uint32_t icu_base; 199 int cpu_int, s; 200 struct au_chipdep *chip; 201 202 chip = au_chipdep(); 203 KASSERT(chip != NULL); 204 205 if (irq >= NIRQS) 206 panic("au_intr_establish: bogus IRQ %d", irq); 207 if (req > 1) 208 panic("au_intr_establish: bogus request %d", req); 209 210 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 211 if (ih == NULL) 212 return (NULL); 213 214 ih->ih_func = func; 215 ih->ih_arg = arg; 216 ih->ih_irq = irq; 217 ih->ih_mask = (1 << (irq & 31)); 218 219 s = splhigh(); 220 221 /* 222 * First, link it into the tables. 223 * XXX do we want a separate list (really, should only be one item, not 224 * a list anyway) per irq, not per CPU interrupt? 225 */ 226 cpu_int = (irq < 32 ? 0 : 2) + req; 227 LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q); 228 229 /* 230 * Now enable it. 231 */ 232 if (au_icu_intrtab[irq].intr_refcnt++ == 0) { 233 icu_base = (irq < 32) ? ic0_base : ic1_base; 234 235 irq &= 31; /* throw away high bit if set */ 236 irq = 1 << irq; /* only used as a mask from here on */ 237 238 /* XXX Only level interrupts for now */ 239 switch (type) { 240 case IST_NONE: 241 case IST_PULSE: 242 case IST_EDGE: 243 panic("unsupported irq type %d", type); 244 /* NOTREACHED */ 245 case IST_LEVEL: 246 case IST_LEVEL_HIGH: 247 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 248 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 249 REGVAL(icu_base + IC_CONFIG0_SET) = irq; 250 break; 251 case IST_LEVEL_LOW: 252 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 253 REGVAL(icu_base + IC_CONFIG1_SET) = irq; 254 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 255 break; 256 } 257 wbflush(); 258 259 /* XXX handle GPIO interrupts - not done at all yet */ 260 if (cpu_int & 0x1) 261 REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq; 262 else 263 REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq; 264 265 /* Associate interrupt with peripheral */ 266 REGVAL(icu_base + IC_SOURCE_SET) = irq; 267 268 /* Actually enable the interrupt */ 269 REGVAL(icu_base + IC_MASK_SET) = irq; 270 271 /* And allow the interrupt to interrupt idle */ 272 REGVAL(icu_base + IC_WAKEUP_SET) = irq; 273 274 wbflush(); 275 } 276 splx(s); 277 278 return (ih); 279 } 280 281 void 282 au_intr_disestablish(void *cookie) 283 { 284 struct au_intrhand *ih = cookie; 285 uint32_t icu_base; 286 int irq, s; 287 288 irq = ih->ih_irq; 289 290 s = splhigh(); 291 292 /* 293 * First, remove it from the table. 294 */ 295 LIST_REMOVE(ih, ih_q); 296 297 /* 298 * Now, disable it, if there is nothing remaining on the 299 * list. 300 */ 301 if (au_icu_intrtab[irq].intr_refcnt-- == 1) { 302 icu_base = (irq < 32) ? ic0_base : ic1_base; 303 304 irq &= 31; /* throw away high bit if set */ 305 irq = 1 << irq; /* only used as a mask from here on */ 306 307 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq; 308 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 309 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 310 311 /* disable with MASK_CLEAR and WAKEUP_CLEAR */ 312 REGVAL(icu_base + IC_MASK_CLEAR) = irq; 313 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq; 314 wbflush(); 315 } 316 317 splx(s); 318 319 free(ih, M_DEVBUF); 320 } 321 322 void 323 au_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 324 { 325 struct au_intrhand *ih; 326 int level; 327 uint32_t icu_base, irqstat, irqmask; 328 329 icu_base = irqstat = 0; 330 331 for (level = 3; level >= 0; level--) { 332 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 333 continue; 334 335 /* 336 * XXX the following may well be slow to execute. 337 * investigate and possibly speed up. 338 * 339 * is something like: 340 * 341 * irqstat = REGVAL( 342 * (level & 4 == 0) ? IC0_BASE ? IC1_BASE + 343 * (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT); 344 * 345 * be any better? 346 * 347 */ 348 switch (level) { 349 case 0: 350 icu_base = ic0_base; 351 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 352 break; 353 case 1: 354 icu_base = ic0_base; 355 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 356 break; 357 case 2: 358 icu_base = ic1_base; 359 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 360 break; 361 case 3: 362 icu_base = ic1_base; 363 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 364 break; 365 } 366 irqmask = REGVAL(icu_base + IC_MASK_READ); 367 au_cpuintrs[level].cintr_count.ev_count++; 368 LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) { 369 int mask = ih->ih_mask; 370 371 if (mask & irqmask & irqstat) { 372 au_icu_intrtab[ih->ih_irq].intr_count.ev_count++; 373 (*ih->ih_func)(ih->ih_arg); 374 375 if (REGVAL(icu_base + IC_MASK_READ) & mask) { 376 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 377 REGVAL(icu_base + IC_MASK_SET) = mask; 378 wbflush(); 379 } 380 } 381 } 382 cause &= ~(MIPS_INT_MASK_0 << level); 383 } 384 385 /* Re-enable anything that we have processed. */ 386 _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK)); 387 } 388 389 /* 390 * Some devices (e.g. PCMCIA) want to be able to mask interrupts at 391 * the ICU, and leave them masked off until some later time 392 * (e.g. reenabled by a soft interrupt). 393 */ 394 395 void 396 au_intr_enable(int irq) 397 { 398 int s; 399 uint32_t icu_base, mask; 400 401 if (irq >= NIRQS) 402 panic("au_intr_enable: bogus IRQ %d", irq); 403 404 icu_base = (irq < 32) ? ic0_base : ic1_base; 405 mask = irq & 31; 406 mask = 1 << mask; 407 408 s = splhigh(); 409 /* only enable the interrupt if we have a handler */ 410 if (au_icu_intrtab[irq].intr_refcnt) { 411 REGVAL(icu_base + IC_MASK_SET) = mask; 412 REGVAL(icu_base + IC_WAKEUP_SET) = mask; 413 wbflush(); 414 } 415 splx(s); 416 } 417 418 void 419 au_intr_disable(int irq) 420 { 421 int s; 422 uint32_t icu_base, mask; 423 424 if (irq >= NIRQS) 425 panic("au_intr_disable: bogus IRQ %d", irq); 426 427 icu_base = (irq < 32) ? ic0_base : ic1_base; 428 mask = irq & 31; 429 mask = 1 << mask; 430 431 s = splhigh(); 432 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 433 REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask; 434 wbflush(); 435 splx(s); 436 } 437
Indexes created Mon Oct 20 11:09:49 GMT 2025