au_icu.c revision 1.26
1 /* $NetBSD: au_icu.c,v 1.26 2011/02/20 07:48:36 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 2001 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Jason R. Thorpe. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs. 65 * 66 * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal 67 * interrupt controllers. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.26 2011/02/20 07:48:36 matt Exp $"); 72 73 #include "opt_ddb.h" 74 #define __INTR_PRIVATE 75 76 #include <sys/param.h> 77 #include <sys/queue.h> 78 #include <sys/malloc.h> 79 #include <sys/systm.h> 80 #include <sys/device.h> 81 #include <sys/kernel.h> 82 83 #include <machine/bus.h> 84 #include <machine/intr.h> 85 86 #include <mips/locore.h> 87 #include <mips/alchemy/include/aureg.h> 88 #include <mips/alchemy/include/auvar.h> 89 90 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 91 92 /* 93 * This is a mask of bits to clear in the SR when we go to a 94 * given hardware interrupt priority level. 95 */ 96 97 static const struct ipl_sr_map alchemy_ipl_sr_map = { 98 .sr_bits = { 99 [IPL_NONE] = 0, 100 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 101 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0, 102 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, 103 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK, 104 [IPL_VM] = MIPS_SOFT_INT_MASK|MIPS_INT_MASK_0, 105 [IPL_SCHED] = MIPS_INT_MASK, 106 [IPL_HIGH] = MIPS_INT_MASK, 107 }, 108 }; 109 110 #define NIRQS 64 111 112 struct au_icu_intrhead { 113 struct evcnt intr_count; 114 int intr_refcnt; 115 }; 116 struct au_icu_intrhead au_icu_intrtab[NIRQS]; 117 118 #define NINTRS 4 /* MIPS INT0 - INT3 */ 119 120 struct au_intrhand { 121 LIST_ENTRY(au_intrhand) ih_q; 122 int (*ih_func)(void *); 123 void *ih_arg; 124 int ih_irq; 125 int ih_mask; 126 }; 127 128 struct au_cpuintr { 129 LIST_HEAD(, au_intrhand) cintr_list; 130 struct evcnt cintr_count; 131 }; 132 133 struct au_cpuintr au_cpuintrs[NINTRS]; 134 const char * const au_cpuintrnames[NINTRS] = { 135 "icu 0, req 0", 136 "icu 0, req 1", 137 "icu 1, req 0", 138 "icu 1, req 1", 139 }; 140 141 static bus_addr_t ic0_base, ic1_base; 142 143 void 144 au_intr_init(void) 145 { 146 ipl_sr_map = alchemy_ipl_sr_map; 147 148 for (size_t i = 0; i < NINTRS; i++) { 149 LIST_INIT(&au_cpuintrs[i].cintr_list); 150 evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count, 151 EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]); 152 } 153 154 struct au_chipdep * const chip = au_chipdep(); 155 KASSERT(chip != NULL); 156 157 ic0_base = chip->icus[0]; 158 ic1_base = chip->icus[1]; 159 160 for (size_t i = 0; i < NIRQS; i++) { 161 au_icu_intrtab[i].intr_refcnt = 0; 162 evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count, 163 EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]); 164 } 165 166 /* start with all interrupts masked */ 167 REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff; 168 REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff; 169 REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff; 170 REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff; 171 REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff; 172 REGVAL(ic0_base + IC_TEST_BIT) = 0; 173 174 REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff; 175 REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff; 176 REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff; 177 REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff; 178 REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff; 179 REGVAL(ic1_base + IC_TEST_BIT) = 0; 180 } 181 182 void * 183 au_intr_establish(int irq, int req, int level, int type, 184 int (*func)(void *), void *arg) 185 { 186 struct au_intrhand *ih; 187 uint32_t icu_base; 188 int cpu_int, s; 189 struct au_chipdep *chip; 190 191 chip = au_chipdep(); 192 KASSERT(chip != NULL); 193 194 if (irq >= NIRQS) 195 panic("au_intr_establish: bogus IRQ %d", irq); 196 if (req > 1) 197 panic("au_intr_establish: bogus request %d", req); 198 199 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 200 if (ih == NULL) 201 return (NULL); 202 203 ih->ih_func = func; 204 ih->ih_arg = arg; 205 ih->ih_irq = irq; 206 ih->ih_mask = (1 << (irq & 31)); 207 208 s = splhigh(); 209 210 /* 211 * First, link it into the tables. 212 * XXX do we want a separate list (really, should only be one item, not 213 * a list anyway) per irq, not per CPU interrupt? 214 */ 215 cpu_int = (irq < 32 ? 0 : 2) + req; 216 LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q); 217 218 /* 219 * Now enable it. 220 */ 221 if (au_icu_intrtab[irq].intr_refcnt++ == 0) { 222 icu_base = (irq < 32) ? ic0_base : ic1_base; 223 224 irq &= 31; /* throw away high bit if set */ 225 irq = 1 << irq; /* only used as a mask from here on */ 226 227 /* XXX Only level interrupts for now */ 228 switch (type) { 229 case IST_NONE: 230 case IST_PULSE: 231 case IST_EDGE: 232 panic("unsupported irq type %d", type); 233 /* NOTREACHED */ 234 case IST_LEVEL: 235 case IST_LEVEL_HIGH: 236 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 237 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 238 REGVAL(icu_base + IC_CONFIG0_SET) = irq; 239 break; 240 case IST_LEVEL_LOW: 241 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 242 REGVAL(icu_base + IC_CONFIG1_SET) = irq; 243 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 244 break; 245 } 246 wbflush(); 247 248 /* XXX handle GPIO interrupts - not done at all yet */ 249 if (cpu_int & 0x1) 250 REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq; 251 else 252 REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq; 253 254 /* Associate interrupt with peripheral */ 255 REGVAL(icu_base + IC_SOURCE_SET) = irq; 256 257 /* Actually enable the interrupt */ 258 REGVAL(icu_base + IC_MASK_SET) = irq; 259 260 /* And allow the interrupt to interrupt idle */ 261 REGVAL(icu_base + IC_WAKEUP_SET) = irq; 262 263 wbflush(); 264 } 265 splx(s); 266 267 return (ih); 268 } 269 270 void 271 au_intr_disestablish(void *cookie) 272 { 273 struct au_intrhand *ih = cookie; 274 uint32_t icu_base; 275 int irq, s; 276 277 irq = ih->ih_irq; 278 279 s = splhigh(); 280 281 /* 282 * First, remove it from the table. 283 */ 284 LIST_REMOVE(ih, ih_q); 285 286 /* 287 * Now, disable it, if there is nothing remaining on the 288 * list. 289 */ 290 if (au_icu_intrtab[irq].intr_refcnt-- == 1) { 291 icu_base = (irq < 32) ? ic0_base : ic1_base; 292 293 irq &= 31; /* throw away high bit if set */ 294 irq = 1 << irq; /* only used as a mask from here on */ 295 296 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq; 297 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 298 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 299 300 /* disable with MASK_CLEAR and WAKEUP_CLEAR */ 301 REGVAL(icu_base + IC_MASK_CLEAR) = irq; 302 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq; 303 wbflush(); 304 } 305 306 splx(s); 307 308 free(ih, M_DEVBUF); 309 } 310 311 void 312 au_iointr(int ipl, vaddr_t pc, uint32_t ipending) 313 { 314 struct au_intrhand *ih; 315 int level; 316 uint32_t icu_base, irqstat, irqmask; 317 318 icu_base = irqstat = 0; 319 320 for (level = 3; level >= 0; level--) { 321 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 322 continue; 323 324 /* 325 * XXX the following may well be slow to execute. 326 * investigate and possibly speed up. 327 * 328 * is something like: 329 * 330 * irqstat = REGVAL( 331 * (level & 4 == 0) ? IC0_BASE ? IC1_BASE + 332 * (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT); 333 * 334 * be any better? 335 * 336 */ 337 switch (level) { 338 case 0: 339 icu_base = ic0_base; 340 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 341 break; 342 case 1: 343 icu_base = ic0_base; 344 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 345 break; 346 case 2: 347 icu_base = ic1_base; 348 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 349 break; 350 case 3: 351 icu_base = ic1_base; 352 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 353 break; 354 } 355 irqmask = REGVAL(icu_base + IC_MASK_READ); 356 au_cpuintrs[level].cintr_count.ev_count++; 357 LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) { 358 int mask = ih->ih_mask; 359 360 if (mask & irqmask & irqstat) { 361 au_icu_intrtab[ih->ih_irq].intr_count.ev_count++; 362 (*ih->ih_func)(ih->ih_arg); 363 364 if (REGVAL(icu_base + IC_MASK_READ) & mask) { 365 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 366 REGVAL(icu_base + IC_MASK_SET) = mask; 367 wbflush(); 368 } 369 } 370 } 371 } 372 } 373 374 /* 375 * Some devices (e.g. PCMCIA) want to be able to mask interrupts at 376 * the ICU, and leave them masked off until some later time 377 * (e.g. reenabled by a soft interrupt). 378 */ 379 380 void 381 au_intr_enable(int irq) 382 { 383 int s; 384 uint32_t icu_base, mask; 385 386 if (irq >= NIRQS) 387 panic("au_intr_enable: bogus IRQ %d", irq); 388 389 icu_base = (irq < 32) ? ic0_base : ic1_base; 390 mask = irq & 31; 391 mask = 1 << mask; 392 393 s = splhigh(); 394 /* only enable the interrupt if we have a handler */ 395 if (au_icu_intrtab[irq].intr_refcnt) { 396 REGVAL(icu_base + IC_MASK_SET) = mask; 397 REGVAL(icu_base + IC_WAKEUP_SET) = mask; 398 wbflush(); 399 } 400 splx(s); 401 } 402 403 void 404 au_intr_disable(int irq) 405 { 406 int s; 407 uint32_t icu_base, mask; 408 409 if (irq >= NIRQS) 410 panic("au_intr_disable: bogus IRQ %d", irq); 411 412 icu_base = (irq < 32) ? ic0_base : ic1_base; 413 mask = irq & 31; 414 mask = 1 << mask; 415 416 s = splhigh(); 417 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 418 REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask; 419 wbflush(); 420 splx(s); 421 } 422
Indexes created Sat Sep 27 14:09:57 GMT 2025