au_icu.c revision 1.28
1 /* $NetBSD: au_icu.c,v 1.28 2011/07/10 23:13:23 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 2001 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Jason R. Thorpe. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs. 65 * 66 * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal 67 * interrupt controllers. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.28 2011/07/10 23:13:23 matt Exp $"); 72 73 #include "opt_ddb.h" 74 #define __INTR_PRIVATE 75 76 #include <sys/param.h> 77 #include <sys/bus.h> 78 #include <sys/device.h> 79 #include <sys/intr.h> 80 #include <sys/kernel.h> 81 #include <sys/malloc.h> 82 #include <sys/systm.h> 83 84 #include <mips/locore.h> 85 #include <mips/alchemy/include/aureg.h> 86 #include <mips/alchemy/include/auvar.h> 87 88 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 89 90 /* 91 * This is a mask of bits to clear in the SR when we go to a 92 * given hardware interrupt priority level. 93 */ 94 95 static const struct ipl_sr_map alchemy_ipl_sr_map = { 96 .sr_bits = { 97 [IPL_NONE] = 0, 98 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 99 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0, 100 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, 101 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK, 102 [IPL_VM] = MIPS_SOFT_INT_MASK|MIPS_INT_MASK_0, 103 [IPL_SCHED] = MIPS_INT_MASK, 104 [IPL_HIGH] = MIPS_INT_MASK, 105 }, 106 }; 107 108 #define NIRQS 64 109 110 struct au_icu_intrhead { 111 struct evcnt intr_count; 112 int intr_refcnt; 113 }; 114 struct au_icu_intrhead au_icu_intrtab[NIRQS]; 115 116 #define NINTRS 4 /* MIPS INT0 - INT3 */ 117 118 struct au_intrhand { 119 LIST_ENTRY(au_intrhand) ih_q; 120 int (*ih_func)(void *); 121 void *ih_arg; 122 int ih_irq; 123 int ih_mask; 124 }; 125 126 struct au_cpuintr { 127 LIST_HEAD(, au_intrhand) cintr_list; 128 struct evcnt cintr_count; 129 }; 130 131 struct au_cpuintr au_cpuintrs[NINTRS]; 132 const char * const au_cpuintrnames[NINTRS] = { 133 "icu 0, req 0", 134 "icu 0, req 1", 135 "icu 1, req 0", 136 "icu 1, req 1", 137 }; 138 139 static bus_addr_t ic0_base, ic1_base; 140 141 void 142 au_intr_init(void) 143 { 144 ipl_sr_map = alchemy_ipl_sr_map; 145 146 for (size_t i = 0; i < NINTRS; i++) { 147 LIST_INIT(&au_cpuintrs[i].cintr_list); 148 evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count, 149 EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]); 150 } 151 152 struct au_chipdep * const chip = au_chipdep(); 153 KASSERT(chip != NULL); 154 155 ic0_base = chip->icus[0]; 156 ic1_base = chip->icus[1]; 157 158 for (size_t i = 0; i < NIRQS; i++) { 159 au_icu_intrtab[i].intr_refcnt = 0; 160 evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count, 161 EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]); 162 } 163 164 /* start with all interrupts masked */ 165 REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff; 166 REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff; 167 REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff; 168 REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff; 169 REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff; 170 REGVAL(ic0_base + IC_TEST_BIT) = 0; 171 172 REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff; 173 REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff; 174 REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff; 175 REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff; 176 REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff; 177 REGVAL(ic1_base + IC_TEST_BIT) = 0; 178 } 179 180 void * 181 au_intr_establish(int irq, int req, int level, int type, 182 int (*func)(void *), void *arg) 183 { 184 struct au_intrhand *ih; 185 uint32_t icu_base; 186 int cpu_int, s; 187 struct au_chipdep *chip; 188 189 chip = au_chipdep(); 190 KASSERT(chip != NULL); 191 192 if (irq >= NIRQS) 193 panic("au_intr_establish: bogus IRQ %d", irq); 194 if (req > 1) 195 panic("au_intr_establish: bogus request %d", req); 196 197 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 198 if (ih == NULL) 199 return (NULL); 200 201 ih->ih_func = func; 202 ih->ih_arg = arg; 203 ih->ih_irq = irq; 204 ih->ih_mask = (1 << (irq & 31)); 205 206 s = splhigh(); 207 208 /* 209 * First, link it into the tables. 210 * XXX do we want a separate list (really, should only be one item, not 211 * a list anyway) per irq, not per CPU interrupt? 212 */ 213 cpu_int = (irq < 32 ? 0 : 2) + req; 214 LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q); 215 216 /* 217 * Now enable it. 218 */ 219 if (au_icu_intrtab[irq].intr_refcnt++ == 0) { 220 icu_base = (irq < 32) ? ic0_base : ic1_base; 221 222 irq &= 31; /* throw away high bit if set */ 223 irq = 1 << irq; /* only used as a mask from here on */ 224 225 /* XXX Only level interrupts for now */ 226 switch (type) { 227 case IST_NONE: 228 case IST_PULSE: 229 case IST_EDGE: 230 panic("unsupported irq type %d", type); 231 /* NOTREACHED */ 232 case IST_LEVEL: 233 case IST_LEVEL_HIGH: 234 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 235 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 236 REGVAL(icu_base + IC_CONFIG0_SET) = irq; 237 break; 238 case IST_LEVEL_LOW: 239 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 240 REGVAL(icu_base + IC_CONFIG1_SET) = irq; 241 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 242 break; 243 } 244 wbflush(); 245 246 /* XXX handle GPIO interrupts - not done at all yet */ 247 if (cpu_int & 0x1) 248 REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq; 249 else 250 REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq; 251 252 /* Associate interrupt with peripheral */ 253 REGVAL(icu_base + IC_SOURCE_SET) = irq; 254 255 /* Actually enable the interrupt */ 256 REGVAL(icu_base + IC_MASK_SET) = irq; 257 258 /* And allow the interrupt to interrupt idle */ 259 REGVAL(icu_base + IC_WAKEUP_SET) = irq; 260 261 wbflush(); 262 } 263 splx(s); 264 265 return (ih); 266 } 267 268 void 269 au_intr_disestablish(void *cookie) 270 { 271 struct au_intrhand *ih = cookie; 272 uint32_t icu_base; 273 int irq, s; 274 275 irq = ih->ih_irq; 276 277 s = splhigh(); 278 279 /* 280 * First, remove it from the table. 281 */ 282 LIST_REMOVE(ih, ih_q); 283 284 /* 285 * Now, disable it, if there is nothing remaining on the 286 * list. 287 */ 288 if (au_icu_intrtab[irq].intr_refcnt-- == 1) { 289 icu_base = (irq < 32) ? ic0_base : ic1_base; 290 291 irq &= 31; /* throw away high bit if set */ 292 irq = 1 << irq; /* only used as a mask from here on */ 293 294 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq; 295 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 296 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 297 298 /* disable with MASK_CLEAR and WAKEUP_CLEAR */ 299 REGVAL(icu_base + IC_MASK_CLEAR) = irq; 300 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq; 301 wbflush(); 302 } 303 304 splx(s); 305 306 free(ih, M_DEVBUF); 307 } 308 309 void 310 au_iointr(int ipl, vaddr_t pc, uint32_t ipending) 311 { 312 struct au_intrhand *ih; 313 int level; 314 uint32_t icu_base, irqstat, irqmask; 315 316 icu_base = irqstat = 0; 317 318 for (level = 3; level >= 0; level--) { 319 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 320 continue; 321 322 /* 323 * XXX the following may well be slow to execute. 324 * investigate and possibly speed up. 325 * 326 * is something like: 327 * 328 * irqstat = REGVAL( 329 * (level & 4 == 0) ? IC0_BASE ? IC1_BASE + 330 * (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT); 331 * 332 * be any better? 333 * 334 */ 335 switch (level) { 336 case 0: 337 icu_base = ic0_base; 338 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 339 break; 340 case 1: 341 icu_base = ic0_base; 342 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 343 break; 344 case 2: 345 icu_base = ic1_base; 346 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 347 break; 348 case 3: 349 icu_base = ic1_base; 350 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 351 break; 352 } 353 irqmask = REGVAL(icu_base + IC_MASK_READ); 354 au_cpuintrs[level].cintr_count.ev_count++; 355 LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) { 356 int mask = ih->ih_mask; 357 358 if (mask & irqmask & irqstat) { 359 au_icu_intrtab[ih->ih_irq].intr_count.ev_count++; 360 (*ih->ih_func)(ih->ih_arg); 361 362 if (REGVAL(icu_base + IC_MASK_READ) & mask) { 363 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 364 REGVAL(icu_base + IC_MASK_SET) = mask; 365 wbflush(); 366 } 367 } 368 } 369 } 370 } 371 372 /* 373 * Some devices (e.g. PCMCIA) want to be able to mask interrupts at 374 * the ICU, and leave them masked off until some later time 375 * (e.g. reenabled by a soft interrupt). 376 */ 377 378 void 379 au_intr_enable(int irq) 380 { 381 int s; 382 uint32_t icu_base, mask; 383 384 if (irq >= NIRQS) 385 panic("au_intr_enable: bogus IRQ %d", irq); 386 387 icu_base = (irq < 32) ? ic0_base : ic1_base; 388 mask = irq & 31; 389 mask = 1 << mask; 390 391 s = splhigh(); 392 /* only enable the interrupt if we have a handler */ 393 if (au_icu_intrtab[irq].intr_refcnt) { 394 REGVAL(icu_base + IC_MASK_SET) = mask; 395 REGVAL(icu_base + IC_WAKEUP_SET) = mask; 396 wbflush(); 397 } 398 splx(s); 399 } 400 401 void 402 au_intr_disable(int irq) 403 { 404 int s; 405 uint32_t icu_base, mask; 406 407 if (irq >= NIRQS) 408 panic("au_intr_disable: bogus IRQ %d", irq); 409 410 icu_base = (irq < 32) ? ic0_base : ic1_base; 411 mask = irq & 31; 412 mask = 1 << mask; 413 414 s = splhigh(); 415 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 416 REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask; 417 wbflush(); 418 splx(s); 419 } 420
Indexes created Mon Sep 29 21:09:56 GMT 2025