au_wired_space.c revision 1.1
1 /* $NetBSD: au_wired_space.c,v 1.1 2006/02/06 03:07:44 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 39 * Simulation Facility, NASA Ames Research Center. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the NetBSD 52 * Foundation, Inc. and its contributors. 53 * 4. Neither the name of The NetBSD Foundation nor the names of its 54 * contributors may be used to endorse or promote products derived 55 * from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: au_wired_space.c,v 1.1 2006/02/06 03:07:44 gdamore Exp $"); 72 73 /* 74 * This provides mappings for the upper I/O regions used on some 75 * Alchemy parts, e.g. PCI and PCMCIA spaces. These spaces require 76 * the use of wired TLB entries. 77 * 78 * Earlier Alchemy parts with all of peripherials located in the 79 * bottom 4GB of physical memory, do not need this. 80 */ 81 82 #include <sys/param.h> 83 #include <sys/systm.h> 84 #include <sys/extent.h> 85 #include <sys/malloc.h> 86 #include <sys/endian.h> 87 88 #include <machine/bus.h> 89 #include <machine/locore.h> 90 #include <machine/wired_map.h> 91 #include <mips/alchemy/include/au_wired_space.h> 92 93 #ifndef AU_WIRED_EXTENT_SZ 94 #define AU_WIRED_EXTENT_SZ EXTENT_FIXED_STORAGE_SIZE(10) 95 #endif 96 97 typedef struct au_wired_cookie { 98 const char *c_name; 99 bus_addr_t c_start; 100 bus_size_t c_size; 101 paddr_t c_pbase; 102 int c_flags; 103 int c_swswap; 104 boolean_t c_hwswap; 105 struct extent *c_extent; 106 long c_exstore[AU_WIRED_EXTENT_SZ/sizeof (long)]; 107 } au_wired_cookie_t; 108 109 int au_wired_map(void *, bus_addr_t, bus_size_t, int, 110 bus_space_handle_t *, int); 111 void au_wired_unmap(void *, bus_space_handle_t, bus_size_t, int); 112 void *au_wired_vaddr(void *, bus_space_handle_t); 113 int au_wired_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t, 114 bus_space_handle_t *); 115 paddr_t au_wired_mmap(void *, bus_addr_t, off_t, int, int); 116 int au_wired_alloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, 117 bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 118 void au_wired_free(void *, bus_space_handle_t, bus_size_t); 119 void au_wired_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int); 120 uint8_t au_wired_r_1(void *, bus_space_handle_t, bus_size_t); 121 uint16_t au_wired_r_2(void *, bus_space_handle_t, bus_size_t); 122 uint32_t au_wired_r_4(void *, bus_space_handle_t, bus_size_t); 123 uint64_t au_wired_r_8(void *, bus_space_handle_t, bus_size_t); 124 void au_wired_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, 125 bus_size_t); 126 void au_wired_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 127 bus_size_t); 128 void au_wired_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 129 bus_size_t); 130 void au_wired_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 131 bus_size_t); 132 void au_wired_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, 133 bus_size_t); 134 void au_wired_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 135 bus_size_t); 136 void au_wired_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 137 bus_size_t); 138 void au_wired_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 139 bus_size_t); 140 void au_wired_w_1(void *, bus_space_handle_t, bus_size_t, uint8_t); 141 void au_wired_w_2(void *, bus_space_handle_t, bus_size_t, uint16_t); 142 void au_wired_w_4(void *, bus_space_handle_t, bus_size_t, uint32_t); 143 void au_wired_w_8(void *, bus_space_handle_t, bus_size_t, uint64_t); 144 void au_wired_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 145 bus_size_t); 146 void au_wired_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 147 bus_size_t); 148 void au_wired_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 149 bus_size_t); 150 void au_wired_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 151 bus_size_t); 152 void au_wired_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 153 bus_size_t); 154 void au_wired_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 155 bus_size_t); 156 void au_wired_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 157 bus_size_t); 158 void au_wired_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 159 bus_size_t); 160 void au_wired_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t, 161 bus_size_t); 162 void au_wired_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, 163 bus_size_t); 164 void au_wired_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, 165 bus_size_t); 166 void au_wired_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t, 167 bus_size_t); 168 void au_wired_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t, 169 bus_size_t); 170 void au_wired_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, 171 bus_size_t); 172 void au_wired_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, 173 bus_size_t); 174 void au_wired_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t, 175 bus_size_t); 176 void au_wired_c_1(void *, bus_space_handle_t, bus_size_t, 177 bus_space_handle_t, bus_size_t, bus_size_t); 178 void au_wired_c_2(void *, bus_space_handle_t, bus_size_t, 179 bus_space_handle_t, bus_size_t, bus_size_t); 180 void au_wired_c_4(void *, bus_space_handle_t, bus_size_t, 181 bus_space_handle_t, bus_size_t, bus_size_t); 182 void au_wired_c_8(void *, bus_space_handle_t, bus_size_t, 183 bus_space_handle_t, bus_size_t, bus_size_t); 184 uint16_t au_wired_rs_2(void *, bus_space_handle_t, bus_size_t); 185 uint32_t au_wired_rs_4(void *, bus_space_handle_t, bus_size_t); 186 uint64_t au_wired_rs_8(void *, bus_space_handle_t, bus_size_t); 187 void au_wired_ws_2(void *, bus_space_handle_t, bus_size_t, uint16_t); 188 void au_wired_ws_4(void *, bus_space_handle_t, bus_size_t, uint32_t); 189 void au_wired_ws_8(void *, bus_space_handle_t, bus_size_t, uint64_t); 190 void au_wired_rms_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 191 bus_size_t); 192 void au_wired_rms_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 193 bus_size_t); 194 void au_wired_rms_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 195 bus_size_t); 196 void au_wired_rrs_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 197 bus_size_t); 198 void au_wired_rrs_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 199 bus_size_t); 200 void au_wired_rrs_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 201 bus_size_t); 202 void au_wired_wms_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 203 bus_size_t); 204 void au_wired_wms_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 205 bus_size_t); 206 void au_wired_wms_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 207 bus_size_t); 208 void au_wired_wrs_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 209 bus_size_t); 210 void au_wired_wrs_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 211 bus_size_t); 212 void au_wired_wrs_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 213 bus_size_t); 214 215 int 216 au_wired_map(void *cookie, bus_addr_t addr, bus_size_t size, 217 int flags, bus_space_handle_t *bshp, int acct) 218 { 219 int err; 220 au_wired_cookie_t *c = (au_wired_cookie_t *)cookie; 221 paddr_t pa; 222 223 /* make sure we can map this bus address */ 224 if (addr < c->c_start || 225 addr + size > c->c_start + c->c_size) 226 return EINVAL; 227 228 pa = c->c_pbase + (addr - c->c_start); 229 230 if (!mips3_wired_enter_region(addr, pa, size)) 231 return ENOMEM; 232 233 /* 234 * bus addresses are taken from virtual address space. 235 */ 236 if (acct && c->c_extent != NULL) { 237 err = extent_alloc_region(c->c_extent, addr, size, EX_NOWAIT); 238 if (err) 239 return err; 240 } 241 242 *bshp = addr; 243 244 return 0; 245 } 246 247 void 248 au_wired_unmap(void *cookie, bus_space_handle_t bsh, bus_size_t size, int acct) 249 { 250 au_wired_cookie_t *c = (au_wired_cookie_t *)cookie; 251 252 if (acct != 0 && c->c_extent != NULL) { 253 extent_free(c->c_extent, (vaddr_t)bsh, size, EX_NOWAIT); 254 } 255 } 256 257 int 258 au_wired_subregion(void *cookie, bus_space_handle_t bsh, 259 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 260 { 261 262 *nbshp = bsh + offset; 263 return 0; 264 } 265 266 void * 267 au_wired_vaddr(void *cookie, bus_space_handle_t bsh) 268 { 269 270 return ((void *)bsh); 271 } 272 273 paddr_t 274 au_wired_mmap(void *cookie, bus_addr_t addr, off_t off, int prot, int flags) 275 { 276 au_wired_cookie_t *c = (au_wired_cookie_t *)cookie; 277 278 /* I/O spaces should not be directly mmap'ed */ 279 if (c->c_flags & AU_WIRED_SPACE_IO) 280 return -1; 281 282 if (addr < c->c_start || (addr + off) >= (c->c_start + c->c_size)) 283 return -1; 284 285 return mips_btop(c->c_pbase + (addr - c->c_start) + off); 286 } 287 288 int 289 au_wired_alloc(void *cookie, bus_addr_t start, bus_addr_t end, 290 bus_size_t size, bus_size_t align, bus_size_t boundary, int flags, 291 bus_addr_t *addrp, bus_space_handle_t *bshp) 292 { 293 au_wired_cookie_t *c = (au_wired_cookie_t *)cookie; 294 vaddr_t addr; 295 int err; 296 paddr_t pa; 297 298 if (c->c_extent == NULL) 299 panic("au_wired_alloc: extent map %s not avail", c->c_name); 300 301 if (start < c->c_start || ((start + size) > (c->c_start + c->c_size))) 302 return EINVAL; 303 304 err = extent_alloc_subregion(c->c_extent, start, end, size, 305 align, boundary, EX_FAST | EX_NOWAIT, &addr); 306 if (err) 307 return err; 308 309 pa = c->c_pbase + (addr - c->c_start); 310 311 if (!mips3_wired_enter_region(addr, pa, size)) 312 return ENOMEM; 313 314 *bshp = addr; 315 *addrp = addr; 316 return 0; 317 } 318 319 void 320 au_wired_free(void *cookie, bus_space_handle_t bsh, bus_size_t size) 321 { 322 323 /* unmap takes care of it all */ 324 au_wired_unmap(cookie, bsh, size, 1); 325 } 326 327 inline void 328 au_wired_barrier(void *cookie, bus_space_handle_t bsh, bus_size_t o, 329 bus_size_t l, int f) 330 { 331 332 if (f & BUS_SPACE_BARRIER_WRITE) 333 wbflush(); 334 } 335 336 inline uint8_t 337 au_wired_r_1(void *v, bus_space_handle_t h, bus_size_t o) 338 { 339 340 return (*(volatile uint8_t *)(h + o)); 341 } 342 343 inline uint16_t 344 au_wired_r_2(void *v, bus_space_handle_t h, bus_size_t o) 345 { 346 uint16_t val = (*(volatile uint16_t *)(h + o)); 347 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 348 349 return (c->c_swswap ? bswap16(val) : val); 350 } 351 352 inline uint32_t 353 au_wired_r_4(void *v, bus_space_handle_t h, bus_size_t o) 354 { 355 uint32_t val = (*(volatile uint32_t *)(h + o)); 356 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 357 358 return (c->c_swswap ? bswap32(val) : val); 359 } 360 361 inline uint64_t 362 au_wired_r_8(void *v, bus_space_handle_t h, bus_size_t o) 363 { 364 uint64_t val = (*(volatile uint64_t *)(h + o)); 365 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 366 367 return (c->c_swswap ? bswap64(val) : val); 368 } 369 370 inline void 371 au_wired_w_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t val) 372 { 373 374 *(volatile uint8_t *)(h + o) = val; 375 } 376 377 inline void 378 au_wired_w_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t val) 379 { 380 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 381 382 *(volatile uint16_t *)(h + o) = c->c_swswap ? bswap16(val) : val; 383 } 384 385 inline void 386 au_wired_w_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t val) 387 { 388 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 389 390 *(volatile uint32_t *)(h + o) = c->c_swswap ? bswap32(val) : val; 391 } 392 393 inline void 394 au_wired_w_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t val) 395 { 396 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 397 398 *(volatile uint64_t *)(h + o) = c->c_swswap ? bswap64(val) : val; 399 } 400 401 inline uint16_t 402 au_wired_rs_2(void *v, bus_space_handle_t h, bus_size_t o) 403 { 404 uint16_t val = (*(volatile uint16_t *)(h + o)); 405 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 406 407 return (c->c_hwswap ? bswap16(val) : val); 408 } 409 410 inline uint32_t 411 au_wired_rs_4(void *v, bus_space_handle_t h, bus_size_t o) 412 { 413 uint32_t val = (*(volatile uint32_t *)(h + o)); 414 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 415 416 return (c->c_hwswap ? bswap32(val) : val); 417 } 418 419 inline uint64_t 420 au_wired_rs_8(void *v, bus_space_handle_t h, bus_size_t o) 421 { 422 uint64_t val = (*(volatile uint64_t *)(h + o)); 423 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 424 425 return (c->c_hwswap ? bswap64(val) : val); 426 } 427 428 inline void 429 au_wired_ws_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t val) 430 { 431 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 432 433 *(volatile uint16_t *)(h + o) = c->c_hwswap ? bswap16(val) : val; 434 } 435 436 inline void 437 au_wired_ws_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t val) 438 { 439 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 440 441 *(volatile uint32_t *)(h + o) = c->c_hwswap ? bswap32(val) : val; 442 } 443 444 inline void 445 au_wired_ws_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t val) 446 { 447 au_wired_cookie_t *c = (au_wired_cookie_t *)v; 448 449 *(volatile uint64_t *)(h + o) = c->c_hwswap ? bswap64(val) : val; 450 } 451 452 #define AU_WIRED_RM(TYPE,BYTES) \ 453 void \ 454 __CONCAT(au_wired_rm_,BYTES)(void *v, \ 455 bus_space_handle_t h, bus_size_t o, TYPE *dst, bus_size_t cnt) \ 456 { \ 457 \ 458 while (cnt-- > 0) \ 459 *dst ++ = __CONCAT(au_wired_r_,BYTES)(v, h, o); \ 460 } 461 AU_WIRED_RM(uint8_t,1) 462 AU_WIRED_RM(uint16_t,2) 463 AU_WIRED_RM(uint32_t,4) 464 AU_WIRED_RM(uint64_t,8) 465 466 #define AU_WIRED_RMS(TYPE,BYTES) \ 467 void \ 468 __CONCAT(au_wired_rms_,BYTES)(void *v, \ 469 bus_space_handle_t h, bus_size_t o, TYPE *dst, bus_size_t cnt) \ 470 { \ 471 \ 472 while (cnt-- > 0) { \ 473 wbflush(); \ 474 *dst++ = __CONCAT(au_wired_rs_,BYTES)(v, h, o); \ 475 } \ 476 } 477 AU_WIRED_RMS(uint16_t,2) 478 AU_WIRED_RMS(uint32_t,4) 479 AU_WIRED_RMS(uint64_t,8) 480 481 #define AU_WIRED_RR(TYPE,BYTES) \ 482 void \ 483 __CONCAT(au_wired_rr_,BYTES)(void *v, \ 484 bus_space_handle_t h, bus_size_t o, TYPE *dst, bus_size_t cnt) \ 485 { \ 486 \ 487 while (cnt-- > 0) { \ 488 *dst++ = __CONCAT(au_wired_r_,BYTES)(v, h, o); \ 489 o += BYTES; \ 490 } \ 491 } 492 AU_WIRED_RR(uint8_t,1) 493 AU_WIRED_RR(uint16_t,2) 494 AU_WIRED_RR(uint32_t,4) 495 AU_WIRED_RR(uint64_t,8) 496 497 #define AU_WIRED_RRS(TYPE,BYTES) \ 498 void \ 499 __CONCAT(au_wired_rrs_,BYTES)(void *v, \ 500 bus_space_handle_t h, bus_size_t o, TYPE *dst, bus_size_t cnt) \ 501 { \ 502 \ 503 while (cnt-- > 0) { \ 504 *dst++ = __CONCAT(au_wired_rs_,BYTES)(v, h, o); \ 505 o += BYTES; \ 506 } \ 507 } 508 AU_WIRED_RRS(uint16_t,2) 509 AU_WIRED_RRS(uint32_t,4) 510 AU_WIRED_RRS(uint64_t,8) 511 512 #define AU_WIRED_WM(TYPE,BYTES) \ 513 void \ 514 __CONCAT(au_wired_wm_,BYTES)(void *v, \ 515 bus_space_handle_t h, bus_size_t o, const TYPE *src, \ 516 bus_size_t cnt) \ 517 { \ 518 \ 519 while (cnt-- > 0) { \ 520 __CONCAT(au_wired_w_,BYTES)(v, h, o, *src++); \ 521 wbflush(); \ 522 } \ 523 } 524 AU_WIRED_WM(uint8_t,1) 525 AU_WIRED_WM(uint16_t,2) 526 AU_WIRED_WM(uint32_t,4) 527 AU_WIRED_WM(uint64_t,8) 528 529 #define AU_WIRED_WMS(TYPE,BYTES) \ 530 void \ 531 __CONCAT(au_wired_wms_,BYTES)(void *v, \ 532 bus_space_handle_t h, bus_size_t o, const TYPE *src, \ 533 bus_size_t cnt) \ 534 { \ 535 \ 536 while (cnt-- > 0) { \ 537 __CONCAT(au_wired_ws_,BYTES)(v, h, o, *src++); \ 538 wbflush(); \ 539 } \ 540 } 541 AU_WIRED_WMS(uint16_t,2) 542 AU_WIRED_WMS(uint32_t,4) 543 AU_WIRED_WMS(uint64_t,8) 544 545 #define AU_WIRED_WR(TYPE,BYTES) \ 546 void \ 547 __CONCAT(au_wired_wr_,BYTES)(void *v, \ 548 bus_space_handle_t h, bus_size_t o, const TYPE *src, \ 549 bus_size_t cnt) \ 550 { \ 551 \ 552 while (cnt-- > 0) { \ 553 __CONCAT(au_wired_w_,BYTES)(v, h, o, *src++); \ 554 o += BYTES; \ 555 } \ 556 } 557 AU_WIRED_WR(uint8_t,1) 558 AU_WIRED_WR(uint16_t,2) 559 AU_WIRED_WR(uint32_t,4) 560 AU_WIRED_WR(uint64_t,8) 561 562 #define AU_WIRED_WRS(TYPE,BYTES) \ 563 void \ 564 __CONCAT(au_wired_wrs_,BYTES)(void *v, \ 565 bus_space_handle_t h, bus_size_t o, const TYPE *src, \ 566 bus_size_t cnt) \ 567 { \ 568 \ 569 while (cnt-- > 0) { \ 570 __CONCAT(au_wired_ws_,BYTES)(v, h, o, *src++); \ 571 o += BYTES; \ 572 } \ 573 } 574 AU_WIRED_WRS(uint16_t,2) 575 AU_WIRED_WRS(uint32_t,4) 576 AU_WIRED_WRS(uint64_t,8) 577 578 #define AU_WIRED_SM(TYPE,BYTES) \ 579 void \ 580 __CONCAT(au_wired_sm_,BYTES)(void *v, \ 581 bus_space_handle_t h, bus_size_t o, TYPE val, \ 582 bus_size_t cnt) \ 583 { \ 584 \ 585 while (cnt-- > 0) { \ 586 __CONCAT(au_wired_w_,BYTES)(v, h, o, val); \ 587 wbflush(); \ 588 } \ 589 } 590 AU_WIRED_SM(uint8_t,1) 591 AU_WIRED_SM(uint16_t,2) 592 AU_WIRED_SM(uint32_t,4) 593 AU_WIRED_SM(uint64_t,8) 594 595 #define AU_WIRED_SR(TYPE,BYTES) \ 596 void \ 597 __CONCAT(au_wired_sr_,BYTES)(void *v, \ 598 bus_space_handle_t h, bus_size_t o, TYPE val, \ 599 bus_size_t cnt) \ 600 { \ 601 \ 602 while (cnt-- > 0) { \ 603 __CONCAT(au_wired_w_,BYTES)(v, h, o, val); \ 604 o += BYTES; \ 605 } \ 606 } 607 AU_WIRED_SR(uint8_t,1) 608 AU_WIRED_SR(uint16_t,2) 609 AU_WIRED_SR(uint32_t,4) 610 AU_WIRED_SR(uint64_t,8) 611 612 613 #define AU_WIRED_C(TYPE,BYTES) \ 614 void \ 615 __CONCAT(au_wired_c_,BYTES)(void *v, \ 616 bus_space_handle_t h1, bus_size_t o1, bus_space_handle_t h2, \ 617 bus_space_handle_t o2, bus_size_t cnt) \ 618 { \ 619 volatile TYPE *src, *dst; \ 620 src = (volatile TYPE *)(h1 + o1); \ 621 dst = (volatile TYPE *)(h2 + o2); \ 622 \ 623 if (src >= dst) { \ 624 while (cnt-- > 0) \ 625 *dst++ = *src++; \ 626 } else { \ 627 src += cnt - 1; \ 628 dst += cnt - 1; \ 629 while (cnt-- > 0) \ 630 *dst-- = *src--; \ 631 } \ 632 } 633 AU_WIRED_C(uint8_t,1) 634 AU_WIRED_C(uint16_t,2) 635 AU_WIRED_C(uint32_t,4) 636 AU_WIRED_C(uint64_t,8) 637 638 639 void 640 au_wired_space_init(bus_space_tag_t bst, const char *name, 641 paddr_t paddr, bus_addr_t start, bus_size_t size, int flags) 642 { 643 au_wired_cookie_t *c; 644 645 c = malloc(sizeof (struct au_wired_cookie), M_DEVBUF, 646 M_NOWAIT | M_ZERO); 647 648 c->c_pbase = paddr; 649 c->c_name = name; 650 c->c_start = start; 651 c->c_size = size; 652 c->c_pbase = paddr; 653 654 /* allocate extent manager */ 655 c->c_extent = extent_create(name, start, start + size, M_DEVBUF, 656 (caddr_t)c->c_exstore, sizeof (c->c_exstore), EX_NOWAIT); 657 if (c->c_extent == NULL) 658 panic("au_wired_space_init: %s: cannot create extent", name); 659 660 #if _BYTE_ORDER == _BIG_ENDIAN 661 if (flags & AU_WIRED_SPACE_LITTLE_ENDIAN) { 662 if (flags & AU_WIRED_SPACE_SWAP_HW) 663 c->c_hwswap = 1; 664 else 665 c->c_swswap = 1; 666 } 667 668 #elif _BYTE_ORDER == _LITTLE_ENDIAN 669 if (flags & AU_WIRED_SPACE_BIG_ENDIAN) { 670 if (flags & AU_WIRED_SPACE_SWAP_HW) 671 c->c_hwswap = 1; 672 else 673 c->c_swswap = 1; 674 } 675 #endif 676 677 bst->bs_cookie = c; 678 bst->bs_map = au_wired_map; 679 bst->bs_unmap = au_wired_unmap; 680 bst->bs_subregion = au_wired_subregion; 681 bst->bs_translate = NULL; /* we don't use these */ 682 bst->bs_get_window = NULL; /* we don't use these */ 683 bst->bs_alloc = au_wired_alloc; 684 bst->bs_free = au_wired_free; 685 bst->bs_vaddr = au_wired_vaddr; 686 bst->bs_mmap = au_wired_mmap; 687 bst->bs_barrier = au_wired_barrier; 688 bst->bs_r_1 = au_wired_r_1; 689 bst->bs_w_1 = au_wired_w_1; 690 bst->bs_r_2 = au_wired_r_2; 691 bst->bs_r_4 = au_wired_r_4; 692 bst->bs_r_8 = au_wired_r_8; 693 bst->bs_w_2 = au_wired_w_2; 694 bst->bs_w_4 = au_wired_w_4; 695 bst->bs_w_8 = au_wired_w_8; 696 bst->bs_rm_1 = au_wired_rm_1; 697 bst->bs_rm_2 = au_wired_rm_2; 698 bst->bs_rm_4 = au_wired_rm_4; 699 bst->bs_rm_8 = au_wired_rm_8; 700 bst->bs_rr_1 = au_wired_rr_1; 701 bst->bs_rr_2 = au_wired_rr_2; 702 bst->bs_rr_4 = au_wired_rr_4; 703 bst->bs_rr_8 = au_wired_rr_8; 704 bst->bs_wm_1 = au_wired_wm_1; 705 bst->bs_wm_2 = au_wired_wm_2; 706 bst->bs_wm_4 = au_wired_wm_4; 707 bst->bs_wm_8 = au_wired_wm_8; 708 bst->bs_wr_1 = au_wired_wr_1; 709 bst->bs_wr_2 = au_wired_wr_2; 710 bst->bs_wr_4 = au_wired_wr_4; 711 bst->bs_wr_8 = au_wired_wr_8; 712 bst->bs_sm_1 = au_wired_sm_1; 713 bst->bs_sm_2 = au_wired_sm_2; 714 bst->bs_sm_4 = au_wired_sm_4; 715 bst->bs_sm_8 = au_wired_sm_8; 716 bst->bs_sr_1 = au_wired_sr_1; 717 bst->bs_sr_2 = au_wired_sr_2; 718 bst->bs_sr_4 = au_wired_sr_4; 719 bst->bs_sr_8 = au_wired_sr_8; 720 bst->bs_c_1 = au_wired_c_1; 721 bst->bs_c_2 = au_wired_c_2; 722 bst->bs_c_4 = au_wired_c_4; 723 bst->bs_c_8 = au_wired_c_8; 724 725 bst->bs_rs_1 = au_wired_r_1; 726 bst->bs_rs_2 = au_wired_rs_2; 727 bst->bs_rs_4 = au_wired_rs_4; 728 bst->bs_rs_8 = au_wired_rs_8; 729 bst->bs_rms_1 = au_wired_rm_1; 730 bst->bs_rms_2 = au_wired_rms_2; 731 bst->bs_rms_4 = au_wired_rms_4; 732 bst->bs_rms_8 = au_wired_rms_8; 733 bst->bs_rrs_1 = au_wired_rr_1; 734 bst->bs_rrs_2 = au_wired_rrs_2; 735 bst->bs_rrs_4 = au_wired_rrs_4; 736 bst->bs_rrs_8 = au_wired_rrs_8; 737 bst->bs_ws_1 = au_wired_w_1; 738 bst->bs_ws_2 = au_wired_ws_2; 739 bst->bs_ws_4 = au_wired_ws_4; 740 bst->bs_ws_8 = au_wired_ws_8; 741 bst->bs_wms_1 = au_wired_wm_1; 742 bst->bs_wms_2 = au_wired_wms_2; 743 bst->bs_wms_4 = au_wired_wms_4; 744 bst->bs_wms_8 = au_wired_wms_8; 745 bst->bs_wrs_1 = au_wired_wr_1; 746 bst->bs_wrs_2 = au_wired_wrs_2; 747 bst->bs_wrs_4 = au_wired_wrs_4; 748 bst->bs_wrs_8 = au_wired_wrs_8; 749 } 750
Indexes created Mon Sep 29 03:10:08 GMT 2025