xref: /src/sys/arch/mips/alchemy/dev/augpio.c

/* $NetBSD: augpio.c,v 1.3 2006/02/18 23:21:06 gdamore Exp $ */

/*-
 * Copyright (c) 2006 Itronix Inc.
 * All rights reserved.
 *
 * Written by Garrett D'Amore for Itronix Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of Itronix Inc. may not be used to endorse
 *    or promote products derived from this software without specific
 *    prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: augpio.c,v 1.3 2006/02/18 23:21:06 gdamore Exp $");

#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/errno.h>
#include <sys/device.h>
#include <sys/gpio.h>
#include <sys/kernel.h>

#include <dev/gpio/gpiovar.h>

#include <machine/bus.h>
#include <machine/cpu.h>

#include <mips/alchemy/include/aubusvar.h>
#include <mips/alchemy/include/aureg.h>
#include <mips/alchemy/dev/augpioreg.h>

struct augpio_softc {
	struct device			sc_dev;
	struct gpio_chipset_tag		sc_gc;
	gpio_pin_t			sc_pins[AUGPIO_NPINS];
	int				sc_npins;
	bus_space_tag_t			sc_bst;
	bus_space_handle_t		sc_bsh;
	int				sc_caps;
	const char 			*sc_name;
	int				(*sc_getctl)(void *, int);
};

static int augpio_read(void *, int);
static void augpio_write(void *, int, int);
static void augpio_ctl(void *, int, int);
static int augpio_getctl(void *, int);

static int augpio2_read(void *, int);
static void augpio2_write(void *, int, int);
static void augpio2_ctl(void *, int, int);
static int augpio2_getctl(void *, int);

static int augpio_match(struct device *, struct cfdata *, void *);
static void augpio_attach(struct device *, struct device *, void *);

CFATTACH_DECL(augpio, sizeof(struct augpio_softc),
    augpio_match, augpio_attach, NULL, NULL);

#define	GETREG(x)	\
	(*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x))
#define	PUTREG(x, v)	\
	((*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))

static int augpio_found = 0;

int
augpio_match(struct device *parent, struct cfdata *match, void *aux)
{
	struct aubus_attach_args *aa = (struct aubus_attach_args *)aux;

	if (strcmp(aa->aa_name, "augpio") != 0)
		return 0;

	if (augpio_found)
		return 0;

	return 1;
}

void
augpio_attach(struct device *parent, struct device *self, void *aux)
{
	int	pin;

	struct augpio_softc *sc = (struct augpio_softc *)self;
	struct aubus_attach_args *aa = aux;
	struct gpiobus_attach_args gba;

	sc->sc_bst = aa->aa_st;
	sc->sc_npins = aa->aa_addrs[1];
	sc->sc_gc.gp_cookie = sc;

	if (aa->aa_addrs[0] == GPIO_BASE) {

		if (bus_space_map(sc->sc_bst, aa->aa_addrs[0],
			AUGPIO_SIZE, 0, &sc->sc_bsh) != 0) {
			printf(": cannot map registers!\n");
			return;
		}
		sc->sc_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
		    GPIO_PIN_TRISTATE;
		sc->sc_gc.gp_pin_read = augpio_read;
		sc->sc_gc.gp_pin_write = augpio_write;
		sc->sc_gc.gp_pin_ctl = augpio_ctl;
		sc->sc_getctl = augpio_getctl;
		sc->sc_name = "primary block";

	} else if (aa->aa_addrs[0] == GPIO2_BASE) {
		/*
		 * We rely on firmware (or platform init code) to initialize
		 * the GPIO2 block.  We can't do it ourselves, because
		 * resetting the GPIO2 block can have nasty effects (e.g.
		 * reset PCI bus...)
		 */
		if (bus_space_map(sc->sc_bst, aa->aa_addrs[0],
			AUGPIO2_SIZE, 0, &sc->sc_bsh) != 0) {
			printf(": cannot map registers!\n");
			return;
		}
		sc->sc_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
		sc->sc_gc.gp_pin_read = augpio2_read;
		sc->sc_gc.gp_pin_write = augpio2_write;
		sc->sc_gc.gp_pin_ctl = augpio2_ctl;
		sc->sc_getctl = augpio2_getctl;
		sc->sc_name = "secondary block";

	} else {
		printf(": unidentified block\n");
		return;
	}

	for (pin = 0; pin < sc->sc_npins; pin++) {
		gpio_pin_t	*pp = &sc->sc_pins[pin];

		pp->pin_num = pin;
		pp->pin_caps = sc->sc_caps;
		pp->pin_flags = sc->sc_getctl(sc, pin);
		pp->pin_state = sc->sc_gc.gp_pin_read(sc, pin);
	}

	gba.gba_gc = &sc->sc_gc;
	gba.gba_pins = sc->sc_pins;
	gba.gba_npins = sc->sc_npins;

	printf(": Alchemy GPIO, %s\n", sc->sc_name);
	config_found_ia(&sc->sc_dev, "gpiobus", &gba, gpiobus_print);
}

int
augpio_read(void *arg, int pin)
{
	struct augpio_softc	*sc = arg;

	pin = 1 << pin;

	if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, AUGPIO_PINSTATERD) & pin)
		return GPIO_PIN_HIGH;
	else
		return GPIO_PIN_LOW;
}

void
augpio_write(void *arg, int pin, int value)
{
	struct augpio_softc	*sc = arg;

	pin = 1 << pin;
	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
	    value ? AUGPIO_OUTPUTSET : AUGPIO_OUTPUTCLR, pin);
}

void
augpio_ctl(void *arg, int pin, int flags)
{
	struct augpio_softc	*sc = arg;
	bus_addr_t		reg;

	pin = 1 << pin;

	if (flags & (GPIO_PIN_TRISTATE|GPIO_PIN_INPUT)) {
		reg = AUGPIO_TRIOUTCLR;
	} else if (flags & GPIO_PIN_OUTPUT) {
		uint32_t		out;
		out = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AUGPIO_OUTPUTRD);
		reg = pin & out ? AUGPIO_OUTPUTSET : AUGPIO_OUTPUTCLR;
	} else {
		return;
	}

	bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, pin);
}

int
augpio_getctl(void *arg, int pin)
{
	struct augpio_softc	*sc = arg;

	if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, AUGPIO_TRIOUTRD) & pin)
		return GPIO_PIN_OUTPUT;
	else
		return GPIO_PIN_INPUT;
}

int
augpio2_read(void *arg, int pin)
{
	struct augpio_softc	*sc = arg;

	pin = 1 << pin;

	if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, AUGPIO2_PINSTATE) & pin)
		return GPIO_PIN_HIGH;
	else
		return GPIO_PIN_LOW;
}

void
augpio2_write(void *arg, int pin, int value)
{
	struct augpio_softc	*sc = arg;

	pin = 1 << pin;

	if (value) {
		pin = pin | (pin << 16);
	} else {
		pin = (pin << 16);
	}

	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AUGPIO2_OUTPUT, pin);
}

void
augpio2_ctl(void *arg, int pin, int flags)
{
	struct augpio_softc	*sc = arg;
	uint32_t		dir;

	pin = 1 << pin;

	dir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AUGPIO2_DIR);

	if (flags & GPIO_PIN_INPUT) {
		dir |= pin;
	} else if (flags & GPIO_PIN_OUTPUT) {
		dir &= ~pin;
	}
	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AUGPIO2_DIR, dir);
}

int
augpio2_getctl(void *arg, int pin)
{
	struct augpio_softc	*sc = arg;
	uint32_t		dir;

	pin = 1 << pin;

	dir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AUGPIO2_DIR);
	if (dir & (uint32_t)pin) {
		return GPIO_PIN_OUTPUT;
	} else {
		return GPIO_PIN_INPUT;
	}
}