aupcivar.h revision 1.2.16.2
1 1.2.16.2 yamt /* $NetBSD: aupcivar.h,v 1.2.16.2 2006/06/21 14:53:28 yamt Exp $ */ 2 1.2.16.2 yamt 3 1.2.16.2 yamt /*- 4 1.2.16.2 yamt * Copyright (c) 2006 Itronix Inc. 5 1.2.16.2 yamt * All rights reserved. 6 1.2.16.2 yamt * 7 1.2.16.2 yamt * Written by Garrett D'Amore for Itronix Inc. 8 1.2.16.2 yamt * 9 1.2.16.2 yamt * Redistribution and use in source and binary forms, with or without 10 1.2.16.2 yamt * modification, are permitted provided that the following conditions 11 1.2.16.2 yamt * are met: 12 1.2.16.2 yamt * 1. Redistributions of source code must retain the above copyright 13 1.2.16.2 yamt * notice, this list of conditions and the following disclaimer. 14 1.2.16.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.16.2 yamt * notice, this list of conditions and the following disclaimer in the 16 1.2.16.2 yamt * documentation and/or other materials provided with the distribution. 17 1.2.16.2 yamt * 3. The name of Itronix Inc. may not be used to endorse 18 1.2.16.2 yamt * or promote products derived from this software without specific 19 1.2.16.2 yamt * prior written permission. 20 1.2.16.2 yamt * 21 1.2.16.2 yamt * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 1.2.16.2 yamt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 1.2.16.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 1.2.16.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 1.2.16.2 yamt * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 1.2.16.2 yamt * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 1.2.16.2 yamt * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 1.2.16.2 yamt * ON ANY THEORY OF LIABILITY, WHETHER IN 29 1.2.16.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 1.2.16.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 1.2.16.2 yamt * POSSIBILITY OF SUCH DAMAGE. 32 1.2.16.2 yamt */ 33 1.2.16.2 yamt 34 1.2.16.2 yamt #ifndef _MIPS_ALCHEMY_DEV_AUPCIVAR_H 35 1.2.16.2 yamt #define _MIPS_ALCHEMY_DEV_AUPCIVAR_H 36 1.2.16.2 yamt 37 1.2.16.2 yamt #include <dev/pci/pcivar.h> 38 1.2.16.2 yamt 39 1.2.16.2 yamt /* 40 1.2.16.2 yamt * PCI configuration space encompasses all 32-bits. 41 1.2.16.2 yamt * 42 1.2.16.2 yamt * PCI memory space encompasses all 32-bits, excepting that portion of 43 1.2.16.2 yamt * the address space that is decoded by the Alchemy core for accesses 44 1.2.16.2 yamt * to host memory. (That range is determined dynamically.) 45 1.2.16.2 yamt * 46 1.2.16.2 yamt * PCI I/O address range. We want to start offset from zero to avoid 47 1.2.16.2 yamt * potential problems with devices. These addresses do not 48 1.2.16.2 yamt * participate on the Alchemy system bus, hence we can choose any 49 1.2.16.2 yamt * range we like. 16 MB is plenty. 50 1.2.16.2 yamt */ 51 1.2.16.2 yamt 52 1.2.16.2 yamt #define AUPCI_IO_START 0x1000000 53 1.2.16.2 yamt #define AUPCI_IO_END 0x1FFFFFF 54 1.2.16.2 yamt 55 1.2.16.2 yamt 56 1.2.16.2 yamt /* 57 1.2.16.2 yamt * Machdep code must implement this. Stores an IRQ number in 58 1.2.16.2 yamt * pci_intr_handle_t. See pci_intr_map(9) for more detail. Returns 0 59 1.2.16.2 yamt * on success, non-zero on failure. 60 1.2.16.2 yamt */ 61 1.2.16.2 yamt int aupci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 62 1.2.16.2 yamt 63 1.2.16.2 yamt #endif /* _MIPS_ALCHEMY_DEV_AUPCIVAR_H */ 64
Indexes created Sun Oct 19 02:09:48 GMT 2025