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aupcmciavar.h revision 1.1 
      1 /* $NetBSD: aupcmciavar.h,v 1.1 2006/02/23 03:49:28 gdamore Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2006 Itronix Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Garrett D'Amore for Itronix Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. The name of Itronix Inc. may not be used to endorse
     18  *    or promote products derived from this software without specific
     19  *    prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
     22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
     25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     28  * ON ANY THEORY OF LIABILITY, WHETHER IN
     29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31  * POSSIBILITY OF SUCH DAMAGE.
     32  */
     33 
     34 #ifndef _MIPS_ALCHEMY_DEV_AUPCMCIAVAR_H
     35 #define	_MIPS_ALCHEMY_DEV_AUPCMCIAVAR_H
     36 
     37 #define	AUPCMCIA_NWINS	16
     38 #define	AUPCMCIA_NSLOTS	2	/* current boards only have two slots */
     39 
     40 #define	AUPCMCIA_IRQ_CARD	0
     41 #define	AUPCMCIA_IRQ_INSERT	1
     42 #define	AUPCMCIA_MAP_SIZE	16 * 1024 * 1024	/* arbitrary */
     43 
     44 struct aupcmcia_machdep {
     45 	int		am_nslots;
     46 	bus_size_t	(*am_slot_offset)(int);
     47 	int		(*am_slot_irq)(int, int);
     48 	void		(*am_slot_enable)(int);
     49 	void		(*am_slot_disable)(int);
     50 	int		(*am_slot_status)(int);
     51 	const char *	(*am_slot_name)(int);
     52 };
     53 
     54 /*
     55  * Machdep code must implement this to supply its slot implementation
     56  * details to the framework.  The address
     57  */
     58 struct aupcmcia_machdep *aupcmcia_machdep(void);
     59 
     60 #endif	/* _MIPS_ALCHEMY_DEV_AUPCIVAR_H */
     61