aupscreg.h revision 1.2.12.3
1 1.2.12.3 yamt /* $NetBSD: aupscreg.h,v 1.2.12.3 2006/12/30 20:46:30 yamt Exp $ */ 2 1.2.12.2 yamt 3 1.2.12.2 yamt /*- 4 1.2.12.2 yamt * Copyright (c) 2006 Shigeyuki Fukushima. 5 1.2.12.2 yamt * All rights reserved. 6 1.2.12.2 yamt * 7 1.2.12.2 yamt * Written by Shigeyuki Fukushima. 8 1.2.12.2 yamt * 9 1.2.12.2 yamt * Redistribution and use in source and binary forms, with or without 10 1.2.12.2 yamt * modification, are permitted provided that the following conditions 11 1.2.12.2 yamt * are met: 12 1.2.12.2 yamt * 1. Redistributions of source code must retain the above copyright 13 1.2.12.2 yamt * notice, this list of conditions and the following disclaimer. 14 1.2.12.2 yamt * 2. Redistributions in binary form must reproduce the above 15 1.2.12.2 yamt * copyright notice, this list of conditions and the following 16 1.2.12.2 yamt * disclaimer in the documentation and/or other materials provided 17 1.2.12.2 yamt * with the distribution. 18 1.2.12.2 yamt * 3. The name of the author may not be used to endorse or promote 19 1.2.12.2 yamt * products derived from this software without specific prior 20 1.2.12.2 yamt * written permission. 21 1.2.12.2 yamt * 22 1.2.12.2 yamt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 1.2.12.2 yamt * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 1.2.12.2 yamt * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 1.2.12.2 yamt * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 1.2.12.2 yamt * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 1.2.12.2 yamt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 1.2.12.2 yamt * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 1.2.12.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 1.2.12.2 yamt * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 1.2.12.2 yamt * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 1.2.12.2 yamt * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 1.2.12.2 yamt */ 34 1.2.12.2 yamt 35 1.2.12.2 yamt #ifndef _MIPS_ALCHEMY_DEV_AUPSCREG_H_ 36 1.2.12.2 yamt #define _MIPS_ALCHEMY_DEV_AUPSCREG_H_ 37 1.2.12.2 yamt 38 1.2.12.2 yamt /* 39 1.2.12.2 yamt * PSC registers (offset from PSCn_BASE). 40 1.2.12.2 yamt */ 41 1.2.12.2 yamt 42 1.2.12.2 yamt /* psc_sel: PSC clock and protocol select 43 1.2.12.2 yamt * CLK [5:4] 44 1.2.12.2 yamt * 00 = pscn_intclk (for SPI, SMBus, I2S Master[PSC3 Only]) 45 1.2.12.2 yamt * 01 = PSCn_EXTCLK (for SPI, SMBus, I2S Master) 46 1.2.12.2 yamt * 10 = PSCn_CLK (for AC97, I2S Slave) 47 1.2.12.2 yamt * 11 = Reserved 48 1.2.12.2 yamt * PS [2:0] 49 1.2.12.2 yamt * 000 = Protocol disable 50 1.2.12.2 yamt * 001 = Reserved 51 1.2.12.2 yamt * 010 = SPI mode 52 1.2.12.2 yamt * 011 = I2S mode 53 1.2.12.2 yamt * 100 = AC97 mode 54 1.2.12.2 yamt * 101 = SMBus mode 55 1.2.12.2 yamt * 11x = Reserved 56 1.2.12.2 yamt */ 57 1.2.12.2 yamt #define AUPSC_SEL 0x00 /* R/W */ 58 1.2.12.2 yamt # define AUPSC_SEL_CLK(x) ((x & 0x03) << 4) /* CLK */ 59 1.2.12.2 yamt # define AUPSC_SEL_PS(x) (x & 0x07) 60 1.2.12.2 yamt # define AUPSC_SEL_DISABLE 0 61 1.2.12.2 yamt # define AUPSC_SEL_SPI 2 62 1.2.12.2 yamt # define AUPSC_SEL_I2S 3 63 1.2.12.2 yamt # define AUPSC_SEL_AC97 4 64 1.2.12.2 yamt # define AUPSC_SEL_SMBUS 5 65 1.2.12.2 yamt 66 1.2.12.2 yamt /* psc_ctrl: PSC control 67 1.2.12.2 yamt * ENA [1:0] 68 1.2.12.2 yamt * 00 = Disable/Reset 69 1.2.12.2 yamt * 01 = Reserved 70 1.2.12.2 yamt * 10 = Suspend 71 1.2.12.2 yamt * 11 = Enable 72 1.2.12.2 yamt */ 73 1.2.12.2 yamt #define AUPSC_CTRL 0x04 /* R/W */ 74 1.2.12.2 yamt # define AUPSC_CTRL_ENA(x) (x & 0x03) 75 1.2.12.2 yamt # define AUPSC_CTRL_DISABLE 0 76 1.2.12.2 yamt # define AUPSC_CTRL_SUSPEND 2 77 1.2.12.2 yamt # define AUPSC_CTRL_ENABLE 3 78 1.2.12.2 yamt 79 1.2.12.2 yamt /* 0x0008 - 0x002F: Protocol-specific registers */ 80 1.2.12.2 yamt 81 1.2.12.3 yamt /* psc_stat: PSC status 82 1.2.12.3 yamt * DI [1] 83 1.2.12.3 yamt * 1 = Device interrupt 84 1.2.12.3 yamt * DR [1] 85 1.2.12.3 yamt * 1 = Device ready 86 1.2.12.3 yamt * SR [0] 87 1.2.12.3 yamt * 1 = PSC ready 88 1.2.12.3 yamt * all other bits a are protocol specific 89 1.2.12.3 yamt */ 90 1.2.12.3 yamt #define AUPSC_STAT 0x14 91 1.2.12.3 yamt # define AUPSC_STAT_SR 1 92 1.2.12.3 yamt # define AUPSC_STAT_DR 2 93 1.2.12.3 yamt # define AUPSC_STAT_DI 4 94 1.2.12.2 yamt /* PSC registers size */ 95 1.2.12.2 yamt #define AUPSC_SIZE 0x2f 96 1.2.12.2 yamt 97 1.2.12.2 yamt 98 1.2.12.2 yamt /* 99 1.2.12.2 yamt * SPI Protocol registers 100 1.2.12.2 yamt */ 101 1.2.12.2 yamt #define AUPSC_SPICFG 0x08 /* R/W */ 102 1.2.12.2 yamt #define AUPSC_SPIMSK 0x0c /* R/W */ 103 1.2.12.2 yamt #define AUPSC_SPIPCR 0x10 /* R/W */ 104 1.2.12.2 yamt #define AUPSC_SPISTAT 0x14 /* Read only */ 105 1.2.12.2 yamt #define AUPSC_SPIEVNT 0x18 /* R/W */ 106 1.2.12.2 yamt #define AUPSC_SPITXRX 0x1c /* R/W */ 107 1.2.12.2 yamt 108 1.2.12.2 yamt /* 109 1.2.12.2 yamt * I2S Protocol registers 110 1.2.12.2 yamt */ 111 1.2.12.2 yamt #define AUPSC_I2SCFG 0x08 /* R/W */ 112 1.2.12.2 yamt #define AUPSC_I2SMSK 0x0c /* R/W */ 113 1.2.12.2 yamt #define AUPSC_I2SPCR 0x10 /* R/W */ 114 1.2.12.2 yamt #define AUPSC_I2SSTAT 0x14 /* Read only */ 115 1.2.12.2 yamt #define AUPSC_I2SEVNT 0x18 /* R/W */ 116 1.2.12.2 yamt #define AUPSC_I2STXRX 0x1c /* R/W */ 117 1.2.12.2 yamt #define AUPSC_I2SUDF 0x20 /* R/W */ 118 1.2.12.2 yamt 119 1.2.12.2 yamt /* 120 1.2.12.2 yamt * AC97 Protocol registers 121 1.2.12.2 yamt */ 122 1.2.12.2 yamt #define AUPSC_AC97CFG 0x08 /* R/W */ 123 1.2.12.2 yamt #define AUPSC_AC97MSK 0x0c /* R/W */ 124 1.2.12.2 yamt #define AUPSC_AC97PCR 0x10 /* R/W */ 125 1.2.12.2 yamt #define AUPSC_AC97STAT 0x14 /* Read only */ 126 1.2.12.2 yamt #define AUPSC_AC97EVNT 0x18 /* R/W */ 127 1.2.12.2 yamt #define AUPSC_AC97TXRX 0x1c /* R/W */ 128 1.2.12.2 yamt #define AUPSC_AC97CDC 0x20 /* R/W */ 129 1.2.12.2 yamt #define AUPSC_AC97RST 0x24 /* R/W */ 130 1.2.12.2 yamt #define AUPSC_AC97GPO 0x28 /* R/W */ 131 1.2.12.2 yamt #define AUPSC_AC97GPI 0x2c /* Read only */ 132 1.2.12.2 yamt 133 1.2.12.2 yamt /* 134 1.2.12.2 yamt * SMBus Protocol registers 135 1.2.12.2 yamt */ 136 1.2.12.2 yamt #define AUPSC_SMBCFG 0x08 /* R/W */ 137 1.2.12.2 yamt #define AUPSC_SMBMSK 0x0c /* R/W */ 138 1.2.12.2 yamt #define AUPSC_SMBPCR 0x10 /* R/W */ 139 1.2.12.2 yamt #define AUPSC_SMBSTAT 0x14 /* Read only */ 140 1.2.12.2 yamt #define AUPSC_SMBEVNT 0x18 /* R/W */ 141 1.2.12.2 yamt #define AUPSC_SMBTXRX 0x1c /* R/W */ 142 1.2.12.2 yamt #define AUPSC_SMBTMR 0x20 /* R/W */ 143 1.2.12.2 yamt 144 1.2.12.2 yamt #endif /* _MIPS_ALCHEMY_DEV_AUPSCREG_H_ */ 145
Indexes created Mon Oct 20 20:10:13 GMT 2025