ausmbus_psc.c revision 1.1
1 /* $NetBSD: ausmbus_psc.c,v 1.1 2006/03/06 17:16:45 shige Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer in the documentation and/or other materials provided 17 * with the distribution. 18 * 3. The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ausmbus_psc.c,v 1.1 2006/03/06 17:16:45 shige Exp $"); 37 38 #include "locators.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/errno.h> 44 45 #include <machine/bus.h> 46 #include <machine/cpu.h> 47 48 #include <mips/alchemy/dev/aupscreg.h> 49 #include <mips/alchemy/dev/aupscvar.h> 50 #include <mips/alchemy/dev/smbusreg.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/i2c_bitbang.h> 54 55 struct ausmbus_softc { 56 struct device sc_dev; 57 58 /* protocol comoon fields */ 59 struct aupsc_controller sc_ctrl; 60 61 /* protocol specific fields */ 62 struct i2c_controller sc_i2c; 63 i2c_addr_t sc_smbus_slave_addr; 64 int sc_smbus_timeout; 65 }; 66 67 #define ausmbus_reg_read(sc, reg) \ 68 bus_space_read_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg) 69 #define ausmbus_reg_write(sc, reg, val) \ 70 bus_space_write_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg, val) 71 72 static int ausmbus_match(struct device *, struct cfdata *, void *); 73 static void ausmbus_attach(struct device *, struct device *, void *); 74 75 CFATTACH_DECL(ausmbus, sizeof(struct ausmbus_softc), 76 ausmbus_match, ausmbus_attach, NULL, NULL); 77 78 /* fuctions for i2c_controller */ 79 static int ausmbus_acquire_bus(void *, int); 80 static void ausmbus_release_bus(void *, int); 81 static int ausmbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 82 const void *cmd, size_t cmdlen, void *vbuf, 83 size_t buflen, int flags); 84 85 /* subroutine functions for i2c_controller */ 86 static int ausmbus_receive_1(struct ausmbus_softc *, uint8_t *); 87 static int ausmbus_read_1(struct ausmbus_softc *, uint8_t, uint8_t *); 88 static int ausmbus_send_1(struct ausmbus_softc *, uint8_t); 89 static int ausmbus_write_1(struct ausmbus_softc *, uint8_t, uint8_t); 90 static int ausmbus_wait_mastertx(struct ausmbus_softc *sc); 91 static int ausmbus_wait_masterrx(struct ausmbus_softc *sc); 92 static int ausmbus_initiate_xfer(void *, i2c_addr_t, int); 93 static int ausmbus_read_byte(void *arg, uint8_t *vp, int flags); 94 static int ausmbus_write_byte(void *arg, uint8_t v, int flags); 95 96 97 static int 98 ausmbus_match(struct device *parent, struct cfdata *cf, void *aux) 99 { 100 struct aupsc_attach_args *aa = (struct aupsc_attach_args *)aux; 101 102 if (strcmp(aa->aupsc_name, cf->cf_name) != 0) 103 return 0; 104 105 return 1; 106 } 107 108 static void 109 ausmbus_attach(struct device *parent, struct device *self, void *aux) 110 { 111 struct ausmbus_softc *sc = (struct ausmbus_softc *)self; 112 struct aupsc_attach_args *aa = (struct aupsc_attach_args *)aux; 113 struct i2cbus_attach_args iba; 114 115 aprint_normal(": Alchemy PSC SMBus protocol\n"); 116 117 /* Initialize PSC */ 118 sc->sc_ctrl = aa->aupsc_ctrl; 119 120 /* Initialize i2c_controller for SMBus */ 121 sc->sc_i2c.ic_cookie = sc; 122 sc->sc_i2c.ic_acquire_bus = ausmbus_acquire_bus; 123 sc->sc_i2c.ic_release_bus = ausmbus_release_bus; 124 sc->sc_i2c.ic_send_start = NULL; 125 sc->sc_i2c.ic_send_stop = NULL; 126 sc->sc_i2c.ic_initiate_xfer = NULL; 127 sc->sc_i2c.ic_read_byte = NULL; 128 sc->sc_i2c.ic_write_byte = NULL; 129 sc->sc_i2c.ic_exec = ausmbus_exec; 130 sc->sc_smbus_timeout = 10; 131 132 { 133 uint8_t cmd[1]; 134 uint8_t vbuf[1]; 135 136 #if 1 137 ausmbus_acquire_bus(sc, 0); 138 cmd[0] = 0x50; 139 vbuf[0] = 0x86; 140 ausmbus_exec(sc, I2C_OP_WRITE_WITH_STOP, 0x33, cmd,1, vbuf,1, 0); 141 ausmbus_release_bus(sc, 0); 142 #endif 143 144 ausmbus_acquire_bus(sc, 0); 145 cmd[0] = 0x50; 146 vbuf[0] = 0x0; 147 ausmbus_exec(sc, I2C_OP_READ_WITH_STOP, 0x32, cmd,1, &vbuf[0],1, 0); 148 printf("iic_exec: vbuf[0]=0x%x\n", vbuf[0]); 149 ausmbus_release_bus(sc, 0); 150 151 } 152 153 iba.iba_name = "iic"; 154 iba.iba_tag = &sc->sc_i2c; 155 (void) config_found(&sc->sc_dev, &iba, iicbus_print); 156 } 157 158 static int 159 ausmbus_acquire_bus(void *arg, int flags) 160 { 161 struct ausmbus_softc *sc = arg; 162 uint32_t v; 163 164 /* Select SMBus Protocol & Enable PSC */ 165 sc->sc_ctrl.psc_enable(sc, AUPSC_SEL_SMBUS); 166 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 167 if ((v & SMBUS_STAT_SR) == 0) { 168 /* PSC is not ready */ 169 return -1; 170 } 171 172 /* Setup SMBus Configuration register */ 173 v = SMBUS_CFG_DD; /* Disable DMA */ 174 v |= SMBUS_CFG_RT_SET(SMBUS_CFG_RT_FIFO8); /* Rx FIFO 8data */ 175 v |= SMBUS_CFG_TT_SET(SMBUS_CFG_TT_FIFO8); /* Tx FIFO 8data */ 176 v |= SMBUS_CFG_DIV_SET(SMBUS_CFG_DIV8); /* pscn_mainclk/8 */ 177 v &= ~SMBUS_CFG_SFM; /* Standard Mode */ 178 ausmbus_reg_write(sc, AUPSC_SMBCFG, v); 179 180 /* Setup SMBus Protocol Timing register */ 181 v = SMBUS_TMR_TH_SET(SMBUS_TMR_STD_TH) 182 | SMBUS_TMR_PS_SET(SMBUS_TMR_STD_PS) 183 | SMBUS_TMR_PU_SET(SMBUS_TMR_STD_PU) 184 | SMBUS_TMR_SH_SET(SMBUS_TMR_STD_SH) 185 | SMBUS_TMR_SU_SET(SMBUS_TMR_STD_SU) 186 | SMBUS_TMR_CL_SET(SMBUS_TMR_STD_CL) 187 | SMBUS_TMR_CH_SET(SMBUS_TMR_STD_CH); 188 ausmbus_reg_write(sc, AUPSC_SMBTMR, v); 189 190 /* Setup SMBus Mask register */ 191 v = SMBUS_MSK_ALLMASK; 192 ausmbus_reg_write(sc, AUPSC_SMBMSK, v); 193 194 /* SMBus Enable */ 195 v = ausmbus_reg_read(sc, AUPSC_SMBCFG); 196 v |= SMBUS_CFG_DE; 197 ausmbus_reg_write(sc, AUPSC_SMBCFG, v); 198 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 199 if ((v & SMBUS_STAT_SR) == 0) { 200 /* SMBus is not ready */ 201 return -1; 202 } 203 204 #ifdef AUSMBUS_PSC_DEBUG 205 aprint_normal("AuSMBus enabled.\n"); 206 aprint_normal("AuSMBus smbconfig: 0x%08x\n", 207 ausmbus_reg_read(sc, AUPSC_SMBCFG)); 208 aprint_normal("AuSMBus smbstatus: 0x%08x\n", 209 ausmbus_reg_read(sc, AUPSC_SMBSTAT)); 210 aprint_normal("AuSMBus smbtmr : 0x%08x\n", 211 ausmbus_reg_read(sc, AUPSC_SMBTMR)); 212 aprint_normal("AuSMBus smbmask : 0x%08x\n", 213 ausmbus_reg_read(sc, AUPSC_SMBMSK)); 214 #endif 215 216 return 0; 217 } 218 219 static void 220 ausmbus_release_bus(void *arg, int flags) 221 { 222 struct ausmbus_softc *sc = arg; 223 224 ausmbus_reg_write(sc, AUPSC_SMBCFG, 0); 225 sc->sc_ctrl.psc_disable(sc); 226 227 return; 228 } 229 230 static int 231 ausmbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd, 232 size_t cmdlen, void *vbuf, size_t buflen, int flags) 233 { 234 struct ausmbus_softc *sc = (struct ausmbus_softc *)cookie; 235 const uint8_t *cmd = vcmd; 236 uint8_t *buf = vbuf; 237 238 sc->sc_smbus_slave_addr = addr; 239 240 /* Receive byte */ 241 if ((I2C_OP_READ_P(op)) && (cmdlen == 0) && (buflen == 1)) { 242 return ausmbus_receive_1(sc, buf); 243 } 244 245 /* Read byte */ 246 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 247 return ausmbus_read_1(sc, *cmd, buf); 248 } 249 250 /* Send byte */ 251 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 252 return ausmbus_send_1(sc, *buf); 253 } 254 255 /* Write byte */ 256 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 257 return ausmbus_write_1(sc, *cmd, *buf); 258 } 259 260 /* 261 * XXX: TODO Please Support other protocols defined in SMBus 2.0 262 * - Quick Command 263 * - Write word 264 * - Read word 265 * - Process call 266 * - Block write/read 267 * - Clock write-block read process cal 268 * - SMBus host notify protocol 269 */ 270 271 return -1; 272 } 273 274 static int 275 ausmbus_receive_1(struct ausmbus_softc *sc, uint8_t *vp) 276 { 277 int error; 278 279 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 280 if (error != 0) { 281 return error; 282 } 283 error = ausmbus_read_byte(sc, vp, I2C_F_STOP); 284 if (error != 0) { 285 return error; 286 } 287 288 return 0; 289 } 290 291 static int 292 ausmbus_read_1(struct ausmbus_softc *sc, uint8_t cmd, uint8_t *vp) 293 { 294 int error; 295 296 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 297 if (error != 0) { 298 return error; 299 } 300 301 error = ausmbus_write_byte(sc, cmd, I2C_F_READ); 302 if (error != 0) { 303 return error; 304 } 305 306 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 307 if (error != 0) { 308 return error; 309 } 310 311 error = ausmbus_read_byte(sc, vp, I2C_F_STOP); 312 if (error != 0) { 313 return error; 314 } 315 316 return 0; 317 } 318 319 static int 320 ausmbus_send_1(struct ausmbus_softc *sc, uint8_t val) 321 { 322 int error; 323 324 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 325 if (error != 0) { 326 return error; 327 } 328 329 error = ausmbus_write_byte(sc, val, I2C_F_STOP); 330 if (error != 0) { 331 return error; 332 } 333 334 return 0; 335 } 336 337 static int 338 ausmbus_write_1(struct ausmbus_softc *sc, uint8_t cmd, uint8_t val) 339 { 340 int error; 341 342 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 343 if (error != 0) { 344 return error; 345 } 346 347 error = ausmbus_write_byte(sc, cmd, 0); 348 if (error != 0) { 349 return error; 350 } 351 352 error = ausmbus_write_byte(sc, val, I2C_F_STOP); 353 if (error != 0) { 354 return error; 355 } 356 357 return 0; 358 } 359 360 static int 361 ausmbus_wait_mastertx(struct ausmbus_softc *sc) 362 { 363 uint32_t v; 364 int timeout; 365 int txerr = 0; 366 367 timeout = sc->sc_smbus_timeout; 368 369 do { 370 v = ausmbus_reg_read(sc, AUPSC_SMBEVNT); 371 #ifdef AUSMBUS_PSC_DEBUG 372 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): psc_smbevnt=0x%08x\n", v); 373 #endif 374 if ((v & SMBUS_EVNT_TU) != 0) 375 break; 376 if ((v & SMBUS_EVNT_MD) != 0) 377 break; 378 if ((v & (SMBUS_EVNT_DN | SMBUS_EVNT_AN | SMBUS_EVNT_AL)) 379 != 0) { 380 txerr = 1; 381 break; 382 } 383 timeout--; 384 delay(1); 385 } while (timeout > 0); 386 387 if (txerr != 0) { 388 ausmbus_reg_write(sc, AUPSC_SMBEVNT, 389 SMBUS_EVNT_DN | SMBUS_EVNT_AN | SMBUS_EVNT_AL); 390 #ifdef AUSMBUS_PSC_DEBUG 391 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): Tx error\n"); 392 #endif 393 return -1; 394 } 395 396 /* Reset Event TU (Tx Underflow) */ 397 ausmbus_reg_write(sc, AUPSC_SMBEVNT, SMBUS_EVNT_TU | SMBUS_EVNT_MD); 398 399 #ifdef AUSMBUS_PSC_DEBUG 400 v = ausmbus_reg_read(sc, AUPSC_SMBEVNT); 401 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): psc_smbevnt=0x%08x (reset)\n", v); 402 #endif 403 return 0; 404 } 405 406 static int 407 ausmbus_wait_masterrx(struct ausmbus_softc *sc) 408 { 409 uint32_t v; 410 int timeout; 411 timeout = sc->sc_smbus_timeout; 412 413 if (ausmbus_wait_mastertx(sc) != 0) 414 return -1; 415 416 do { 417 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 418 #ifdef AUSMBUS_PSC_DEBUG 419 aprint_normal("AuSMBus: ausmbus_wait_masterrx(): psc_smbstat=0x%08x\n", v); 420 #endif 421 if ((v & SMBUS_STAT_RE) == 0) 422 break; 423 timeout--; 424 delay(1); 425 } while (timeout > 0); 426 427 return 0; 428 } 429 430 static int 431 ausmbus_initiate_xfer(void *arg, i2c_addr_t addr, int flags) 432 { 433 struct ausmbus_softc *sc = arg; 434 uint32_t v; 435 436 /* Tx/Rx Slave Address */ 437 v = (addr << 1) & SMBUS_TXRX_ADDRDATA; 438 if ((flags & I2C_F_READ) != 0) 439 v |= 1; 440 ausmbus_reg_write(sc, AUPSC_SMBTXRX, v); 441 442 /* Master Start */ 443 ausmbus_reg_write(sc, AUPSC_SMBPCR, SMBUS_PCR_MS); 444 445 if (ausmbus_wait_mastertx(sc) != 0) 446 return -1; 447 448 return 0; 449 } 450 451 static int 452 ausmbus_read_byte(void *arg, uint8_t *vp, int flags) 453 { 454 struct ausmbus_softc *sc = arg; 455 uint32_t v; 456 457 if ((flags & I2C_F_STOP) != 0) { 458 ausmbus_reg_write(sc, AUPSC_SMBTXRX, SMBUS_TXRX_STP); 459 } else { 460 ausmbus_reg_write(sc, AUPSC_SMBTXRX, 0); 461 } 462 463 if (ausmbus_wait_masterrx(sc) != 0) 464 return -1; 465 466 v = ausmbus_reg_read(sc, AUPSC_SMBTXRX); 467 *vp = v & SMBUS_TXRX_ADDRDATA; 468 printf("read byte: 0x%02x\n", v); 469 470 return 0; 471 } 472 473 static int 474 ausmbus_write_byte(void *arg, uint8_t v, int flags) 475 { 476 struct ausmbus_softc *sc = arg; 477 478 if ((flags & I2C_F_STOP) != 0) { 479 ausmbus_reg_write(sc, AUPSC_SMBTXRX, (v | SMBUS_TXRX_STP)); 480 } else if ((flags & I2C_F_READ) != 0) { 481 ausmbus_reg_write(sc, AUPSC_SMBTXRX, (v | SMBUS_TXRX_RSR)); 482 } else { 483 ausmbus_reg_write(sc, AUPSC_SMBTXRX, v); 484 } 485 486 if (ausmbus_wait_mastertx(sc) != 0) 487 return -1; 488 489 return 0; 490 } 491
Indexes created Sat Oct 04 05:10:05 GMT 2025