ausmbus_psc.c revision 1.12
1 /* $NetBSD: ausmbus_psc.c,v 1.12 2016/02/14 19:54:21 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer in the documentation and/or other materials provided 17 * with the distribution. 18 * 3. The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ausmbus_psc.c,v 1.12 2016/02/14 19:54:21 chs Exp $"); 37 38 #include "locators.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/errno.h> 44 45 #include <sys/bus.h> 46 #include <machine/cpu.h> 47 48 #include <mips/alchemy/dev/aupscreg.h> 49 #include <mips/alchemy/dev/aupscvar.h> 50 #include <mips/alchemy/dev/ausmbus_pscreg.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/i2c_bitbang.h> 54 55 struct ausmbus_softc { 56 device_t sc_dev; 57 58 /* protocol comoon fields */ 59 struct aupsc_controller sc_ctrl; 60 61 /* protocol specific fields */ 62 struct i2c_controller sc_i2c; 63 i2c_addr_t sc_smbus_slave_addr; 64 int sc_smbus_timeout; 65 }; 66 67 #define ausmbus_reg_read(sc, reg) \ 68 bus_space_read_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg) 69 #define ausmbus_reg_write(sc, reg, val) \ 70 bus_space_write_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg, \ 71 val); \ 72 delay(100); 73 74 static int ausmbus_match(device_t, struct cfdata *, void *); 75 static void ausmbus_attach(device_t, device_t, void *); 76 77 CFATTACH_DECL_NEW(ausmbus, sizeof(struct ausmbus_softc), 78 ausmbus_match, ausmbus_attach, NULL, NULL); 79 80 /* fuctions for i2c_controller */ 81 static int ausmbus_acquire_bus(void *, int); 82 static void ausmbus_release_bus(void *, int); 83 static int ausmbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 84 const void *cmd, size_t cmdlen, void *vbuf, 85 size_t buflen, int flags); 86 87 /* subroutine functions for i2c_controller */ 88 static int ausmbus_quick_write(struct ausmbus_softc *); 89 static int ausmbus_quick_read(struct ausmbus_softc *); 90 static int ausmbus_receive_1(struct ausmbus_softc *, uint8_t *); 91 static int ausmbus_read_1(struct ausmbus_softc *, uint8_t, uint8_t *); 92 static int ausmbus_read_2(struct ausmbus_softc *, uint8_t, uint16_t *); 93 static int ausmbus_send_1(struct ausmbus_softc *, uint8_t); 94 static int ausmbus_write_1(struct ausmbus_softc *, uint8_t, uint8_t); 95 static int ausmbus_write_2(struct ausmbus_softc *, uint8_t, uint16_t); 96 static int ausmbus_wait_mastertx(struct ausmbus_softc *sc); 97 static int ausmbus_wait_masterrx(struct ausmbus_softc *sc); 98 static int ausmbus_initiate_xfer(void *, i2c_addr_t, int); 99 static int ausmbus_read_byte(void *arg, uint8_t *vp, int flags); 100 static int ausmbus_write_byte(void *arg, uint8_t v, int flags); 101 102 103 static int 104 ausmbus_match(device_t parent, struct cfdata *cf, void *aux) 105 { 106 struct aupsc_attach_args *aa = (struct aupsc_attach_args *)aux; 107 108 if (strcmp(aa->aupsc_name, cf->cf_name) != 0) 109 return 0; 110 111 return 1; 112 } 113 114 static void 115 ausmbus_attach(device_t parent, device_t self, void *aux) 116 { 117 struct ausmbus_softc *sc = device_private(self); 118 struct aupsc_attach_args *aa = (struct aupsc_attach_args *)aux; 119 struct i2cbus_attach_args iba; 120 121 aprint_normal(": Alchemy PSC SMBus protocol\n"); 122 123 sc->sc_dev = self; 124 125 /* Initialize PSC */ 126 sc->sc_ctrl = aa->aupsc_ctrl; 127 128 /* Initialize i2c_controller for SMBus */ 129 sc->sc_i2c.ic_cookie = sc; 130 sc->sc_i2c.ic_acquire_bus = ausmbus_acquire_bus; 131 sc->sc_i2c.ic_release_bus = ausmbus_release_bus; 132 sc->sc_i2c.ic_send_start = NULL; 133 sc->sc_i2c.ic_send_stop = NULL; 134 sc->sc_i2c.ic_initiate_xfer = NULL; 135 sc->sc_i2c.ic_read_byte = NULL; 136 sc->sc_i2c.ic_write_byte = NULL; 137 sc->sc_i2c.ic_exec = ausmbus_exec; 138 sc->sc_smbus_timeout = 10; 139 140 memset(&iba, 0, sizeof(iba)); 141 iba.iba_tag = &sc->sc_i2c; 142 (void) config_found_ia(self, "i2cbus", &iba, iicbus_print); 143 } 144 145 static int 146 ausmbus_acquire_bus(void *arg, int flags) 147 { 148 struct ausmbus_softc *sc = arg; 149 uint32_t v; 150 151 /* Select SMBus Protocol & Enable PSC */ 152 sc->sc_ctrl.psc_enable(sc, AUPSC_SEL_SMBUS); 153 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 154 if ((v & SMBUS_STAT_SR) == 0) { 155 /* PSC is not ready */ 156 return -1; 157 } 158 159 /* Setup SMBus Configuration register */ 160 v = SMBUS_CFG_DD; /* Disable DMA */ 161 v |= SMBUS_CFG_RT_SET(SMBUS_CFG_RT_FIFO8); /* Rx FIFO 8data */ 162 v |= SMBUS_CFG_TT_SET(SMBUS_CFG_TT_FIFO8); /* Tx FIFO 8data */ 163 v |= SMBUS_CFG_DIV_SET(SMBUS_CFG_DIV8); /* pscn_mainclk/8 */ 164 v &= ~SMBUS_CFG_SFM; /* Standard Mode */ 165 ausmbus_reg_write(sc, AUPSC_SMBCFG, v); 166 167 /* Setup SMBus Protocol Timing register */ 168 v = SMBUS_TMR_TH_SET(SMBUS_TMR_STD_TH) 169 | SMBUS_TMR_PS_SET(SMBUS_TMR_STD_PS) 170 | SMBUS_TMR_PU_SET(SMBUS_TMR_STD_PU) 171 | SMBUS_TMR_SH_SET(SMBUS_TMR_STD_SH) 172 | SMBUS_TMR_SU_SET(SMBUS_TMR_STD_SU) 173 | SMBUS_TMR_CL_SET(SMBUS_TMR_STD_CL) 174 | SMBUS_TMR_CH_SET(SMBUS_TMR_STD_CH); 175 ausmbus_reg_write(sc, AUPSC_SMBTMR, v); 176 177 /* Setup SMBus Mask register */ 178 v = SMBUS_MSK_ALLMASK; 179 ausmbus_reg_write(sc, AUPSC_SMBMSK, v); 180 181 /* SMBus Enable */ 182 v = ausmbus_reg_read(sc, AUPSC_SMBCFG); 183 v |= SMBUS_CFG_DE; 184 ausmbus_reg_write(sc, AUPSC_SMBCFG, v); 185 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 186 if ((v & SMBUS_STAT_SR) == 0) { 187 /* SMBus is not ready */ 188 return -1; 189 } 190 191 #ifdef AUSMBUS_PSC_DEBUG 192 aprint_normal("AuSMBus enabled.\n"); 193 aprint_normal("AuSMBus smbconfig: 0x%08x\n", 194 ausmbus_reg_read(sc, AUPSC_SMBCFG)); 195 aprint_normal("AuSMBus smbstatus: 0x%08x\n", 196 ausmbus_reg_read(sc, AUPSC_SMBSTAT)); 197 aprint_normal("AuSMBus smbtmr : 0x%08x\n", 198 ausmbus_reg_read(sc, AUPSC_SMBTMR)); 199 aprint_normal("AuSMBus smbmask : 0x%08x\n", 200 ausmbus_reg_read(sc, AUPSC_SMBMSK)); 201 #endif 202 203 return 0; 204 } 205 206 static void 207 ausmbus_release_bus(void *arg, int flags) 208 { 209 struct ausmbus_softc *sc = arg; 210 211 ausmbus_reg_write(sc, AUPSC_SMBCFG, 0); 212 sc->sc_ctrl.psc_disable(sc); 213 214 return; 215 } 216 217 static int 218 ausmbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd, 219 size_t cmdlen, void *vbuf, size_t buflen, int flags) 220 { 221 struct ausmbus_softc *sc = (struct ausmbus_softc *)cookie; 222 const uint8_t *cmd = vcmd; 223 224 sc->sc_smbus_slave_addr = addr; 225 226 /* Receive byte */ 227 if ((I2C_OP_READ_P(op)) && (cmdlen == 0) && (buflen == 1)) { 228 return ausmbus_receive_1(sc, (uint8_t *)vbuf); 229 } 230 231 /* Read byte */ 232 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 233 return ausmbus_read_1(sc, *cmd, (uint8_t *)vbuf); 234 } 235 236 /* Read word */ 237 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 2)) { 238 return ausmbus_read_2(sc, *cmd, (uint16_t *)vbuf); 239 } 240 241 /* Read quick */ 242 if ((I2C_OP_READ_P(op)) && (cmdlen == 0) && (buflen == 0)) { 243 return ausmbus_quick_read(sc); 244 } 245 246 /* Send byte */ 247 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 248 return ausmbus_send_1(sc, *((uint8_t *)vbuf)); 249 } 250 251 /* Write byte */ 252 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 253 return ausmbus_write_1(sc, *cmd, *((uint8_t *)vbuf)); 254 } 255 256 /* Write word */ 257 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 2)) { 258 return ausmbus_write_2(sc, *cmd, *((uint16_t *)vbuf)); 259 } 260 261 /* Write quick */ 262 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 0)) { 263 return ausmbus_quick_write(sc); 264 } 265 266 /* 267 * XXX: TODO Please Support other protocols defined in SMBus 2.0 268 * - Process call 269 * - Block write/read 270 * - Clock write-block read process cal 271 * - SMBus host notify protocol 272 * 273 * - Read quick and write quick have not been tested! 274 */ 275 276 return -1; 277 } 278 279 static int 280 ausmbus_receive_1(struct ausmbus_softc *sc, uint8_t *vp) 281 { 282 int error; 283 284 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 285 if (error != 0) { 286 return error; 287 } 288 error = ausmbus_read_byte(sc, vp, I2C_F_STOP); 289 if (error != 0) { 290 return error; 291 } 292 293 return 0; 294 } 295 296 static int 297 ausmbus_read_1(struct ausmbus_softc *sc, uint8_t cmd, uint8_t *vp) 298 { 299 int error; 300 301 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 302 if (error != 0) { 303 return error; 304 } 305 306 error = ausmbus_write_byte(sc, cmd, I2C_F_READ); 307 if (error != 0) { 308 return error; 309 } 310 311 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 312 if (error != 0) { 313 return error; 314 } 315 316 error = ausmbus_read_byte(sc, vp, I2C_F_STOP); 317 if (error != 0) { 318 return error; 319 } 320 321 return 0; 322 } 323 324 static int 325 ausmbus_read_2(struct ausmbus_softc *sc, uint8_t cmd, uint16_t *vp) 326 { 327 int error; 328 uint8_t high, low; 329 330 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 331 if (error != 0) { 332 return error; 333 } 334 335 error = ausmbus_write_byte(sc, cmd, I2C_F_READ); 336 if (error != 0) { 337 return error; 338 } 339 340 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 341 if (error != 0) { 342 return error; 343 } 344 345 error = ausmbus_read_byte(sc, &low, 0); 346 if (error != 0) { 347 return error; 348 } 349 350 error = ausmbus_read_byte(sc, &high, I2C_F_STOP); 351 if (error != 0) { 352 return error; 353 } 354 355 *vp = (high << 8) | low; 356 357 return 0; 358 } 359 360 static int 361 ausmbus_send_1(struct ausmbus_softc *sc, uint8_t val) 362 { 363 int error; 364 365 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 366 if (error != 0) { 367 return error; 368 } 369 370 error = ausmbus_write_byte(sc, val, I2C_F_STOP); 371 if (error != 0) { 372 return error; 373 } 374 375 return 0; 376 } 377 378 static int 379 ausmbus_write_1(struct ausmbus_softc *sc, uint8_t cmd, uint8_t val) 380 { 381 int error; 382 383 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 384 if (error != 0) { 385 return error; 386 } 387 388 error = ausmbus_write_byte(sc, cmd, 0); 389 if (error != 0) { 390 return error; 391 } 392 393 error = ausmbus_write_byte(sc, val, I2C_F_STOP); 394 if (error != 0) { 395 return error; 396 } 397 398 return 0; 399 } 400 401 static int 402 ausmbus_write_2(struct ausmbus_softc *sc, uint8_t cmd, uint16_t val) 403 { 404 int error; 405 uint8_t high, low; 406 407 high = (val >> 8) & 0xff; 408 low = val & 0xff; 409 410 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 411 if (error != 0) { 412 return error; 413 } 414 415 error = ausmbus_write_byte(sc, cmd, 0); 416 if (error != 0) { 417 return error; 418 } 419 420 error = ausmbus_write_byte(sc, low, 0); 421 if (error != 0) { 422 return error; 423 } 424 425 error = ausmbus_write_byte(sc, high, I2C_F_STOP); 426 if (error != 0) { 427 return error; 428 } 429 430 return 0; 431 } 432 433 /* 434 * XXX The quick_write() and quick_read() routines have not been tested! 435 */ 436 static int 437 ausmbus_quick_write(struct ausmbus_softc *sc) 438 { 439 return ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, 440 I2C_F_STOP | I2C_F_WRITE); 441 } 442 443 static int 444 ausmbus_quick_read(struct ausmbus_softc *sc) 445 { 446 return ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, 447 I2C_F_STOP | I2C_F_READ); 448 } 449 450 static int 451 ausmbus_wait_mastertx(struct ausmbus_softc *sc) 452 { 453 uint32_t v; 454 int timeout; 455 int txerr = 0; 456 457 timeout = sc->sc_smbus_timeout; 458 459 do { 460 v = ausmbus_reg_read(sc, AUPSC_SMBEVNT); 461 #ifdef AUSMBUS_PSC_DEBUG 462 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): psc_smbevnt=0x%08x\n", v); 463 #endif 464 if ((v & SMBUS_EVNT_TU) != 0) 465 break; 466 if ((v & SMBUS_EVNT_MD) != 0) 467 break; 468 if ((v & (SMBUS_EVNT_DN | SMBUS_EVNT_AN | SMBUS_EVNT_AL)) 469 != 0) { 470 txerr = 1; 471 break; 472 } 473 timeout--; 474 delay(1); 475 } while (timeout > 0); 476 477 if (txerr != 0) { 478 ausmbus_reg_write(sc, AUPSC_SMBEVNT, 479 SMBUS_EVNT_DN | SMBUS_EVNT_AN | SMBUS_EVNT_AL); 480 #ifdef AUSMBUS_PSC_DEBUG 481 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): Tx error\n"); 482 #endif 483 return -1; 484 } 485 486 /* Reset Event TU (Tx Underflow) */ 487 ausmbus_reg_write(sc, AUPSC_SMBEVNT, SMBUS_EVNT_TU | SMBUS_EVNT_MD); 488 489 #ifdef AUSMBUS_PSC_DEBUG 490 v = ausmbus_reg_read(sc, AUPSC_SMBEVNT); 491 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): psc_smbevnt=0x%08x (reset)\n", v); 492 #endif 493 return 0; 494 } 495 496 static int 497 ausmbus_wait_masterrx(struct ausmbus_softc *sc) 498 { 499 uint32_t v; 500 int timeout; 501 timeout = sc->sc_smbus_timeout; 502 503 if (ausmbus_wait_mastertx(sc) != 0) 504 return -1; 505 506 do { 507 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 508 #ifdef AUSMBUS_PSC_DEBUG 509 aprint_normal("AuSMBus: ausmbus_wait_masterrx(): psc_smbstat=0x%08x\n", v); 510 #endif 511 if ((v & SMBUS_STAT_RE) == 0) 512 break; 513 timeout--; 514 delay(1); 515 } while (timeout > 0); 516 517 return 0; 518 } 519 520 static int 521 ausmbus_initiate_xfer(void *arg, i2c_addr_t addr, int flags) 522 { 523 struct ausmbus_softc *sc = arg; 524 uint32_t v; 525 526 /* Tx/Rx Slave Address */ 527 v = (addr << 1) & SMBUS_TXRX_ADDRDATA; 528 if ((flags & I2C_F_READ) != 0) 529 v |= 1; 530 if ((flags & I2C_F_STOP) != 0) 531 v |= SMBUS_TXRX_STP; 532 ausmbus_reg_write(sc, AUPSC_SMBTXRX, v); 533 534 /* Master Start */ 535 ausmbus_reg_write(sc, AUPSC_SMBPCR, SMBUS_PCR_MS); 536 537 if (ausmbus_wait_mastertx(sc) != 0) 538 return -1; 539 540 return 0; 541 } 542 543 static int 544 ausmbus_read_byte(void *arg, uint8_t *vp, int flags) 545 { 546 struct ausmbus_softc *sc = arg; 547 uint32_t v; 548 549 if ((flags & I2C_F_STOP) != 0) { 550 ausmbus_reg_write(sc, AUPSC_SMBTXRX, SMBUS_TXRX_STP); 551 } else { 552 ausmbus_reg_write(sc, AUPSC_SMBTXRX, 0); 553 } 554 555 if (ausmbus_wait_masterrx(sc) != 0) 556 return -1; 557 558 v = ausmbus_reg_read(sc, AUPSC_SMBTXRX); 559 *vp = v & SMBUS_TXRX_ADDRDATA; 560 561 return 0; 562 } 563 564 static int 565 ausmbus_write_byte(void *arg, uint8_t v, int flags) 566 { 567 struct ausmbus_softc *sc = arg; 568 569 if ((flags & I2C_F_STOP) != 0) { 570 ausmbus_reg_write(sc, AUPSC_SMBTXRX, (v | SMBUS_TXRX_STP)); 571 } else if ((flags & I2C_F_READ) != 0) { 572 ausmbus_reg_write(sc, AUPSC_SMBTXRX, (v | SMBUS_TXRX_RSR)); 573 } else { 574 ausmbus_reg_write(sc, AUPSC_SMBTXRX, v); 575 } 576 577 if (ausmbus_wait_mastertx(sc) != 0) 578 return -1; 579 580 return 0; 581 } 582
Indexes created Sat Oct 04 16:09:51 GMT 2025