ausmbus_psc.c revision 1.4
1 /* $NetBSD: ausmbus_psc.c,v 1.4 2006/03/27 19:03:50 shige Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer in the documentation and/or other materials provided 17 * with the distribution. 18 * 3. The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ausmbus_psc.c,v 1.4 2006/03/27 19:03:50 shige Exp $"); 37 38 #include "locators.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/errno.h> 44 45 #include <machine/bus.h> 46 #include <machine/cpu.h> 47 48 #include <mips/alchemy/dev/aupscreg.h> 49 #include <mips/alchemy/dev/aupscvar.h> 50 #include <mips/alchemy/dev/ausmbus_pscreg.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/i2c_bitbang.h> 54 55 struct ausmbus_softc { 56 struct device sc_dev; 57 58 /* protocol comoon fields */ 59 struct aupsc_controller sc_ctrl; 60 61 /* protocol specific fields */ 62 struct i2c_controller sc_i2c; 63 i2c_addr_t sc_smbus_slave_addr; 64 int sc_smbus_timeout; 65 }; 66 67 #define ausmbus_reg_read(sc, reg) \ 68 bus_space_read_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg) 69 #define ausmbus_reg_write(sc, reg, val) \ 70 bus_space_write_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg, \ 71 val); \ 72 delay(100); 73 74 static int ausmbus_match(struct device *, struct cfdata *, void *); 75 static void ausmbus_attach(struct device *, struct device *, void *); 76 77 CFATTACH_DECL(ausmbus, sizeof(struct ausmbus_softc), 78 ausmbus_match, ausmbus_attach, NULL, NULL); 79 80 /* fuctions for i2c_controller */ 81 static int ausmbus_acquire_bus(void *, int); 82 static void ausmbus_release_bus(void *, int); 83 static int ausmbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 84 const void *cmd, size_t cmdlen, void *vbuf, 85 size_t buflen, int flags); 86 87 /* subroutine functions for i2c_controller */ 88 static int ausmbus_receive_1(struct ausmbus_softc *, uint8_t *); 89 static int ausmbus_read_1(struct ausmbus_softc *, uint8_t, uint8_t *); 90 static int ausmbus_send_1(struct ausmbus_softc *, uint8_t); 91 static int ausmbus_write_1(struct ausmbus_softc *, uint8_t, uint8_t); 92 static int ausmbus_wait_mastertx(struct ausmbus_softc *sc); 93 static int ausmbus_wait_masterrx(struct ausmbus_softc *sc); 94 static int ausmbus_initiate_xfer(void *, i2c_addr_t, int); 95 static int ausmbus_read_byte(void *arg, uint8_t *vp, int flags); 96 static int ausmbus_write_byte(void *arg, uint8_t v, int flags); 97 98 99 static int 100 ausmbus_match(struct device *parent, struct cfdata *cf, void *aux) 101 { 102 struct aupsc_attach_args *aa = (struct aupsc_attach_args *)aux; 103 104 if (strcmp(aa->aupsc_name, cf->cf_name) != 0) 105 return 0; 106 107 return 1; 108 } 109 110 static void 111 ausmbus_attach(struct device *parent, struct device *self, void *aux) 112 { 113 struct ausmbus_softc *sc = (struct ausmbus_softc *)self; 114 struct aupsc_attach_args *aa = (struct aupsc_attach_args *)aux; 115 struct i2cbus_attach_args iba; 116 117 aprint_normal(": Alchemy PSC SMBus protocol\n"); 118 119 /* Initialize PSC */ 120 sc->sc_ctrl = aa->aupsc_ctrl; 121 122 /* Initialize i2c_controller for SMBus */ 123 sc->sc_i2c.ic_cookie = sc; 124 sc->sc_i2c.ic_acquire_bus = ausmbus_acquire_bus; 125 sc->sc_i2c.ic_release_bus = ausmbus_release_bus; 126 sc->sc_i2c.ic_send_start = NULL; 127 sc->sc_i2c.ic_send_stop = NULL; 128 sc->sc_i2c.ic_initiate_xfer = NULL; 129 sc->sc_i2c.ic_read_byte = NULL; 130 sc->sc_i2c.ic_write_byte = NULL; 131 sc->sc_i2c.ic_exec = ausmbus_exec; 132 sc->sc_smbus_timeout = 10; 133 134 iba.iba_name = "iic"; 135 iba.iba_tag = &sc->sc_i2c; 136 (void) config_found(&sc->sc_dev, &iba, iicbus_print); 137 } 138 139 static int 140 ausmbus_acquire_bus(void *arg, int flags) 141 { 142 struct ausmbus_softc *sc = arg; 143 uint32_t v; 144 145 /* Select SMBus Protocol & Enable PSC */ 146 sc->sc_ctrl.psc_enable(sc, AUPSC_SEL_SMBUS); 147 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 148 if ((v & SMBUS_STAT_SR) == 0) { 149 /* PSC is not ready */ 150 return -1; 151 } 152 153 /* Setup SMBus Configuration register */ 154 v = SMBUS_CFG_DD; /* Disable DMA */ 155 v |= SMBUS_CFG_RT_SET(SMBUS_CFG_RT_FIFO8); /* Rx FIFO 8data */ 156 v |= SMBUS_CFG_TT_SET(SMBUS_CFG_TT_FIFO8); /* Tx FIFO 8data */ 157 v |= SMBUS_CFG_DIV_SET(SMBUS_CFG_DIV8); /* pscn_mainclk/8 */ 158 v &= ~SMBUS_CFG_SFM; /* Standard Mode */ 159 ausmbus_reg_write(sc, AUPSC_SMBCFG, v); 160 161 /* Setup SMBus Protocol Timing register */ 162 v = SMBUS_TMR_TH_SET(SMBUS_TMR_STD_TH) 163 | SMBUS_TMR_PS_SET(SMBUS_TMR_STD_PS) 164 | SMBUS_TMR_PU_SET(SMBUS_TMR_STD_PU) 165 | SMBUS_TMR_SH_SET(SMBUS_TMR_STD_SH) 166 | SMBUS_TMR_SU_SET(SMBUS_TMR_STD_SU) 167 | SMBUS_TMR_CL_SET(SMBUS_TMR_STD_CL) 168 | SMBUS_TMR_CH_SET(SMBUS_TMR_STD_CH); 169 ausmbus_reg_write(sc, AUPSC_SMBTMR, v); 170 171 /* Setup SMBus Mask register */ 172 v = SMBUS_MSK_ALLMASK; 173 ausmbus_reg_write(sc, AUPSC_SMBMSK, v); 174 175 /* SMBus Enable */ 176 v = ausmbus_reg_read(sc, AUPSC_SMBCFG); 177 v |= SMBUS_CFG_DE; 178 ausmbus_reg_write(sc, AUPSC_SMBCFG, v); 179 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 180 if ((v & SMBUS_STAT_SR) == 0) { 181 /* SMBus is not ready */ 182 return -1; 183 } 184 185 #ifdef AUSMBUS_PSC_DEBUG 186 aprint_normal("AuSMBus enabled.\n"); 187 aprint_normal("AuSMBus smbconfig: 0x%08x\n", 188 ausmbus_reg_read(sc, AUPSC_SMBCFG)); 189 aprint_normal("AuSMBus smbstatus: 0x%08x\n", 190 ausmbus_reg_read(sc, AUPSC_SMBSTAT)); 191 aprint_normal("AuSMBus smbtmr : 0x%08x\n", 192 ausmbus_reg_read(sc, AUPSC_SMBTMR)); 193 aprint_normal("AuSMBus smbmask : 0x%08x\n", 194 ausmbus_reg_read(sc, AUPSC_SMBMSK)); 195 #endif 196 197 return 0; 198 } 199 200 static void 201 ausmbus_release_bus(void *arg, int flags) 202 { 203 struct ausmbus_softc *sc = arg; 204 205 ausmbus_reg_write(sc, AUPSC_SMBCFG, 0); 206 sc->sc_ctrl.psc_disable(sc); 207 208 return; 209 } 210 211 static int 212 ausmbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd, 213 size_t cmdlen, void *vbuf, size_t buflen, int flags) 214 { 215 struct ausmbus_softc *sc = (struct ausmbus_softc *)cookie; 216 const uint8_t *cmd = vcmd; 217 uint8_t *buf = vbuf; 218 219 sc->sc_smbus_slave_addr = addr; 220 221 /* Receive byte */ 222 if ((I2C_OP_READ_P(op)) && (cmdlen == 0) && (buflen == 1)) { 223 return ausmbus_receive_1(sc, buf); 224 } 225 226 /* Read byte */ 227 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 228 return ausmbus_read_1(sc, *cmd, buf); 229 } 230 231 /* Send byte */ 232 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 233 return ausmbus_send_1(sc, *buf); 234 } 235 236 /* Write byte */ 237 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 238 return ausmbus_write_1(sc, *cmd, *buf); 239 } 240 241 /* 242 * XXX: TODO Please Support other protocols defined in SMBus 2.0 243 * - Quick Command 244 * - Write word 245 * - Read word 246 * - Process call 247 * - Block write/read 248 * - Clock write-block read process cal 249 * - SMBus host notify protocol 250 */ 251 252 return -1; 253 } 254 255 static int 256 ausmbus_receive_1(struct ausmbus_softc *sc, uint8_t *vp) 257 { 258 int error; 259 260 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 261 if (error != 0) { 262 return error; 263 } 264 error = ausmbus_read_byte(sc, vp, I2C_F_STOP); 265 if (error != 0) { 266 return error; 267 } 268 269 return 0; 270 } 271 272 static int 273 ausmbus_read_1(struct ausmbus_softc *sc, uint8_t cmd, uint8_t *vp) 274 { 275 int error; 276 277 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 278 if (error != 0) { 279 return error; 280 } 281 282 error = ausmbus_write_byte(sc, cmd, I2C_F_READ); 283 if (error != 0) { 284 return error; 285 } 286 287 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 288 if (error != 0) { 289 return error; 290 } 291 292 error = ausmbus_read_byte(sc, vp, I2C_F_STOP); 293 if (error != 0) { 294 return error; 295 } 296 297 return 0; 298 } 299 300 static int 301 ausmbus_send_1(struct ausmbus_softc *sc, uint8_t val) 302 { 303 int error; 304 305 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 306 if (error != 0) { 307 return error; 308 } 309 310 error = ausmbus_write_byte(sc, val, I2C_F_STOP); 311 if (error != 0) { 312 return error; 313 } 314 315 return 0; 316 } 317 318 static int 319 ausmbus_write_1(struct ausmbus_softc *sc, uint8_t cmd, uint8_t val) 320 { 321 int error; 322 323 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 324 if (error != 0) { 325 return error; 326 } 327 328 error = ausmbus_write_byte(sc, cmd, 0); 329 if (error != 0) { 330 return error; 331 } 332 333 error = ausmbus_write_byte(sc, val, I2C_F_STOP); 334 if (error != 0) { 335 return error; 336 } 337 338 return 0; 339 } 340 341 static int 342 ausmbus_wait_mastertx(struct ausmbus_softc *sc) 343 { 344 uint32_t v; 345 int timeout; 346 int txerr = 0; 347 348 timeout = sc->sc_smbus_timeout; 349 350 do { 351 v = ausmbus_reg_read(sc, AUPSC_SMBEVNT); 352 #ifdef AUSMBUS_PSC_DEBUG 353 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): psc_smbevnt=0x%08x\n", v); 354 #endif 355 if ((v & SMBUS_EVNT_TU) != 0) 356 break; 357 if ((v & SMBUS_EVNT_MD) != 0) 358 break; 359 if ((v & (SMBUS_EVNT_DN | SMBUS_EVNT_AN | SMBUS_EVNT_AL)) 360 != 0) { 361 txerr = 1; 362 break; 363 } 364 timeout--; 365 delay(1); 366 } while (timeout > 0); 367 368 if (txerr != 0) { 369 ausmbus_reg_write(sc, AUPSC_SMBEVNT, 370 SMBUS_EVNT_DN | SMBUS_EVNT_AN | SMBUS_EVNT_AL); 371 #ifdef AUSMBUS_PSC_DEBUG 372 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): Tx error\n"); 373 #endif 374 return -1; 375 } 376 377 /* Reset Event TU (Tx Underflow) */ 378 ausmbus_reg_write(sc, AUPSC_SMBEVNT, SMBUS_EVNT_TU | SMBUS_EVNT_MD); 379 380 #ifdef AUSMBUS_PSC_DEBUG 381 v = ausmbus_reg_read(sc, AUPSC_SMBEVNT); 382 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): psc_smbevnt=0x%08x (reset)\n", v); 383 #endif 384 return 0; 385 } 386 387 static int 388 ausmbus_wait_masterrx(struct ausmbus_softc *sc) 389 { 390 uint32_t v; 391 int timeout; 392 timeout = sc->sc_smbus_timeout; 393 394 if (ausmbus_wait_mastertx(sc) != 0) 395 return -1; 396 397 do { 398 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 399 #ifdef AUSMBUS_PSC_DEBUG 400 aprint_normal("AuSMBus: ausmbus_wait_masterrx(): psc_smbstat=0x%08x\n", v); 401 #endif 402 if ((v & SMBUS_STAT_RE) == 0) 403 break; 404 timeout--; 405 delay(1); 406 } while (timeout > 0); 407 408 return 0; 409 } 410 411 static int 412 ausmbus_initiate_xfer(void *arg, i2c_addr_t addr, int flags) 413 { 414 struct ausmbus_softc *sc = arg; 415 uint32_t v; 416 417 /* Tx/Rx Slave Address */ 418 v = (addr << 1) & SMBUS_TXRX_ADDRDATA; 419 if ((flags & I2C_F_READ) != 0) 420 v |= 1; 421 ausmbus_reg_write(sc, AUPSC_SMBTXRX, v); 422 423 /* Master Start */ 424 ausmbus_reg_write(sc, AUPSC_SMBPCR, SMBUS_PCR_MS); 425 426 if (ausmbus_wait_mastertx(sc) != 0) 427 return -1; 428 429 return 0; 430 } 431 432 static int 433 ausmbus_read_byte(void *arg, uint8_t *vp, int flags) 434 { 435 struct ausmbus_softc *sc = arg; 436 uint32_t v; 437 438 if ((flags & I2C_F_STOP) != 0) { 439 ausmbus_reg_write(sc, AUPSC_SMBTXRX, SMBUS_TXRX_STP); 440 } else { 441 ausmbus_reg_write(sc, AUPSC_SMBTXRX, 0); 442 } 443 444 if (ausmbus_wait_masterrx(sc) != 0) 445 return -1; 446 447 v = ausmbus_reg_read(sc, AUPSC_SMBTXRX); 448 *vp = v & SMBUS_TXRX_ADDRDATA; 449 450 return 0; 451 } 452 453 static int 454 ausmbus_write_byte(void *arg, uint8_t v, int flags) 455 { 456 struct ausmbus_softc *sc = arg; 457 458 if ((flags & I2C_F_STOP) != 0) { 459 ausmbus_reg_write(sc, AUPSC_SMBTXRX, (v | SMBUS_TXRX_STP)); 460 } else if ((flags & I2C_F_READ) != 0) { 461 ausmbus_reg_write(sc, AUPSC_SMBTXRX, (v | SMBUS_TXRX_RSR)); 462 } else { 463 ausmbus_reg_write(sc, AUPSC_SMBTXRX, v); 464 } 465 466 if (ausmbus_wait_mastertx(sc) != 0) 467 return -1; 468 469 return 0; 470 } 471
Indexes created Sat Oct 04 05:10:05 GMT 2025