ausmbus_psc.c revision 1.5
1 /* $NetBSD: ausmbus_psc.c,v 1.5 2006/06/25 13:32:16 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Shigeyuki Fukushima. 5 * All rights reserved. 6 * 7 * Written by Shigeyuki Fukushima. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer in the documentation and/or other materials provided 17 * with the distribution. 18 * 3. The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ausmbus_psc.c,v 1.5 2006/06/25 13:32:16 kiyohara Exp $"); 37 38 #include "locators.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/errno.h> 44 45 #include <machine/bus.h> 46 #include <machine/cpu.h> 47 48 #include <mips/alchemy/dev/aupscreg.h> 49 #include <mips/alchemy/dev/aupscvar.h> 50 #include <mips/alchemy/dev/ausmbus_pscreg.h> 51 52 #include <dev/i2c/i2cvar.h> 53 #include <dev/i2c/i2c_bitbang.h> 54 55 struct ausmbus_softc { 56 struct device sc_dev; 57 58 /* protocol comoon fields */ 59 struct aupsc_controller sc_ctrl; 60 61 /* protocol specific fields */ 62 struct i2c_controller sc_i2c; 63 i2c_addr_t sc_smbus_slave_addr; 64 int sc_smbus_timeout; 65 }; 66 67 #define ausmbus_reg_read(sc, reg) \ 68 bus_space_read_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg) 69 #define ausmbus_reg_write(sc, reg, val) \ 70 bus_space_write_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg, \ 71 val); \ 72 delay(100); 73 74 static int ausmbus_match(struct device *, struct cfdata *, void *); 75 static void ausmbus_attach(struct device *, struct device *, void *); 76 77 CFATTACH_DECL(ausmbus, sizeof(struct ausmbus_softc), 78 ausmbus_match, ausmbus_attach, NULL, NULL); 79 80 /* fuctions for i2c_controller */ 81 static int ausmbus_acquire_bus(void *, int); 82 static void ausmbus_release_bus(void *, int); 83 static int ausmbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 84 const void *cmd, size_t cmdlen, void *vbuf, 85 size_t buflen, int flags); 86 87 /* subroutine functions for i2c_controller */ 88 static int ausmbus_receive_1(struct ausmbus_softc *, uint8_t *); 89 static int ausmbus_read_1(struct ausmbus_softc *, uint8_t, uint8_t *); 90 static int ausmbus_read_2(struct ausmbus_softc *, uint8_t, uint16_t *); 91 static int ausmbus_send_1(struct ausmbus_softc *, uint8_t); 92 static int ausmbus_write_1(struct ausmbus_softc *, uint8_t, uint8_t); 93 static int ausmbus_write_2(struct ausmbus_softc *, uint8_t, uint16_t); 94 static int ausmbus_wait_mastertx(struct ausmbus_softc *sc); 95 static int ausmbus_wait_masterrx(struct ausmbus_softc *sc); 96 static int ausmbus_initiate_xfer(void *, i2c_addr_t, int); 97 static int ausmbus_read_byte(void *arg, uint8_t *vp, int flags); 98 static int ausmbus_write_byte(void *arg, uint8_t v, int flags); 99 100 101 static int 102 ausmbus_match(struct device *parent, struct cfdata *cf, void *aux) 103 { 104 struct aupsc_attach_args *aa = (struct aupsc_attach_args *)aux; 105 106 if (strcmp(aa->aupsc_name, cf->cf_name) != 0) 107 return 0; 108 109 return 1; 110 } 111 112 static void 113 ausmbus_attach(struct device *parent, struct device *self, void *aux) 114 { 115 struct ausmbus_softc *sc = (struct ausmbus_softc *)self; 116 struct aupsc_attach_args *aa = (struct aupsc_attach_args *)aux; 117 struct i2cbus_attach_args iba; 118 119 aprint_normal(": Alchemy PSC SMBus protocol\n"); 120 121 /* Initialize PSC */ 122 sc->sc_ctrl = aa->aupsc_ctrl; 123 124 /* Initialize i2c_controller for SMBus */ 125 sc->sc_i2c.ic_cookie = sc; 126 sc->sc_i2c.ic_acquire_bus = ausmbus_acquire_bus; 127 sc->sc_i2c.ic_release_bus = ausmbus_release_bus; 128 sc->sc_i2c.ic_send_start = NULL; 129 sc->sc_i2c.ic_send_stop = NULL; 130 sc->sc_i2c.ic_initiate_xfer = NULL; 131 sc->sc_i2c.ic_read_byte = NULL; 132 sc->sc_i2c.ic_write_byte = NULL; 133 sc->sc_i2c.ic_exec = ausmbus_exec; 134 sc->sc_smbus_timeout = 10; 135 136 iba.iba_name = "iic"; 137 iba.iba_tag = &sc->sc_i2c; 138 (void) config_found(&sc->sc_dev, &iba, iicbus_print); 139 } 140 141 static int 142 ausmbus_acquire_bus(void *arg, int flags) 143 { 144 struct ausmbus_softc *sc = arg; 145 uint32_t v; 146 147 /* Select SMBus Protocol & Enable PSC */ 148 sc->sc_ctrl.psc_enable(sc, AUPSC_SEL_SMBUS); 149 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 150 if ((v & SMBUS_STAT_SR) == 0) { 151 /* PSC is not ready */ 152 return -1; 153 } 154 155 /* Setup SMBus Configuration register */ 156 v = SMBUS_CFG_DD; /* Disable DMA */ 157 v |= SMBUS_CFG_RT_SET(SMBUS_CFG_RT_FIFO8); /* Rx FIFO 8data */ 158 v |= SMBUS_CFG_TT_SET(SMBUS_CFG_TT_FIFO8); /* Tx FIFO 8data */ 159 v |= SMBUS_CFG_DIV_SET(SMBUS_CFG_DIV8); /* pscn_mainclk/8 */ 160 v &= ~SMBUS_CFG_SFM; /* Standard Mode */ 161 ausmbus_reg_write(sc, AUPSC_SMBCFG, v); 162 163 /* Setup SMBus Protocol Timing register */ 164 v = SMBUS_TMR_TH_SET(SMBUS_TMR_STD_TH) 165 | SMBUS_TMR_PS_SET(SMBUS_TMR_STD_PS) 166 | SMBUS_TMR_PU_SET(SMBUS_TMR_STD_PU) 167 | SMBUS_TMR_SH_SET(SMBUS_TMR_STD_SH) 168 | SMBUS_TMR_SU_SET(SMBUS_TMR_STD_SU) 169 | SMBUS_TMR_CL_SET(SMBUS_TMR_STD_CL) 170 | SMBUS_TMR_CH_SET(SMBUS_TMR_STD_CH); 171 ausmbus_reg_write(sc, AUPSC_SMBTMR, v); 172 173 /* Setup SMBus Mask register */ 174 v = SMBUS_MSK_ALLMASK; 175 ausmbus_reg_write(sc, AUPSC_SMBMSK, v); 176 177 /* SMBus Enable */ 178 v = ausmbus_reg_read(sc, AUPSC_SMBCFG); 179 v |= SMBUS_CFG_DE; 180 ausmbus_reg_write(sc, AUPSC_SMBCFG, v); 181 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 182 if ((v & SMBUS_STAT_SR) == 0) { 183 /* SMBus is not ready */ 184 return -1; 185 } 186 187 #ifdef AUSMBUS_PSC_DEBUG 188 aprint_normal("AuSMBus enabled.\n"); 189 aprint_normal("AuSMBus smbconfig: 0x%08x\n", 190 ausmbus_reg_read(sc, AUPSC_SMBCFG)); 191 aprint_normal("AuSMBus smbstatus: 0x%08x\n", 192 ausmbus_reg_read(sc, AUPSC_SMBSTAT)); 193 aprint_normal("AuSMBus smbtmr : 0x%08x\n", 194 ausmbus_reg_read(sc, AUPSC_SMBTMR)); 195 aprint_normal("AuSMBus smbmask : 0x%08x\n", 196 ausmbus_reg_read(sc, AUPSC_SMBMSK)); 197 #endif 198 199 return 0; 200 } 201 202 static void 203 ausmbus_release_bus(void *arg, int flags) 204 { 205 struct ausmbus_softc *sc = arg; 206 207 ausmbus_reg_write(sc, AUPSC_SMBCFG, 0); 208 sc->sc_ctrl.psc_disable(sc); 209 210 return; 211 } 212 213 static int 214 ausmbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd, 215 size_t cmdlen, void *vbuf, size_t buflen, int flags) 216 { 217 struct ausmbus_softc *sc = (struct ausmbus_softc *)cookie; 218 const uint8_t *cmd = vcmd; 219 220 sc->sc_smbus_slave_addr = addr; 221 222 /* Receive byte */ 223 if ((I2C_OP_READ_P(op)) && (cmdlen == 0) && (buflen == 1)) { 224 return ausmbus_receive_1(sc, (uint8_t *)vbuf); 225 } 226 227 /* Read byte */ 228 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 229 return ausmbus_read_1(sc, *cmd, (uint8_t *)vbuf); 230 } 231 232 /* Read word */ 233 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 2)) { 234 return ausmbus_read_2(sc, *cmd, (uint16_t *)vbuf); 235 } 236 237 /* Send byte */ 238 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) { 239 return ausmbus_send_1(sc, *((uint8_t *)vbuf)); 240 } 241 242 /* Write byte */ 243 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 244 return ausmbus_write_1(sc, *cmd, *((uint8_t *)vbuf)); 245 } 246 247 /* Write word */ 248 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 2)) { 249 return ausmbus_write_2(sc, *cmd, *((uint16_t *)vbuf)); 250 } 251 252 /* 253 * XXX: TODO Please Support other protocols defined in SMBus 2.0 254 * - Quick Command 255 * - Process call 256 * - Block write/read 257 * - Clock write-block read process cal 258 * - SMBus host notify protocol 259 */ 260 261 return -1; 262 } 263 264 static int 265 ausmbus_receive_1(struct ausmbus_softc *sc, uint8_t *vp) 266 { 267 int error; 268 269 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 270 if (error != 0) { 271 return error; 272 } 273 error = ausmbus_read_byte(sc, vp, I2C_F_STOP); 274 if (error != 0) { 275 return error; 276 } 277 278 return 0; 279 } 280 281 static int 282 ausmbus_read_1(struct ausmbus_softc *sc, uint8_t cmd, uint8_t *vp) 283 { 284 int error; 285 286 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 287 if (error != 0) { 288 return error; 289 } 290 291 error = ausmbus_write_byte(sc, cmd, I2C_F_READ); 292 if (error != 0) { 293 return error; 294 } 295 296 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 297 if (error != 0) { 298 return error; 299 } 300 301 error = ausmbus_read_byte(sc, vp, I2C_F_STOP); 302 if (error != 0) { 303 return error; 304 } 305 306 return 0; 307 } 308 309 static int 310 ausmbus_read_2(struct ausmbus_softc *sc, uint8_t cmd, uint16_t *vp) 311 { 312 int error; 313 uint8_t high, low; 314 315 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 316 if (error != 0) { 317 return error; 318 } 319 320 error = ausmbus_write_byte(sc, cmd, I2C_F_READ); 321 if (error != 0) { 322 return error; 323 } 324 325 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_READ); 326 if (error != 0) { 327 return error; 328 } 329 330 error = ausmbus_read_byte(sc, &low, 0); 331 if (error != 0) { 332 return error; 333 } 334 335 error = ausmbus_read_byte(sc, &high, I2C_F_STOP); 336 if (error != 0) { 337 return error; 338 } 339 340 *vp = (high << 8) | low; 341 342 return 0; 343 } 344 345 static int 346 ausmbus_send_1(struct ausmbus_softc *sc, uint8_t val) 347 { 348 int error; 349 350 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 351 if (error != 0) { 352 return error; 353 } 354 355 error = ausmbus_write_byte(sc, val, I2C_F_STOP); 356 if (error != 0) { 357 return error; 358 } 359 360 return 0; 361 } 362 363 static int 364 ausmbus_write_1(struct ausmbus_softc *sc, uint8_t cmd, uint8_t val) 365 { 366 int error; 367 368 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 369 if (error != 0) { 370 return error; 371 } 372 373 error = ausmbus_write_byte(sc, cmd, 0); 374 if (error != 0) { 375 return error; 376 } 377 378 error = ausmbus_write_byte(sc, val, I2C_F_STOP); 379 if (error != 0) { 380 return error; 381 } 382 383 return 0; 384 } 385 386 static int 387 ausmbus_write_2(struct ausmbus_softc *sc, uint8_t cmd, uint16_t val) 388 { 389 int error; 390 uint8_t high, low; 391 392 high = (val >> 8) & 0xff; 393 low = val & 0xff; 394 395 error = ausmbus_initiate_xfer(sc, sc->sc_smbus_slave_addr, I2C_F_WRITE); 396 if (error != 0) { 397 return error; 398 } 399 400 error = ausmbus_write_byte(sc, cmd, 0); 401 if (error != 0) { 402 return error; 403 } 404 405 error = ausmbus_write_byte(sc, low, 0); 406 if (error != 0) { 407 return error; 408 } 409 410 error = ausmbus_write_byte(sc, high, I2C_F_STOP); 411 if (error != 0) { 412 return error; 413 } 414 415 return 0; 416 } 417 418 static int 419 ausmbus_wait_mastertx(struct ausmbus_softc *sc) 420 { 421 uint32_t v; 422 int timeout; 423 int txerr = 0; 424 425 timeout = sc->sc_smbus_timeout; 426 427 do { 428 v = ausmbus_reg_read(sc, AUPSC_SMBEVNT); 429 #ifdef AUSMBUS_PSC_DEBUG 430 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): psc_smbevnt=0x%08x\n", v); 431 #endif 432 if ((v & SMBUS_EVNT_TU) != 0) 433 break; 434 if ((v & SMBUS_EVNT_MD) != 0) 435 break; 436 if ((v & (SMBUS_EVNT_DN | SMBUS_EVNT_AN | SMBUS_EVNT_AL)) 437 != 0) { 438 txerr = 1; 439 break; 440 } 441 timeout--; 442 delay(1); 443 } while (timeout > 0); 444 445 if (txerr != 0) { 446 ausmbus_reg_write(sc, AUPSC_SMBEVNT, 447 SMBUS_EVNT_DN | SMBUS_EVNT_AN | SMBUS_EVNT_AL); 448 #ifdef AUSMBUS_PSC_DEBUG 449 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): Tx error\n"); 450 #endif 451 return -1; 452 } 453 454 /* Reset Event TU (Tx Underflow) */ 455 ausmbus_reg_write(sc, AUPSC_SMBEVNT, SMBUS_EVNT_TU | SMBUS_EVNT_MD); 456 457 #ifdef AUSMBUS_PSC_DEBUG 458 v = ausmbus_reg_read(sc, AUPSC_SMBEVNT); 459 aprint_normal("AuSMBus: ausmbus_wait_mastertx(): psc_smbevnt=0x%08x (reset)\n", v); 460 #endif 461 return 0; 462 } 463 464 static int 465 ausmbus_wait_masterrx(struct ausmbus_softc *sc) 466 { 467 uint32_t v; 468 int timeout; 469 timeout = sc->sc_smbus_timeout; 470 471 if (ausmbus_wait_mastertx(sc) != 0) 472 return -1; 473 474 do { 475 v = ausmbus_reg_read(sc, AUPSC_SMBSTAT); 476 #ifdef AUSMBUS_PSC_DEBUG 477 aprint_normal("AuSMBus: ausmbus_wait_masterrx(): psc_smbstat=0x%08x\n", v); 478 #endif 479 if ((v & SMBUS_STAT_RE) == 0) 480 break; 481 timeout--; 482 delay(1); 483 } while (timeout > 0); 484 485 return 0; 486 } 487 488 static int 489 ausmbus_initiate_xfer(void *arg, i2c_addr_t addr, int flags) 490 { 491 struct ausmbus_softc *sc = arg; 492 uint32_t v; 493 494 /* Tx/Rx Slave Address */ 495 v = (addr << 1) & SMBUS_TXRX_ADDRDATA; 496 if ((flags & I2C_F_READ) != 0) 497 v |= 1; 498 ausmbus_reg_write(sc, AUPSC_SMBTXRX, v); 499 500 /* Master Start */ 501 ausmbus_reg_write(sc, AUPSC_SMBPCR, SMBUS_PCR_MS); 502 503 if (ausmbus_wait_mastertx(sc) != 0) 504 return -1; 505 506 return 0; 507 } 508 509 static int 510 ausmbus_read_byte(void *arg, uint8_t *vp, int flags) 511 { 512 struct ausmbus_softc *sc = arg; 513 uint32_t v; 514 515 if ((flags & I2C_F_STOP) != 0) { 516 ausmbus_reg_write(sc, AUPSC_SMBTXRX, SMBUS_TXRX_STP); 517 } else { 518 ausmbus_reg_write(sc, AUPSC_SMBTXRX, 0); 519 } 520 521 if (ausmbus_wait_masterrx(sc) != 0) 522 return -1; 523 524 v = ausmbus_reg_read(sc, AUPSC_SMBTXRX); 525 *vp = v & SMBUS_TXRX_ADDRDATA; 526 527 return 0; 528 } 529 530 static int 531 ausmbus_write_byte(void *arg, uint8_t v, int flags) 532 { 533 struct ausmbus_softc *sc = arg; 534 535 if ((flags & I2C_F_STOP) != 0) { 536 ausmbus_reg_write(sc, AUPSC_SMBTXRX, (v | SMBUS_TXRX_STP)); 537 } else if ((flags & I2C_F_READ) != 0) { 538 ausmbus_reg_write(sc, AUPSC_SMBTXRX, (v | SMBUS_TXRX_RSR)); 539 } else { 540 ausmbus_reg_write(sc, AUPSC_SMBTXRX, v); 541 } 542 543 if (ausmbus_wait_mastertx(sc) != 0) 544 return -1; 545 546 return 0; 547 } 548
Indexes created Sat Oct 04 05:10:05 GMT 2025