1 1.2 gdamore /* $NetBSD: com_aubus_reg.h,v 1.2 2006/07/13 22:56:01 gdamore Exp $ */ 2 1.2 gdamore 3 1.2 gdamore /* copyright */ 4 1.2 gdamore 5 1.2 gdamore #undef COM_FREQ /* relative to CPU clock speed on Au1X00 */ 6 1.2 gdamore 7 1.2 gdamore /* 8 1.2 gdamore * Alchemy Semi Au1X00 UART registers 9 1.2 gdamore */ 10 1.2 gdamore 11 1.2 gdamore #define AUCOM_RXDATA 0x00 /* receive data register (R) */ 12 1.2 gdamore #define AUCOM_TXDATA 0x04 /* transmit data register (W) */ 13 1.2 gdamore #define AUCOM_IER 0x08 /* interrupt enable (R/W) */ 14 1.2 gdamore #define AUCOM_IIR 0x0c /* interrupt identification (R) */ 15 1.2 gdamore #define AUCOM_FIFO 0x10 /* FIFO control (R/W) */ 16 1.2 gdamore #define AUCOM_LCTL 0x14 /* line control register (R/W) */ 17 1.2 gdamore #define AUCOM_CFCR 0x14 /* line control register (R/W) */ 18 1.2 gdamore #define AUCOM_MCR 0x18 /* modem control register (R/W) */ 19 1.2 gdamore #define AUCOM_LSR 0x1c /* line status register (R) */ 20 1.2 gdamore #define AUCOM_MSR 0x20 /* modem status register (R) */ 21 1.2 gdamore #define AUCOM_DLB 0x28 /* divisor latch (16bit) (R/W) */ 22 1.2 gdamore #define AUCOM_MODCTL 0x100 /* module control register (R/W) */ 23 1.2 gdamore 24 1.2 gdamore #define UMC_CE 0x2 /* module clock enable */ 25 1.2 gdamore #define UMC_ME 0x1 /* module enable */ 26 1.2 gdamore 27 1.2 gdamore #define AUCOM_NPORTS 0x104 28
Indexes created Sun Sep 28 12:09:53 GMT 2025