if_aumac.c revision 1.2.2.3
1 1.2.2.3 thorpej /* $NetBSD: if_aumac.c,v 1.2.2.3 2003/01/17 16:06:23 thorpej Exp $ */ 2 1.2.2.2 nathanw 3 1.2.2.2 nathanw /* 4 1.2.2.2 nathanw * Copyright (c) 2001 Wasabi Systems, Inc. 5 1.2.2.2 nathanw * All rights reserved. 6 1.2.2.2 nathanw * 7 1.2.2.2 nathanw * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 1.2.2.2 nathanw * 9 1.2.2.2 nathanw * Redistribution and use in source and binary forms, with or without 10 1.2.2.2 nathanw * modification, are permitted provided that the following conditions 11 1.2.2.2 nathanw * are met: 12 1.2.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 13 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer. 14 1.2.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 16 1.2.2.2 nathanw * documentation and/or other materials provided with the distribution. 17 1.2.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 18 1.2.2.2 nathanw * must display the following acknowledgement: 19 1.2.2.2 nathanw * This product includes software developed for the NetBSD Project by 20 1.2.2.2 nathanw * Wasabi Systems, Inc. 21 1.2.2.2 nathanw * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 1.2.2.2 nathanw * or promote products derived from this software without specific prior 23 1.2.2.2 nathanw * written permission. 24 1.2.2.2 nathanw * 25 1.2.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 1.2.2.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.2.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.2.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 1.2.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.2.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.2.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.2.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.2.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.2.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.2.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 36 1.2.2.2 nathanw */ 37 1.2.2.2 nathanw 38 1.2.2.2 nathanw /* 39 1.2.2.2 nathanw * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 1.2.2.2 nathanw * Access Controller. 41 1.2.2.2 nathanw * 42 1.2.2.2 nathanw * TODO: 43 1.2.2.2 nathanw * 44 1.2.2.2 nathanw * Better Rx buffer management; we want to get new Rx buffers 45 1.2.2.2 nathanw * to the chip more quickly than we currently do. 46 1.2.2.2 nathanw */ 47 1.2.2.2 nathanw 48 1.2.2.2 nathanw #include <sys/cdefs.h> 49 1.2.2.3 thorpej __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.2.2.3 2003/01/17 16:06:23 thorpej Exp $"); 50 1.2.2.2 nathanw 51 1.2.2.2 nathanw #include "bpfilter.h" 52 1.2.2.2 nathanw 53 1.2.2.2 nathanw #include <sys/param.h> 54 1.2.2.2 nathanw #include <sys/systm.h> 55 1.2.2.2 nathanw #include <sys/callout.h> 56 1.2.2.2 nathanw #include <sys/mbuf.h> 57 1.2.2.2 nathanw #include <sys/malloc.h> 58 1.2.2.2 nathanw #include <sys/kernel.h> 59 1.2.2.2 nathanw #include <sys/socket.h> 60 1.2.2.2 nathanw #include <sys/ioctl.h> 61 1.2.2.2 nathanw #include <sys/errno.h> 62 1.2.2.2 nathanw #include <sys/device.h> 63 1.2.2.2 nathanw #include <sys/queue.h> 64 1.2.2.2 nathanw 65 1.2.2.2 nathanw #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 66 1.2.2.2 nathanw 67 1.2.2.2 nathanw #include <net/if.h> 68 1.2.2.2 nathanw #include <net/if_dl.h> 69 1.2.2.2 nathanw #include <net/if_media.h> 70 1.2.2.2 nathanw #include <net/if_ether.h> 71 1.2.2.2 nathanw 72 1.2.2.2 nathanw #if NBPFILTER > 0 73 1.2.2.2 nathanw #include <net/bpf.h> 74 1.2.2.2 nathanw #endif 75 1.2.2.2 nathanw 76 1.2.2.2 nathanw #include <machine/bus.h> 77 1.2.2.2 nathanw #include <machine/intr.h> 78 1.2.2.2 nathanw #include <machine/endian.h> 79 1.2.2.2 nathanw 80 1.2.2.2 nathanw #include <dev/mii/mii.h> 81 1.2.2.2 nathanw #include <dev/mii/miivar.h> 82 1.2.2.2 nathanw 83 1.2.2.2 nathanw #include <mips/alchemy/include/aureg.h> 84 1.2.2.2 nathanw #include <mips/alchemy/include/auvar.h> 85 1.2.2.2 nathanw #include <mips/alchemy/include/aubusvar.h> 86 1.2.2.2 nathanw #include <mips/alchemy/dev/if_aumacreg.h> 87 1.2.2.2 nathanw 88 1.2.2.2 nathanw /* 89 1.2.2.2 nathanw * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 90 1.2.2.2 nathanw * must consist of a single DMA segment, and must be aligned to a 2K 91 1.2.2.2 nathanw * boundary. Therefore, this driver does not perform DMA directly 92 1.2.2.2 nathanw * to/from mbufs. Instead, we copy the data to/from buffers allocated 93 1.2.2.2 nathanw * at device attach time. 94 1.2.2.2 nathanw * 95 1.2.2.2 nathanw * We also skip the bus_dma dance. The MAC is built in to the CPU, so 96 1.2.2.2 nathanw * there's little point in not making assumptions based on the CPU type. 97 1.2.2.2 nathanw * We also program the Au1X00 cache to be DMA coherent, so the buffers 98 1.2.2.2 nathanw * are accessed via KSEG0 addresses. 99 1.2.2.2 nathanw */ 100 1.2.2.2 nathanw #define AUMAC_NTXDESC 4 101 1.2.2.2 nathanw #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 102 1.2.2.2 nathanw 103 1.2.2.2 nathanw #define AUMAC_NRXDESC 4 104 1.2.2.2 nathanw #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 105 1.2.2.2 nathanw 106 1.2.2.2 nathanw #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 107 1.2.2.2 nathanw #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 108 1.2.2.2 nathanw 109 1.2.2.2 nathanw #define AUMAC_TXBUF_OFFSET 0 110 1.2.2.2 nathanw #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 111 1.2.2.2 nathanw #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 112 1.2.2.2 nathanw 113 1.2.2.2 nathanw struct aumac_buf { 114 1.2.2.2 nathanw caddr_t buf_vaddr; /* virtual address of buffer */ 115 1.2.2.2 nathanw bus_addr_t buf_paddr; /* DMA address of buffer */ 116 1.2.2.2 nathanw }; 117 1.2.2.2 nathanw 118 1.2.2.2 nathanw /* 119 1.2.2.2 nathanw * Software state per device. 120 1.2.2.2 nathanw */ 121 1.2.2.2 nathanw struct aumac_softc { 122 1.2.2.2 nathanw struct device sc_dev; /* generic device information */ 123 1.2.2.2 nathanw bus_space_tag_t sc_st; /* bus space tag */ 124 1.2.2.2 nathanw bus_space_handle_t sc_mac_sh; /* MAC space handle */ 125 1.2.2.2 nathanw bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 126 1.2.2.2 nathanw bus_space_handle_t sc_dma_sh; /* DMA space handle */ 127 1.2.2.2 nathanw struct ethercom sc_ethercom; /* Ethernet common data */ 128 1.2.2.2 nathanw void *sc_sdhook; /* shutdown hook */ 129 1.2.2.2 nathanw 130 1.2.2.2 nathanw void *sc_ih; /* interrupt cookie */ 131 1.2.2.2 nathanw 132 1.2.2.2 nathanw struct mii_data sc_mii; /* MII/media information */ 133 1.2.2.2 nathanw 134 1.2.2.2 nathanw struct callout sc_tick_ch; /* tick callout */ 135 1.2.2.2 nathanw 136 1.2.2.2 nathanw /* Transmit and receive buffers */ 137 1.2.2.2 nathanw struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 138 1.2.2.2 nathanw struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 139 1.2.2.2 nathanw caddr_t sc_bufaddr; 140 1.2.2.2 nathanw 141 1.2.2.2 nathanw int sc_txfree; /* number of free Tx descriptors */ 142 1.2.2.2 nathanw int sc_txnext; /* next Tx descriptor to use */ 143 1.2.2.2 nathanw int sc_txdirty; /* first dirty Tx descriptor */ 144 1.2.2.2 nathanw 145 1.2.2.2 nathanw int sc_rxptr; /* next ready Rx descriptor */ 146 1.2.2.2 nathanw 147 1.2.2.2 nathanw #ifdef AUMAC_EVENT_COUNTERS 148 1.2.2.2 nathanw struct evcnt sc_ev_txstall; /* Tx stalled */ 149 1.2.2.2 nathanw struct evcnt sc_ev_rxstall; /* Rx stalled */ 150 1.2.2.2 nathanw struct evcnt sc_ev_txintr; /* Tx interrupts */ 151 1.2.2.2 nathanw struct evcnt sc_ev_rxintr; /* Rx interrupts */ 152 1.2.2.2 nathanw #endif 153 1.2.2.2 nathanw 154 1.2.2.2 nathanw uint32_t sc_control; /* MAC_CONTROL contents */ 155 1.2.2.2 nathanw uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 156 1.2.2.2 nathanw }; 157 1.2.2.2 nathanw 158 1.2.2.2 nathanw #ifdef AUMAC_EVENT_COUNTERS 159 1.2.2.2 nathanw #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 160 1.2.2.3 thorpej #else 161 1.2.2.3 thorpej #define AUMAC_EVCNT_INCR(ev) /* nothing */ 162 1.2.2.2 nathanw #endif 163 1.2.2.2 nathanw 164 1.2.2.2 nathanw #define AUMAC_INIT_RXDESC(sc, x) \ 165 1.2.2.2 nathanw do { \ 166 1.2.2.2 nathanw bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 167 1.2.2.2 nathanw MACDMA_RX_STAT((x)), 0); \ 168 1.2.2.2 nathanw bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 169 1.2.2.2 nathanw MACDMA_RX_ADDR((x)), \ 170 1.2.2.2 nathanw (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 171 1.2.2.2 nathanw } while (/*CONSTCOND*/0) 172 1.2.2.2 nathanw 173 1.2.2.2 nathanw static void aumac_start(struct ifnet *); 174 1.2.2.2 nathanw static void aumac_watchdog(struct ifnet *); 175 1.2.2.2 nathanw static int aumac_ioctl(struct ifnet *, u_long, caddr_t); 176 1.2.2.2 nathanw static int aumac_init(struct ifnet *); 177 1.2.2.2 nathanw static void aumac_stop(struct ifnet *, int); 178 1.2.2.2 nathanw 179 1.2.2.2 nathanw static void aumac_shutdown(void *); 180 1.2.2.2 nathanw 181 1.2.2.2 nathanw static void aumac_tick(void *); 182 1.2.2.2 nathanw 183 1.2.2.2 nathanw static void aumac_set_filter(struct aumac_softc *); 184 1.2.2.2 nathanw 185 1.2.2.2 nathanw static void aumac_powerup(struct aumac_softc *); 186 1.2.2.2 nathanw static void aumac_powerdown(struct aumac_softc *); 187 1.2.2.2 nathanw 188 1.2.2.2 nathanw static int aumac_intr(void *); 189 1.2.2.2 nathanw static void aumac_txintr(struct aumac_softc *); 190 1.2.2.2 nathanw static void aumac_rxintr(struct aumac_softc *); 191 1.2.2.2 nathanw 192 1.2.2.2 nathanw static int aumac_mii_readreg(struct device *, int, int); 193 1.2.2.2 nathanw static void aumac_mii_writereg(struct device *, int, int, int); 194 1.2.2.2 nathanw static void aumac_mii_statchg(struct device *); 195 1.2.2.2 nathanw static int aumac_mii_wait(struct aumac_softc *, const char *); 196 1.2.2.2 nathanw 197 1.2.2.2 nathanw static int aumac_mediachange(struct ifnet *); 198 1.2.2.2 nathanw static void aumac_mediastatus(struct ifnet *, struct ifmediareq *); 199 1.2.2.2 nathanw 200 1.2.2.2 nathanw static int aumac_match(struct device *, struct cfdata *, void *); 201 1.2.2.2 nathanw static void aumac_attach(struct device *, struct device *, void *); 202 1.2.2.2 nathanw 203 1.2.2.2 nathanw int aumac_copy_small = 0; 204 1.2.2.2 nathanw 205 1.2.2.2 nathanw CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 206 1.2.2.2 nathanw aumac_match, aumac_attach, NULL, NULL); 207 1.2.2.2 nathanw 208 1.2.2.2 nathanw static int 209 1.2.2.2 nathanw aumac_match(struct device *parent, struct cfdata *cf, void *aux) 210 1.2.2.2 nathanw { 211 1.2.2.2 nathanw struct aubus_attach_args *aa = aux; 212 1.2.2.2 nathanw 213 1.2.2.2 nathanw if (strcmp(aa->aa_name, cf->cf_name) == 0) 214 1.2.2.2 nathanw return (1); 215 1.2.2.2 nathanw 216 1.2.2.2 nathanw return (0); 217 1.2.2.2 nathanw } 218 1.2.2.2 nathanw 219 1.2.2.2 nathanw static void 220 1.2.2.2 nathanw aumac_attach(struct device *parent, struct device *self, void *aux) 221 1.2.2.2 nathanw { 222 1.2.2.2 nathanw char prop_name[sizeof("0xffffffff:mac-addr") + 1]; 223 1.2.2.2 nathanw uint8_t enaddr[ETHER_ADDR_LEN]; 224 1.2.2.2 nathanw struct aumac_softc *sc = (void *) self; 225 1.2.2.2 nathanw struct aubus_attach_args *aa = aux; 226 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 227 1.2.2.2 nathanw struct pglist pglist; 228 1.2.2.2 nathanw paddr_t bufaddr; 229 1.2.2.2 nathanw caddr_t vbufaddr; 230 1.2.2.2 nathanw int i; 231 1.2.2.2 nathanw 232 1.2.2.2 nathanw callout_init(&sc->sc_tick_ch); 233 1.2.2.2 nathanw 234 1.2.2.2 nathanw printf(": Au1X00 10/100 Ethernet\n"); 235 1.2.2.2 nathanw 236 1.2.2.2 nathanw sc->sc_st = aa->aa_st; 237 1.2.2.2 nathanw 238 1.2.2.2 nathanw /* Get the MAC address. */ 239 1.2.2.2 nathanw snprintf(prop_name, sizeof(prop_name), "%p:mac-addr", self); 240 1.2.2.2 nathanw if (alchemy_info_get(prop_name, enaddr, sizeof(enaddr)) == -1) { 241 1.2.2.2 nathanw printf("%s: unable to determine MAC address\n", 242 1.2.2.2 nathanw sc->sc_dev.dv_xname); 243 1.2.2.2 nathanw return; 244 1.2.2.2 nathanw } 245 1.2.2.2 nathanw 246 1.2.2.2 nathanw printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 247 1.2.2.2 nathanw ether_sprintf(enaddr)); 248 1.2.2.2 nathanw 249 1.2.2.2 nathanw /* Map the device. */ 250 1.2.2.2 nathanw if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 251 1.2.2.2 nathanw MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 252 1.2.2.2 nathanw printf("%s: unable to map MAC registers\n", 253 1.2.2.2 nathanw sc->sc_dev.dv_xname); 254 1.2.2.2 nathanw return; 255 1.2.2.2 nathanw } 256 1.2.2.2 nathanw if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 257 1.2.2.2 nathanw MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 258 1.2.2.2 nathanw printf("%s: unable to map MACEN registers\n", 259 1.2.2.2 nathanw sc->sc_dev.dv_xname); 260 1.2.2.2 nathanw return; 261 1.2.2.2 nathanw } 262 1.2.2.2 nathanw if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 263 1.2.2.2 nathanw MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 264 1.2.2.2 nathanw printf("%s: unable to map MACDMA registers\n", 265 1.2.2.2 nathanw sc->sc_dev.dv_xname); 266 1.2.2.2 nathanw return; 267 1.2.2.2 nathanw } 268 1.2.2.2 nathanw 269 1.2.2.2 nathanw /* Make sure the MAC is powered off. */ 270 1.2.2.2 nathanw aumac_powerdown(sc); 271 1.2.2.2 nathanw 272 1.2.2.2 nathanw /* Hook up the interrupt handler. */ 273 1.2.2.2 nathanw sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 274 1.2.2.2 nathanw aumac_intr, sc); 275 1.2.2.2 nathanw if (sc->sc_ih == NULL) { 276 1.2.2.2 nathanw printf("%s: unable to register interrupt handler\n", 277 1.2.2.2 nathanw sc->sc_dev.dv_xname); 278 1.2.2.2 nathanw return; 279 1.2.2.2 nathanw } 280 1.2.2.2 nathanw 281 1.2.2.2 nathanw /* 282 1.2.2.2 nathanw * Allocate space for the transmit and receive buffers. 283 1.2.2.2 nathanw */ 284 1.2.2.2 nathanw if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 285 1.2.2.2 nathanw &pglist, 1, 0)) 286 1.2.2.2 nathanw return; 287 1.2.2.2 nathanw 288 1.2.2.2 nathanw bufaddr = TAILQ_FIRST(&pglist)->phys_addr; 289 1.2.2.2 nathanw vbufaddr = (void *)MIPS_PHYS_TO_KSEG0(bufaddr); 290 1.2.2.2 nathanw 291 1.2.2.2 nathanw for (i = 0; i < AUMAC_NTXDESC; i++) { 292 1.2.2.2 nathanw int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 293 1.2.2.2 nathanw 294 1.2.2.2 nathanw sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 295 1.2.2.2 nathanw sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 296 1.2.2.2 nathanw } 297 1.2.2.2 nathanw 298 1.2.2.2 nathanw for (i = 0; i < AUMAC_NRXDESC; i++) { 299 1.2.2.2 nathanw int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 300 1.2.2.2 nathanw 301 1.2.2.2 nathanw sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 302 1.2.2.2 nathanw sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 303 1.2.2.2 nathanw } 304 1.2.2.2 nathanw 305 1.2.2.2 nathanw /* 306 1.2.2.2 nathanw * Power up the MAC before accessing any MAC registers (including 307 1.2.2.2 nathanw * MII configuration. 308 1.2.2.2 nathanw */ 309 1.2.2.2 nathanw aumac_powerup(sc); 310 1.2.2.2 nathanw 311 1.2.2.2 nathanw /* 312 1.2.2.2 nathanw * Initialize the media structures and probe the MII. 313 1.2.2.2 nathanw */ 314 1.2.2.2 nathanw sc->sc_mii.mii_ifp = ifp; 315 1.2.2.2 nathanw sc->sc_mii.mii_readreg = aumac_mii_readreg; 316 1.2.2.2 nathanw sc->sc_mii.mii_writereg = aumac_mii_writereg; 317 1.2.2.2 nathanw sc->sc_mii.mii_statchg = aumac_mii_statchg; 318 1.2.2.2 nathanw ifmedia_init(&sc->sc_mii.mii_media, 0, aumac_mediachange, 319 1.2.2.2 nathanw aumac_mediastatus); 320 1.2.2.2 nathanw 321 1.2.2.2 nathanw mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 322 1.2.2.2 nathanw MII_OFFSET_ANY, 0); 323 1.2.2.2 nathanw 324 1.2.2.2 nathanw if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 325 1.2.2.2 nathanw ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 326 1.2.2.2 nathanw ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 327 1.2.2.2 nathanw } else 328 1.2.2.2 nathanw ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 329 1.2.2.2 nathanw 330 1.2.2.2 nathanw strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 331 1.2.2.2 nathanw ifp->if_softc = sc; 332 1.2.2.2 nathanw ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 333 1.2.2.2 nathanw ifp->if_ioctl = aumac_ioctl; 334 1.2.2.2 nathanw ifp->if_start = aumac_start; 335 1.2.2.2 nathanw ifp->if_watchdog = aumac_watchdog; 336 1.2.2.2 nathanw ifp->if_init = aumac_init; 337 1.2.2.2 nathanw ifp->if_stop = aumac_stop; 338 1.2.2.2 nathanw IFQ_SET_READY(&ifp->if_snd); 339 1.2.2.2 nathanw 340 1.2.2.2 nathanw /* Attach the interface. */ 341 1.2.2.2 nathanw if_attach(ifp); 342 1.2.2.2 nathanw ether_ifattach(ifp, enaddr); 343 1.2.2.2 nathanw 344 1.2.2.2 nathanw #ifdef AUMAC_EVENT_COUNTERS 345 1.2.2.2 nathanw evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 346 1.2.2.2 nathanw NULL, sc->sc_dev.dv_xname, "txstall"); 347 1.2.2.2 nathanw evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 348 1.2.2.2 nathanw NULL, sc->sc_dev.dv_xname, "rxstall"); 349 1.2.2.2 nathanw evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 350 1.2.2.2 nathanw NULL, sc->sc_dev.dv_xname, "txintr"); 351 1.2.2.2 nathanw evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 352 1.2.2.2 nathanw NULL, sc->sc_dev.dv_xname, "txintr"); 353 1.2.2.2 nathanw #endif 354 1.2.2.2 nathanw 355 1.2.2.2 nathanw /* Make sure the interface is shutdown during reboot. */ 356 1.2.2.2 nathanw sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 357 1.2.2.2 nathanw if (sc->sc_sdhook == NULL) 358 1.2.2.2 nathanw printf("%s: WARNING: unable to establish shutdown hook\n", 359 1.2.2.2 nathanw sc->sc_dev.dv_xname); 360 1.2.2.2 nathanw return; 361 1.2.2.2 nathanw } 362 1.2.2.2 nathanw 363 1.2.2.2 nathanw /* 364 1.2.2.2 nathanw * aumac_shutdown: 365 1.2.2.2 nathanw * 366 1.2.2.2 nathanw * Make sure the interface is stopped at reboot time. 367 1.2.2.2 nathanw */ 368 1.2.2.2 nathanw static void 369 1.2.2.2 nathanw aumac_shutdown(void *arg) 370 1.2.2.2 nathanw { 371 1.2.2.2 nathanw struct aumac_softc *sc = arg; 372 1.2.2.2 nathanw 373 1.2.2.2 nathanw aumac_stop(&sc->sc_ethercom.ec_if, 1); 374 1.2.2.2 nathanw 375 1.2.2.2 nathanw /* 376 1.2.2.2 nathanw * XXX aumac_stop leaves device powered up at the moment 377 1.2.2.2 nathanw * XXX but this still isn't enough to keep yamon happy... :-( 378 1.2.2.2 nathanw */ 379 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 380 1.2.2.2 nathanw } 381 1.2.2.2 nathanw 382 1.2.2.2 nathanw /* 383 1.2.2.2 nathanw * aumac_start: [ifnet interface function] 384 1.2.2.2 nathanw * 385 1.2.2.2 nathanw * Start packet transmission on the interface. 386 1.2.2.2 nathanw */ 387 1.2.2.2 nathanw static void 388 1.2.2.2 nathanw aumac_start(struct ifnet *ifp) 389 1.2.2.2 nathanw { 390 1.2.2.2 nathanw struct aumac_softc *sc = ifp->if_softc; 391 1.2.2.2 nathanw struct mbuf *m; 392 1.2.2.2 nathanw int nexttx; 393 1.2.2.2 nathanw 394 1.2.2.2 nathanw if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 395 1.2.2.2 nathanw return; 396 1.2.2.2 nathanw 397 1.2.2.2 nathanw /* 398 1.2.2.2 nathanw * Loop through the send queue, setting up transmit descriptors 399 1.2.2.2 nathanw * unitl we drain the queue, or use up all available transmit 400 1.2.2.2 nathanw * descriptors. 401 1.2.2.2 nathanw */ 402 1.2.2.2 nathanw for (;;) { 403 1.2.2.2 nathanw /* Grab a packet off the queue. */ 404 1.2.2.2 nathanw IFQ_POLL(&ifp->if_snd, m); 405 1.2.2.2 nathanw if (m == NULL) 406 1.2.2.2 nathanw return; 407 1.2.2.2 nathanw 408 1.2.2.2 nathanw /* Get a spare descriptor. */ 409 1.2.2.2 nathanw if (sc->sc_txfree == 0) { 410 1.2.2.2 nathanw /* No more slots left; notify upper layer. */ 411 1.2.2.2 nathanw ifp->if_flags |= IFF_OACTIVE; 412 1.2.2.2 nathanw AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 413 1.2.2.2 nathanw return; 414 1.2.2.2 nathanw } 415 1.2.2.2 nathanw nexttx = sc->sc_txnext; 416 1.2.2.2 nathanw 417 1.2.2.2 nathanw IFQ_DEQUEUE(&ifp->if_snd, m); 418 1.2.2.2 nathanw 419 1.2.2.2 nathanw /* 420 1.2.2.2 nathanw * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 421 1.2.2.2 nathanw */ 422 1.2.2.2 nathanw 423 1.2.2.2 nathanw m_copydata(m, 0, m->m_pkthdr.len, 424 1.2.2.2 nathanw sc->sc_txbufs[nexttx].buf_vaddr); 425 1.2.2.2 nathanw 426 1.2.2.3 thorpej /* Zero out the remainder of any short packets. */ 427 1.2.2.3 thorpej if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 428 1.2.2.3 thorpej memset(sc->sc_txbufs[nexttx].buf_vaddr + 429 1.2.2.3 thorpej m->m_pkthdr.len, 0, 430 1.2.2.3 thorpej ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 431 1.2.2.3 thorpej 432 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 433 1.2.2.2 nathanw MACDMA_TX_STAT(nexttx), 0); 434 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 435 1.2.2.2 nathanw MACDMA_TX_LEN(nexttx), 436 1.2.2.2 nathanw m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 437 1.2.2.2 nathanw ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 438 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 439 1.2.2.2 nathanw MACDMA_TX_ADDR(nexttx), 440 1.2.2.2 nathanw sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 441 1.2.2.2 nathanw /* XXX - needed?? we should be coherent */ 442 1.2.2.2 nathanw bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 443 1.2.2.2 nathanw 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 444 1.2.2.2 nathanw 445 1.2.2.2 nathanw /* Advance the Tx pointer. */ 446 1.2.2.2 nathanw sc->sc_txfree--; 447 1.2.2.2 nathanw sc->sc_txnext = AUMAC_NEXTTX(nexttx); 448 1.2.2.2 nathanw 449 1.2.2.2 nathanw #if NBPFILTER > 0 450 1.2.2.2 nathanw /* Pass the packet to any BPF listeners. */ 451 1.2.2.2 nathanw if (ifp->if_bpf) 452 1.2.2.2 nathanw bpf_mtap(ifp->if_bpf, m); 453 1.2.2.2 nathanw #endif /* NBPFILTER */ 454 1.2.2.2 nathanw 455 1.2.2.2 nathanw m_freem(m); 456 1.2.2.2 nathanw 457 1.2.2.2 nathanw /* Set a watchdog timer in case the chip flakes out. */ 458 1.2.2.2 nathanw ifp->if_timer = 5; 459 1.2.2.2 nathanw } 460 1.2.2.2 nathanw /* NOTREACHED */ 461 1.2.2.2 nathanw } 462 1.2.2.2 nathanw 463 1.2.2.2 nathanw /* 464 1.2.2.2 nathanw * aumac_watchdog: [ifnet interface function] 465 1.2.2.2 nathanw * 466 1.2.2.2 nathanw * Watchdog timer handler. 467 1.2.2.2 nathanw */ 468 1.2.2.2 nathanw static void 469 1.2.2.2 nathanw aumac_watchdog(struct ifnet *ifp) 470 1.2.2.2 nathanw { 471 1.2.2.2 nathanw struct aumac_softc *sc = ifp->if_softc; 472 1.2.2.2 nathanw 473 1.2.2.2 nathanw printf("%s: device timeout\n", sc->sc_dev.dv_xname); 474 1.2.2.2 nathanw (void) aumac_init(ifp); 475 1.2.2.2 nathanw 476 1.2.2.2 nathanw /* Try to get more packets going. */ 477 1.2.2.2 nathanw aumac_start(ifp); 478 1.2.2.2 nathanw } 479 1.2.2.2 nathanw 480 1.2.2.2 nathanw /* 481 1.2.2.2 nathanw * aumac_ioctl: [ifnet interface function] 482 1.2.2.2 nathanw * 483 1.2.2.2 nathanw * Handle control requests from the operator. 484 1.2.2.2 nathanw */ 485 1.2.2.2 nathanw static int 486 1.2.2.2 nathanw aumac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 487 1.2.2.2 nathanw { 488 1.2.2.2 nathanw struct aumac_softc *sc = ifp->if_softc; 489 1.2.2.2 nathanw struct ifreq *ifr = (struct ifreq *) data; 490 1.2.2.2 nathanw int s, error; 491 1.2.2.2 nathanw 492 1.2.2.2 nathanw s = splnet(); 493 1.2.2.2 nathanw 494 1.2.2.2 nathanw switch (cmd) { 495 1.2.2.2 nathanw case SIOCSIFMEDIA: 496 1.2.2.2 nathanw case SIOCGIFMEDIA: 497 1.2.2.2 nathanw error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 498 1.2.2.2 nathanw break; 499 1.2.2.2 nathanw 500 1.2.2.2 nathanw default: 501 1.2.2.2 nathanw error = ether_ioctl(ifp, cmd, data); 502 1.2.2.2 nathanw if (error == ENETRESET) { 503 1.2.2.2 nathanw /* 504 1.2.2.2 nathanw * Multicast list has changed; set the hardware filter 505 1.2.2.2 nathanw * accordingly. 506 1.2.2.2 nathanw */ 507 1.2.2.2 nathanw aumac_set_filter(sc); 508 1.2.2.2 nathanw } 509 1.2.2.2 nathanw break; 510 1.2.2.2 nathanw } 511 1.2.2.2 nathanw 512 1.2.2.2 nathanw /* Try to get more packets going. */ 513 1.2.2.2 nathanw aumac_start(ifp); 514 1.2.2.2 nathanw 515 1.2.2.2 nathanw splx(s); 516 1.2.2.2 nathanw return (error); 517 1.2.2.2 nathanw } 518 1.2.2.2 nathanw 519 1.2.2.2 nathanw /* 520 1.2.2.2 nathanw * aumac_intr: 521 1.2.2.2 nathanw * 522 1.2.2.2 nathanw * Interrupt service routine. 523 1.2.2.2 nathanw */ 524 1.2.2.2 nathanw static int 525 1.2.2.2 nathanw aumac_intr(void *arg) 526 1.2.2.2 nathanw { 527 1.2.2.2 nathanw struct aumac_softc *sc = arg; 528 1.2.2.2 nathanw 529 1.2.2.2 nathanw /* 530 1.2.2.2 nathanw * There aren't really any interrupt status bits on the 531 1.2.2.2 nathanw * Au1X00 MAC, and each MAC has a dedicated interrupt 532 1.2.2.2 nathanw * in the CPU's built-in interrupt controller. Just 533 1.2.2.2 nathanw * check for new incoming packets, and then Tx completions 534 1.2.2.2 nathanw * (for status updating). 535 1.2.2.2 nathanw */ 536 1.2.2.2 nathanw if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 537 1.2.2.2 nathanw return (0); 538 1.2.2.2 nathanw 539 1.2.2.2 nathanw aumac_rxintr(sc); 540 1.2.2.2 nathanw aumac_txintr(sc); 541 1.2.2.2 nathanw 542 1.2.2.2 nathanw return (1); 543 1.2.2.2 nathanw } 544 1.2.2.2 nathanw 545 1.2.2.2 nathanw /* 546 1.2.2.2 nathanw * aumac_txintr: 547 1.2.2.2 nathanw * 548 1.2.2.2 nathanw * Helper; handle transmit interrupts. 549 1.2.2.2 nathanw */ 550 1.2.2.2 nathanw static void 551 1.2.2.2 nathanw aumac_txintr(struct aumac_softc *sc) 552 1.2.2.2 nathanw { 553 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 554 1.2.2.2 nathanw uint32_t stat; 555 1.2.2.2 nathanw int i; 556 1.2.2.2 nathanw #ifdef AUMAC_EVENT_COUNTERS 557 1.2.2.2 nathanw int gotone = 0; 558 1.2.2.2 nathanw #endif 559 1.2.2.2 nathanw 560 1.2.2.2 nathanw for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 561 1.2.2.2 nathanw i = AUMAC_NEXTTX(i)) { 562 1.2.2.2 nathanw if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 563 1.2.2.2 nathanw MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 564 1.2.2.2 nathanw break; 565 1.2.2.2 nathanw #ifdef AUMAC_EVENT_COUNTERS 566 1.2.2.2 nathanw gotone = 1; 567 1.2.2.2 nathanw #endif 568 1.2.2.2 nathanw 569 1.2.2.2 nathanw /* ACK interrupt. */ 570 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 571 1.2.2.2 nathanw MACDMA_TX_ADDR(i), 0); 572 1.2.2.2 nathanw 573 1.2.2.2 nathanw stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 574 1.2.2.2 nathanw MACDMA_TX_STAT(i)); 575 1.2.2.2 nathanw 576 1.2.2.2 nathanw if (stat & TX_STAT_FA) { 577 1.2.2.2 nathanw /* XXX STATS */ 578 1.2.2.2 nathanw ifp->if_oerrors++; 579 1.2.2.2 nathanw } else 580 1.2.2.2 nathanw ifp->if_opackets++; 581 1.2.2.2 nathanw 582 1.2.2.2 nathanw if (stat & TX_STAT_EC) 583 1.2.2.2 nathanw ifp->if_collisions += 16; 584 1.2.2.2 nathanw else 585 1.2.2.2 nathanw ifp->if_collisions += TX_STAT_CC(stat); 586 1.2.2.2 nathanw 587 1.2.2.2 nathanw sc->sc_txfree++; 588 1.2.2.2 nathanw ifp->if_flags &= ~IFF_OACTIVE; 589 1.2.2.2 nathanw 590 1.2.2.2 nathanw /* Try to queue more packets. */ 591 1.2.2.2 nathanw aumac_start(ifp); 592 1.2.2.2 nathanw } 593 1.2.2.2 nathanw 594 1.2.2.2 nathanw if (gotone) 595 1.2.2.2 nathanw AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 596 1.2.2.2 nathanw 597 1.2.2.2 nathanw /* Update the dirty descriptor pointer. */ 598 1.2.2.2 nathanw sc->sc_txdirty = i; 599 1.2.2.2 nathanw 600 1.2.2.2 nathanw /* 601 1.2.2.2 nathanw * If there are no more pending transmissions, cancel the watchdog 602 1.2.2.2 nathanw * timer. 603 1.2.2.2 nathanw */ 604 1.2.2.2 nathanw if (sc->sc_txfree == AUMAC_NTXDESC) 605 1.2.2.2 nathanw ifp->if_timer = 0; 606 1.2.2.2 nathanw } 607 1.2.2.2 nathanw 608 1.2.2.2 nathanw /* 609 1.2.2.2 nathanw * aumac_rxintr: 610 1.2.2.2 nathanw * 611 1.2.2.2 nathanw * Helper; handle receive interrupts. 612 1.2.2.2 nathanw */ 613 1.2.2.2 nathanw static void 614 1.2.2.2 nathanw aumac_rxintr(struct aumac_softc *sc) 615 1.2.2.2 nathanw { 616 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 617 1.2.2.2 nathanw struct mbuf *m; 618 1.2.2.2 nathanw uint32_t stat; 619 1.2.2.2 nathanw int i, len; 620 1.2.2.2 nathanw #ifdef AUMAC_EVENT_COUNTERS 621 1.2.2.2 nathanw int pkts = 0; 622 1.2.2.2 nathanw #endif 623 1.2.2.2 nathanw 624 1.2.2.2 nathanw for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 625 1.2.2.2 nathanw if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 626 1.2.2.2 nathanw MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 627 1.2.2.2 nathanw break; 628 1.2.2.2 nathanw #ifdef AUMAC_EVENT_COUNTERS 629 1.2.2.2 nathanw pkts++; 630 1.2.2.2 nathanw #endif 631 1.2.2.2 nathanw 632 1.2.2.2 nathanw stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 633 1.2.2.2 nathanw MACDMA_RX_STAT(i)); 634 1.2.2.2 nathanw 635 1.2.2.2 nathanw #define PRINTERR(str) \ 636 1.2.2.2 nathanw do { \ 637 1.2.2.2 nathanw error++; \ 638 1.2.2.2 nathanw printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 639 1.2.2.2 nathanw } while (0) 640 1.2.2.2 nathanw 641 1.2.2.2 nathanw if (stat & RX_STAT_ERRS) { 642 1.2.2.2 nathanw int error = 0; 643 1.2.2.2 nathanw 644 1.2.2.2 nathanw if (stat & RX_STAT_MI) 645 1.2.2.2 nathanw PRINTERR("missed frame"); 646 1.2.2.2 nathanw if (stat & RX_STAT_UC) 647 1.2.2.2 nathanw PRINTERR("unknown control frame"); 648 1.2.2.2 nathanw if (stat & RX_STAT_LE) 649 1.2.2.2 nathanw PRINTERR("short frame"); 650 1.2.2.2 nathanw if (stat & RX_STAT_CR) 651 1.2.2.2 nathanw PRINTERR("CRC error"); 652 1.2.2.2 nathanw if (stat & RX_STAT_ME) 653 1.2.2.2 nathanw PRINTERR("medium error"); 654 1.2.2.2 nathanw if (stat & RX_STAT_CS) 655 1.2.2.2 nathanw PRINTERR("late collision"); 656 1.2.2.2 nathanw if (stat & RX_STAT_FL) 657 1.2.2.2 nathanw PRINTERR("frame too big"); 658 1.2.2.2 nathanw if (stat & RX_STAT_RF) 659 1.2.2.2 nathanw PRINTERR("runt frame (collision)"); 660 1.2.2.2 nathanw if (stat & RX_STAT_WT) 661 1.2.2.2 nathanw PRINTERR("watch dog"); 662 1.2.2.2 nathanw if (stat & RX_STAT_DB) { 663 1.2.2.2 nathanw if (stat & (RX_STAT_CS | RX_STAT_RF | 664 1.2.2.2 nathanw RX_STAT_CR)) { 665 1.2.2.2 nathanw if (!error) 666 1.2.2.2 nathanw goto pktok; 667 1.2.2.2 nathanw } else 668 1.2.2.2 nathanw PRINTERR("dribbling bit"); 669 1.2.2.2 nathanw } 670 1.2.2.2 nathanw #undef PRINTERR 671 1.2.2.2 nathanw ifp->if_ierrors++; 672 1.2.2.2 nathanw 673 1.2.2.2 nathanw dropit: 674 1.2.2.2 nathanw /* reuse the current descriptor */ 675 1.2.2.2 nathanw AUMAC_INIT_RXDESC(sc, i); 676 1.2.2.2 nathanw continue; 677 1.2.2.2 nathanw } 678 1.2.2.2 nathanw pktok: 679 1.2.2.2 nathanw len = RX_STAT_L(stat); 680 1.2.2.2 nathanw 681 1.2.2.2 nathanw /* 682 1.2.2.2 nathanw * The Au1X00 MAC includes the CRC with every packet; 683 1.2.2.2 nathanw * trim it off here. 684 1.2.2.2 nathanw */ 685 1.2.2.2 nathanw len -= ETHER_CRC_LEN; 686 1.2.2.2 nathanw 687 1.2.2.2 nathanw /* 688 1.2.2.2 nathanw * Truncate the packet if it's too big to fit in 689 1.2.2.2 nathanw * a single mbuf cluster. 690 1.2.2.2 nathanw */ 691 1.2.2.2 nathanw if (len > MCLBYTES - 2) 692 1.2.2.2 nathanw len = MCLBYTES - 2; 693 1.2.2.2 nathanw 694 1.2.2.2 nathanw MGETHDR(m, M_DONTWAIT, MT_DATA); 695 1.2.2.2 nathanw if (m == NULL) { 696 1.2.2.2 nathanw printf("%s: unable to allocate Rx mbuf\n", 697 1.2.2.2 nathanw sc->sc_dev.dv_xname); 698 1.2.2.2 nathanw goto dropit; 699 1.2.2.2 nathanw } 700 1.2.2.2 nathanw if (len > MHLEN - 2) { 701 1.2.2.2 nathanw MCLGET(m, M_DONTWAIT); 702 1.2.2.2 nathanw if ((m->m_flags & M_EXT) == 0) { 703 1.2.2.2 nathanw printf("%s: unable to allocate Rx cluster\n", 704 1.2.2.2 nathanw sc->sc_dev.dv_xname); 705 1.2.2.2 nathanw m_freem(m); 706 1.2.2.2 nathanw goto dropit; 707 1.2.2.2 nathanw } 708 1.2.2.2 nathanw } 709 1.2.2.2 nathanw 710 1.2.2.2 nathanw m->m_data += 2; /* align payload */ 711 1.2.2.2 nathanw memcpy(mtod(m, caddr_t), 712 1.2.2.2 nathanw sc->sc_rxbufs[i].buf_vaddr, len); 713 1.2.2.2 nathanw AUMAC_INIT_RXDESC(sc, i); 714 1.2.2.2 nathanw 715 1.2.2.2 nathanw m->m_pkthdr.rcvif = ifp; 716 1.2.2.2 nathanw m->m_pkthdr.len = m->m_len = len; 717 1.2.2.2 nathanw 718 1.2.2.2 nathanw #if NBPFILTER > 0 719 1.2.2.2 nathanw /* Pass this up to any BPF listeners. */ 720 1.2.2.2 nathanw if (ifp->if_bpf) 721 1.2.2.2 nathanw bpf_mtap(ifp->if_bpf, m); 722 1.2.2.2 nathanw #endif /* NBPFILTER > 0 */ 723 1.2.2.2 nathanw 724 1.2.2.2 nathanw /* Pass it on. */ 725 1.2.2.2 nathanw (*ifp->if_input)(ifp, m); 726 1.2.2.2 nathanw ifp->if_ipackets++; 727 1.2.2.2 nathanw } 728 1.2.2.2 nathanw if (pkts) 729 1.2.2.2 nathanw AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 730 1.2.2.2 nathanw if (pkts == AUMAC_NRXDESC) 731 1.2.2.2 nathanw AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 732 1.2.2.2 nathanw 733 1.2.2.2 nathanw /* Update the receive pointer. */ 734 1.2.2.2 nathanw sc->sc_rxptr = i; 735 1.2.2.2 nathanw } 736 1.2.2.2 nathanw 737 1.2.2.2 nathanw /* 738 1.2.2.2 nathanw * aumac_tick: 739 1.2.2.2 nathanw * 740 1.2.2.2 nathanw * One second timer, used to tick the MII. 741 1.2.2.2 nathanw */ 742 1.2.2.2 nathanw static void 743 1.2.2.2 nathanw aumac_tick(void *arg) 744 1.2.2.2 nathanw { 745 1.2.2.2 nathanw struct aumac_softc *sc = arg; 746 1.2.2.2 nathanw int s; 747 1.2.2.2 nathanw 748 1.2.2.2 nathanw s = splnet(); 749 1.2.2.2 nathanw mii_tick(&sc->sc_mii); 750 1.2.2.2 nathanw splx(s); 751 1.2.2.2 nathanw 752 1.2.2.2 nathanw callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 753 1.2.2.2 nathanw } 754 1.2.2.2 nathanw 755 1.2.2.2 nathanw /* 756 1.2.2.2 nathanw * aumac_init: [ifnet interface function] 757 1.2.2.2 nathanw * 758 1.2.2.2 nathanw * Initialize the interface. Must be called at splnet(). 759 1.2.2.2 nathanw */ 760 1.2.2.2 nathanw static int 761 1.2.2.2 nathanw aumac_init(struct ifnet *ifp) 762 1.2.2.2 nathanw { 763 1.2.2.2 nathanw struct aumac_softc *sc = ifp->if_softc; 764 1.2.2.2 nathanw int i, error = 0; 765 1.2.2.2 nathanw 766 1.2.2.2 nathanw /* Cancel any pending I/O, reset MAC. */ 767 1.2.2.2 nathanw aumac_stop(ifp, 0); 768 1.2.2.2 nathanw 769 1.2.2.2 nathanw /* Set up the transmit ring. */ 770 1.2.2.2 nathanw for (i = 0; i < AUMAC_NTXDESC; i++) { 771 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 772 1.2.2.2 nathanw MACDMA_TX_STAT(i), 0); 773 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 774 1.2.2.2 nathanw MACDMA_TX_LEN(i), 0); 775 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 776 1.2.2.2 nathanw MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 777 1.2.2.2 nathanw } 778 1.2.2.2 nathanw sc->sc_txfree = AUMAC_NTXDESC; 779 1.2.2.2 nathanw sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 780 1.2.2.2 nathanw MACDMA_TX_ADDR(0))); 781 1.2.2.2 nathanw sc->sc_txdirty = sc->sc_txnext; 782 1.2.2.2 nathanw 783 1.2.2.2 nathanw /* Set up the receive ring. */ 784 1.2.2.2 nathanw for (i = 0; i < AUMAC_NRXDESC; i++) 785 1.2.2.2 nathanw AUMAC_INIT_RXDESC(sc, i); 786 1.2.2.2 nathanw sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 787 1.2.2.2 nathanw MACDMA_RX_ADDR(0))); 788 1.2.2.2 nathanw 789 1.2.2.2 nathanw /* 790 1.2.2.2 nathanw * Power up the MAC. 791 1.2.2.2 nathanw */ 792 1.2.2.2 nathanw aumac_powerup(sc); 793 1.2.2.2 nathanw 794 1.2.2.2 nathanw sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 795 1.2.2.2 nathanw #if _BYTE_ORDER == _BIG_ENDIAN 796 1.2.2.2 nathanw sc->sc_control |= CONTROL_EM; 797 1.2.2.2 nathanw #endif 798 1.2.2.2 nathanw 799 1.2.2.2 nathanw /* Set the media. */ 800 1.2.2.2 nathanw aumac_mediachange(ifp); 801 1.2.2.2 nathanw 802 1.2.2.2 nathanw /* 803 1.2.2.2 nathanw * Set the receive filter. This will actually start the transmit 804 1.2.2.2 nathanw * and receive processes. 805 1.2.2.2 nathanw */ 806 1.2.2.2 nathanw aumac_set_filter(sc); 807 1.2.2.2 nathanw 808 1.2.2.2 nathanw /* Start the one second clock. */ 809 1.2.2.2 nathanw callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 810 1.2.2.2 nathanw 811 1.2.2.2 nathanw /* ...all done! */ 812 1.2.2.2 nathanw ifp->if_flags |= IFF_RUNNING; 813 1.2.2.2 nathanw ifp->if_flags &= ~IFF_OACTIVE; 814 1.2.2.2 nathanw 815 1.2.2.2 nathanw if (error) 816 1.2.2.2 nathanw printf("%s: interface not running\n", sc->sc_dev.dv_xname); 817 1.2.2.2 nathanw return (error); 818 1.2.2.2 nathanw } 819 1.2.2.2 nathanw 820 1.2.2.2 nathanw /* 821 1.2.2.2 nathanw * aumac_stop: [ifnet interface function] 822 1.2.2.2 nathanw * 823 1.2.2.2 nathanw * Stop transmission on the interface. 824 1.2.2.2 nathanw */ 825 1.2.2.2 nathanw static void 826 1.2.2.2 nathanw aumac_stop(struct ifnet *ifp, int disable) 827 1.2.2.2 nathanw { 828 1.2.2.2 nathanw struct aumac_softc *sc = ifp->if_softc; 829 1.2.2.2 nathanw 830 1.2.2.2 nathanw /* Stop the one-second clock. */ 831 1.2.2.2 nathanw callout_stop(&sc->sc_tick_ch); 832 1.2.2.2 nathanw 833 1.2.2.2 nathanw /* Down the MII. */ 834 1.2.2.2 nathanw mii_down(&sc->sc_mii); 835 1.2.2.2 nathanw 836 1.2.2.2 nathanw /* Stop the transmit and receive processes. */ 837 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 838 1.2.2.2 nathanw 839 1.2.2.2 nathanw /* Power down/reset the MAC. */ 840 1.2.2.2 nathanw aumac_powerdown(sc); 841 1.2.2.2 nathanw 842 1.2.2.2 nathanw /* Mark the interface as down and cancel the watchdog timer. */ 843 1.2.2.2 nathanw ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 844 1.2.2.2 nathanw ifp->if_timer = 0; 845 1.2.2.2 nathanw } 846 1.2.2.2 nathanw 847 1.2.2.2 nathanw /* 848 1.2.2.2 nathanw * aumac_powerdown: 849 1.2.2.2 nathanw * 850 1.2.2.2 nathanw * Power down the MAC. 851 1.2.2.2 nathanw */ 852 1.2.2.2 nathanw static void 853 1.2.2.2 nathanw aumac_powerdown(struct aumac_softc *sc) 854 1.2.2.2 nathanw { 855 1.2.2.2 nathanw 856 1.2.2.2 nathanw /* Disable the MAC clocks, and place the device in reset. */ 857 1.2.2.2 nathanw // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 858 1.2.2.2 nathanw 859 1.2.2.2 nathanw // delay(10000); 860 1.2.2.2 nathanw } 861 1.2.2.2 nathanw 862 1.2.2.2 nathanw /* 863 1.2.2.2 nathanw * aumac_powerup: 864 1.2.2.2 nathanw * 865 1.2.2.2 nathanw * Bring the device out of reset. 866 1.2.2.2 nathanw */ 867 1.2.2.2 nathanw static void 868 1.2.2.2 nathanw aumac_powerup(struct aumac_softc *sc) 869 1.2.2.2 nathanw { 870 1.2.2.2 nathanw 871 1.2.2.2 nathanw /* Enable clocks to the MAC. */ 872 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 873 1.2.2.2 nathanw 874 1.2.2.2 nathanw /* Enable MAC, coherent transactions, pass only valid frames. */ 875 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 876 1.2.2.2 nathanw MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 877 1.2.2.2 nathanw 878 1.2.2.2 nathanw delay(20000); 879 1.2.2.2 nathanw } 880 1.2.2.2 nathanw 881 1.2.2.2 nathanw /* 882 1.2.2.2 nathanw * aumac_set_filter: 883 1.2.2.2 nathanw * 884 1.2.2.2 nathanw * Set up the receive filter. 885 1.2.2.2 nathanw */ 886 1.2.2.2 nathanw static void 887 1.2.2.2 nathanw aumac_set_filter(struct aumac_softc *sc) 888 1.2.2.2 nathanw { 889 1.2.2.2 nathanw struct ethercom *ec = &sc->sc_ethercom; 890 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 891 1.2.2.2 nathanw struct ether_multi *enm; 892 1.2.2.2 nathanw struct ether_multistep step; 893 1.2.2.2 nathanw const uint8_t *enaddr = LLADDR(ifp->if_sadl); 894 1.2.2.2 nathanw uint32_t mchash[2], crc; 895 1.2.2.2 nathanw 896 1.2.2.2 nathanw sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 897 1.2.2.2 nathanw 898 1.2.2.2 nathanw /* Stop the receiver. */ 899 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 900 1.2.2.2 nathanw sc->sc_control & ~CONTROL_RE); 901 1.2.2.2 nathanw 902 1.2.2.2 nathanw if (ifp->if_flags & IFF_PROMISC) { 903 1.2.2.2 nathanw sc->sc_control |= CONTROL_PR; 904 1.2.2.2 nathanw goto allmulti; 905 1.2.2.2 nathanw } 906 1.2.2.2 nathanw 907 1.2.2.2 nathanw /* Set the station address. */ 908 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 909 1.2.2.2 nathanw enaddr[4] | (enaddr[5] << 8)); 910 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 911 1.2.2.2 nathanw enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 912 1.2.2.2 nathanw (enaddr[3] << 24)); 913 1.2.2.2 nathanw 914 1.2.2.2 nathanw sc->sc_control |= CONTROL_HP; 915 1.2.2.2 nathanw 916 1.2.2.2 nathanw mchash[0] = mchash[1] = 0; 917 1.2.2.2 nathanw 918 1.2.2.2 nathanw /* 919 1.2.2.2 nathanw * Set up the multicast address filter by passing all multicast 920 1.2.2.2 nathanw * addresses through a CRC generator, and then using the high 921 1.2.2.2 nathanw * order 6 bits as an index into the 64-bit multicast hash table. 922 1.2.2.2 nathanw * The high order bits select the word, while the rest of the bits 923 1.2.2.2 nathanw * select the bit within the word. 924 1.2.2.2 nathanw */ 925 1.2.2.2 nathanw ETHER_FIRST_MULTI(step, ec, enm); 926 1.2.2.2 nathanw while (enm != NULL) { 927 1.2.2.2 nathanw if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 928 1.2.2.2 nathanw /* 929 1.2.2.2 nathanw * We must listen to a range of multicast addresses. 930 1.2.2.2 nathanw * For now, just accept all multicasts, rather than 931 1.2.2.2 nathanw * trying to set only those filter bits needed to match 932 1.2.2.2 nathanw * the range. (At this time, the only use of address 933 1.2.2.2 nathanw * ranges is for IP multicast routing, for which the 934 1.2.2.2 nathanw * range is large enough to require all bits set.) 935 1.2.2.2 nathanw */ 936 1.2.2.2 nathanw goto allmulti; 937 1.2.2.2 nathanw } 938 1.2.2.2 nathanw 939 1.2.2.2 nathanw crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 940 1.2.2.2 nathanw 941 1.2.2.2 nathanw /* Just want the 6 most significant bits. */ 942 1.2.2.2 nathanw crc >>= 26; 943 1.2.2.2 nathanw 944 1.2.2.2 nathanw /* Set the corresponding bit in the filter. */ 945 1.2.2.2 nathanw mchash[crc >> 5] |= 1U << (crc & 0x1f); 946 1.2.2.2 nathanw 947 1.2.2.2 nathanw ETHER_NEXT_MULTI(step, enm); 948 1.2.2.2 nathanw } 949 1.2.2.2 nathanw 950 1.2.2.2 nathanw ifp->if_flags &= ~IFF_ALLMULTI; 951 1.2.2.2 nathanw 952 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 953 1.2.2.2 nathanw mchash[1]); 954 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 955 1.2.2.2 nathanw mchash[0]); 956 1.2.2.2 nathanw 957 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 958 1.2.2.2 nathanw sc->sc_control); 959 1.2.2.2 nathanw return; 960 1.2.2.2 nathanw 961 1.2.2.2 nathanw allmulti: 962 1.2.2.2 nathanw sc->sc_control |= CONTROL_PM; 963 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 964 1.2.2.2 nathanw sc->sc_control); 965 1.2.2.2 nathanw } 966 1.2.2.2 nathanw 967 1.2.2.2 nathanw /* 968 1.2.2.2 nathanw * aumac_mediastatus: [ifmedia interface function] 969 1.2.2.2 nathanw * 970 1.2.2.2 nathanw * Get the current interface media status. 971 1.2.2.2 nathanw */ 972 1.2.2.2 nathanw static void 973 1.2.2.2 nathanw aumac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 974 1.2.2.2 nathanw { 975 1.2.2.2 nathanw struct aumac_softc *sc = ifp->if_softc; 976 1.2.2.2 nathanw 977 1.2.2.2 nathanw mii_pollstat(&sc->sc_mii); 978 1.2.2.2 nathanw ifmr->ifm_status = sc->sc_mii.mii_media_status; 979 1.2.2.2 nathanw ifmr->ifm_active = sc->sc_mii.mii_media_active; 980 1.2.2.2 nathanw } 981 1.2.2.2 nathanw 982 1.2.2.2 nathanw /* 983 1.2.2.2 nathanw * aumac_mediachange: [ifmedia interface function] 984 1.2.2.2 nathanw * 985 1.2.2.2 nathanw * Set hardware to newly selected media. 986 1.2.2.2 nathanw */ 987 1.2.2.2 nathanw static int 988 1.2.2.2 nathanw aumac_mediachange(struct ifnet *ifp) 989 1.2.2.2 nathanw { 990 1.2.2.2 nathanw struct aumac_softc *sc = ifp->if_softc; 991 1.2.2.2 nathanw 992 1.2.2.2 nathanw if (ifp->if_flags & IFF_UP) 993 1.2.2.2 nathanw mii_mediachg(&sc->sc_mii); 994 1.2.2.2 nathanw return (0); 995 1.2.2.2 nathanw } 996 1.2.2.2 nathanw 997 1.2.2.2 nathanw /* 998 1.2.2.2 nathanw * aumac_mii_wait: 999 1.2.2.2 nathanw * 1000 1.2.2.2 nathanw * Wait for the MII interface to not be busy. 1001 1.2.2.2 nathanw */ 1002 1.2.2.2 nathanw static int 1003 1.2.2.2 nathanw aumac_mii_wait(struct aumac_softc *sc, const char *msg) 1004 1.2.2.2 nathanw { 1005 1.2.2.2 nathanw int i; 1006 1.2.2.2 nathanw 1007 1.2.2.2 nathanw for (i = 0; i < 10000; i++) { 1008 1.2.2.2 nathanw if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 1009 1.2.2.2 nathanw MAC_MIICTRL) & MIICTRL_MB) == 0) 1010 1.2.2.2 nathanw return (0); 1011 1.2.2.2 nathanw delay(10); 1012 1.2.2.2 nathanw } 1013 1.2.2.2 nathanw 1014 1.2.2.2 nathanw printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 1015 1.2.2.2 nathanw return (1); 1016 1.2.2.2 nathanw } 1017 1.2.2.2 nathanw 1018 1.2.2.2 nathanw /* 1019 1.2.2.2 nathanw * aumac_mii_readreg: [mii interface function] 1020 1.2.2.2 nathanw * 1021 1.2.2.2 nathanw * Read a PHY register on the MII. 1022 1.2.2.2 nathanw */ 1023 1.2.2.2 nathanw static int 1024 1.2.2.2 nathanw aumac_mii_readreg(struct device *self, int phy, int reg) 1025 1.2.2.2 nathanw { 1026 1.2.2.2 nathanw struct aumac_softc *sc = (void *) self; 1027 1.2.2.2 nathanw 1028 1.2.2.2 nathanw if (aumac_mii_wait(sc, "become ready")) 1029 1.2.2.2 nathanw return (0); 1030 1.2.2.2 nathanw 1031 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1032 1.2.2.2 nathanw MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1033 1.2.2.2 nathanw 1034 1.2.2.2 nathanw if (aumac_mii_wait(sc, "complete")) 1035 1.2.2.2 nathanw return (0); 1036 1.2.2.2 nathanw 1037 1.2.2.2 nathanw return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1038 1.2.2.2 nathanw MIIDATA_MASK); 1039 1.2.2.2 nathanw } 1040 1.2.2.2 nathanw 1041 1.2.2.2 nathanw /* 1042 1.2.2.2 nathanw * aumac_mii_writereg: [mii interface function] 1043 1.2.2.2 nathanw * 1044 1.2.2.2 nathanw * Write a PHY register on the MII. 1045 1.2.2.2 nathanw */ 1046 1.2.2.2 nathanw static void 1047 1.2.2.2 nathanw aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1048 1.2.2.2 nathanw { 1049 1.2.2.2 nathanw struct aumac_softc *sc = (void *) self; 1050 1.2.2.2 nathanw 1051 1.2.2.2 nathanw if (aumac_mii_wait(sc, "become ready")) 1052 1.2.2.2 nathanw return; 1053 1.2.2.2 nathanw 1054 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1055 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1056 1.2.2.2 nathanw MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1057 1.2.2.2 nathanw 1058 1.2.2.2 nathanw (void) aumac_mii_wait(sc, "complete"); 1059 1.2.2.2 nathanw } 1060 1.2.2.2 nathanw 1061 1.2.2.2 nathanw /* 1062 1.2.2.2 nathanw * aumac_mii_statchg: [mii interface function] 1063 1.2.2.2 nathanw * 1064 1.2.2.2 nathanw * Callback from MII layer when media changes. 1065 1.2.2.2 nathanw */ 1066 1.2.2.2 nathanw static void 1067 1.2.2.2 nathanw aumac_mii_statchg(struct device *self) 1068 1.2.2.2 nathanw { 1069 1.2.2.2 nathanw struct aumac_softc *sc = (void *) self; 1070 1.2.2.2 nathanw 1071 1.2.2.2 nathanw if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1072 1.2.2.2 nathanw sc->sc_control |= CONTROL_F; 1073 1.2.2.2 nathanw else 1074 1.2.2.2 nathanw sc->sc_control &= ~CONTROL_F; 1075 1.2.2.2 nathanw 1076 1.2.2.2 nathanw bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1077 1.2.2.2 nathanw sc->sc_control); 1078 1.2.2.2 nathanw } 1079
Indexes created Tue Oct 14 06:10:07 GMT 2025