ohci_aubus.c revision 1.10
1 /* $NetBSD: ohci_aubus.c,v 1.10 2006/02/09 03:14:31 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Herb Peyerl of Middle Digital Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ohci_aubus.c,v 1.10 2006/02/09 03:14:31 gdamore Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 48 #include <mips/alchemy/include/aureg.h> 49 #include <mips/alchemy/include/auvar.h> 50 #include <mips/alchemy/include/aubusvar.h> 51 #include <mips/alchemy/dev/ohcireg.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdivar.h> 56 #include <dev/usb/usb_mem.h> 57 58 #include <dev/usb/ohcireg.h> 59 #include <dev/usb/ohcivar.h> 60 61 62 static int ohci_aubus_match(struct device *, struct cfdata *, void *); 63 static void ohci_aubus_attach(struct device *, struct device *, void *); 64 65 CFATTACH_DECL(ohci_aubus, sizeof (ohci_softc_t), 66 ohci_aubus_match, ohci_aubus_attach, NULL, NULL); 67 68 int 69 ohci_aubus_match(struct device *parent, struct cfdata *match, void *aux) 70 { 71 struct aubus_attach_args *aa = aux; 72 73 if (strcmp(aa->aa_name, match->cf_name) == 0) 74 return (1); 75 76 return (0); 77 } 78 79 void 80 ohci_aubus_attach(struct device *parent, struct device *self, void *aux) 81 { 82 ohci_softc_t *sc = (ohci_softc_t *)self; 83 void *ih; 84 usbd_status r; 85 uint32_t x, tmp; 86 bus_addr_t usbh_base, usbh_enable; 87 struct aubus_attach_args *aa = aux; 88 89 r = 0; 90 91 usbh_base = aa->aa_addrs[0]; 92 usbh_enable = aa->aa_addrs[1]; 93 sc->sc_size = aa->aa_addrs[2]; 94 sc->iot = aa->aa_st; 95 sc->sc_bus.dmatag = (bus_dma_tag_t)aa->aa_dt; 96 97 if (bus_space_map(sc->iot, usbh_base, sc->sc_size, 0, &sc->ioh)) { 98 printf("%s: Unable to map USBH registers\n", 99 sc->sc_bus.bdev.dv_xname); 100 return; 101 } 102 /* 103 * Enable the USB Host controller here. 104 * As per 7.2 in the Au1500 manual: 105 * 106 * (1) Set CE bit to enable clocks. 107 * (2) Set E to enable OHCI 108 * (3) Clear HCFS in OHCI_CONTROL. 109 * (4) Wait for RD bit to be set. 110 */ 111 x = bus_space_read_4(sc->iot, sc->ioh, usbh_enable); 112 x |= UE_CE; 113 bus_space_write_4(sc->iot, sc->ioh, usbh_enable, x); 114 delay(10); 115 x |= UE_E; 116 #ifdef __MIPSEB__ 117 x |= UE_BE; 118 #endif 119 bus_space_write_4(sc->iot, sc->ioh, usbh_enable, x); 120 delay(10); 121 x = bus_space_read_4(sc->iot, sc->ioh, OHCI_CONTROL); 122 x &= ~(OHCI_HCFS_MASK); 123 bus_space_write_4(sc->iot, sc->ioh, OHCI_CONTROL, x); 124 delay(10); 125 /* Need to read USBH_ENABLE twice in succession according to 126 * au1500 Errata #7. 127 */ 128 for (x = 100; x; x--) { 129 bus_space_read_4(sc->iot, sc->ioh, usbh_enable); 130 tmp = bus_space_read_4(sc->iot, sc->ioh, usbh_enable); 131 if (tmp&UE_RD) 132 break; 133 delay(1000); 134 } 135 printf(": Alchemy OHCI\n"); 136 137 /* Disable OHCI interrupts */ 138 bus_space_write_4(sc->iot, sc->ioh, OHCI_INTERRUPT_DISABLE, 139 OHCI_ALL_INTRS); 140 /* hook interrupt */ 141 ih = au_intr_establish(aa->aa_irq[0], 0, IPL_USB, IST_LEVEL_LOW, 142 ohci_intr, sc); 143 if (ih == NULL) { 144 printf("%s: couldn't establish interrupt\n", 145 sc->sc_bus.bdev.dv_xname); 146 } 147 148 sc->sc_endian = OHCI_HOST_ENDIAN; 149 150 if (x) 151 r = ohci_init(sc); 152 if (r != USBD_NORMAL_COMPLETION) { 153 printf("%s: init failed, error=%d\n", 154 sc->sc_bus.bdev.dv_xname, r); 155 au_intr_disestablish(ih); 156 return; 157 } 158 159 /* Attach USB device */ 160 sc->sc_child = config_found((void *)sc, &sc->sc_bus, usbctlprint); 161 162 } 163
Indexes created Sun Sep 28 12:09:53 GMT 2025