ohci_aubus.c revision 1.11
1 /* $NetBSD: ohci_aubus.c,v 1.11 2008/03/31 02:42:42 dogcow Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Herb Peyerl of Middle Digital Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ohci_aubus.c,v 1.11 2008/03/31 02:42:42 dogcow Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 48 #include <mips/alchemy/include/aureg.h> 49 #include <mips/alchemy/include/auvar.h> 50 #include <mips/alchemy/include/aubusvar.h> 51 #include <mips/alchemy/dev/ohcireg.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdivar.h> 56 #include <dev/usb/usb_mem.h> 57 58 #include <dev/usb/ohcireg.h> 59 #include <dev/usb/ohcivar.h> 60 61 62 static int ohci_aubus_match(struct device *, struct cfdata *, void *); 63 static void ohci_aubus_attach(struct device *, struct device *, void *); 64 65 CFATTACH_DECL(ohci_aubus, sizeof (ohci_softc_t), 66 ohci_aubus_match, ohci_aubus_attach, NULL, NULL); 67 68 int 69 ohci_aubus_match(struct device *parent, struct cfdata *match, void *aux) 70 { 71 struct aubus_attach_args *aa = aux; 72 73 if (strcmp(aa->aa_name, match->cf_name) == 0) 74 return (1); 75 76 return (0); 77 } 78 79 void 80 ohci_aubus_attach(struct device *parent, struct device *self, void *aux) 81 { 82 ohci_softc_t *sc = (ohci_softc_t *)self; 83 void *ih; 84 usbd_status r; 85 uint32_t x, tmp; 86 bus_addr_t usbh_base, usbh_enable; 87 struct aubus_attach_args *aa = aux; 88 89 r = 0; 90 91 usbh_base = aa->aa_addrs[0]; 92 usbh_enable = aa->aa_addrs[1]; 93 sc->sc_size = aa->aa_addrs[2]; 94 sc->iot = aa->aa_st; 95 sc->sc_bus.dmatag = (bus_dma_tag_t)aa->aa_dt; 96 97 if (bus_space_map(sc->iot, usbh_base, sc->sc_size, 0, &sc->ioh)) { 98 aprint_error_dev(self, "unable to map USBH registers\n"); 99 return; 100 } 101 /* 102 * Enable the USB Host controller here. 103 * As per 7.2 in the Au1500 manual: 104 * 105 * (1) Set CE bit to enable clocks. 106 * (2) Set E to enable OHCI 107 * (3) Clear HCFS in OHCI_CONTROL. 108 * (4) Wait for RD bit to be set. 109 */ 110 x = bus_space_read_4(sc->iot, sc->ioh, usbh_enable); 111 x |= UE_CE; 112 bus_space_write_4(sc->iot, sc->ioh, usbh_enable, x); 113 delay(10); 114 x |= UE_E; 115 #ifdef __MIPSEB__ 116 x |= UE_BE; 117 #endif 118 bus_space_write_4(sc->iot, sc->ioh, usbh_enable, x); 119 delay(10); 120 x = bus_space_read_4(sc->iot, sc->ioh, OHCI_CONTROL); 121 x &= ~(OHCI_HCFS_MASK); 122 bus_space_write_4(sc->iot, sc->ioh, OHCI_CONTROL, x); 123 delay(10); 124 /* Need to read USBH_ENABLE twice in succession according to 125 * au1500 Errata #7. 126 */ 127 for (x = 100; x; x--) { 128 bus_space_read_4(sc->iot, sc->ioh, usbh_enable); 129 tmp = bus_space_read_4(sc->iot, sc->ioh, usbh_enable); 130 if (tmp&UE_RD) 131 break; 132 delay(1000); 133 } 134 printf(": Alchemy OHCI\n"); 135 136 /* Disable OHCI interrupts */ 137 bus_space_write_4(sc->iot, sc->ioh, OHCI_INTERRUPT_DISABLE, 138 OHCI_ALL_INTRS); 139 /* hook interrupt */ 140 ih = au_intr_establish(aa->aa_irq[0], 0, IPL_USB, IST_LEVEL_LOW, 141 ohci_intr, sc); 142 if (ih == NULL) { 143 aprint_error_dev(self,"couldn't establish interrupt\n"); 144 } 145 146 sc->sc_endian = OHCI_HOST_ENDIAN; 147 148 if (x) 149 r = ohci_init(sc); 150 if (r != USBD_NORMAL_COMPLETION) { 151 aprint_error_dev(self, "init failed, error=%d\n", r); 152 au_intr_disestablish(ih); 153 return; 154 } 155 156 /* Attach USB device */ 157 sc->sc_child = config_found((void *)sc, &sc->sc_bus, usbctlprint); 158 159 } 160
Indexes created Mon Sep 29 03:10:08 GMT 2025