aureg.h revision 1.10
1 /* $NetBSD: aureg.h,v 1.10 2006/02/09 01:20:18 gdamore Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* ********************************************************************* 39 * Naming schemes for constants in these files: 40 * 41 * M_xxx MASK constant (identifies bits in a register). 42 * For multi-bit fields, all bits in the field will 43 * be set. 44 * 45 * K_xxx "Code" constant (value for data in a multi-bit 46 * field). The value is right justified. 47 * 48 * V_xxx "Value" constant. This is the same as the 49 * corresponding "K_xxx" constant, except it is 50 * shifted to the correct position in the register. 51 * 52 * S_xxx SHIFT constant. This is the number of bits that 53 * a field value (code) needs to be shifted 54 * (towards the left) to put the value in the right 55 * position for the register. 56 * 57 * A_xxx ADDRESS constant. This will be a physical 58 * address. Use the MIPS_PHYS_TO_KSEG1 macro to 59 * generate a K1SEG address. 60 * 61 * R_xxx RELATIVE offset constant. This is an offset from 62 * an A_xxx constant (usually the first register in 63 * a group). 64 * 65 * G_xxx(X) GET value. This macro obtains a multi-bit field 66 * from a register, masks it, and shifts it to 67 * the bottom of the register (retrieving a K_xxx 68 * value, for example). 69 * 70 * V_xxx(X) VALUE. This macro computes the value of a 71 * K_xxx constant shifted to the correct position 72 * in the register. 73 ********************************************************************* */ 74 75 #if !defined(__ASSEMBLER__) 76 #define _MAKE64(x) ((uint64_t)(x)) 77 #define _MAKE32(x) ((uint32_t)(x)) 78 #else 79 #define _MAKE64(x) (x) 80 #define _MAKE32(x) (x) 81 #endif 82 83 /* Make a mask for 1 bit at position 'n' */ 84 #define _MAKEMASK1_64(n) (_MAKE64(1) << _MAKE64(n)) 85 #define _MAKEMASK1_32(n) (_MAKE32(1) << _MAKE32(n)) 86 87 /* Make a mask for 'v' bits at position 'n' */ 88 #define _MAKEMASK_64(v,n) (_MAKE64((_MAKE64(1)<<(v))-1) << _MAKE64(n)) 89 #define _MAKEMASK_32(v,n) (_MAKE32((_MAKE32(1)<<(v))-1) << _MAKE32(n)) 90 91 /* Make a value at 'v' at bit position 'n' */ 92 #define _MAKEVALUE_64(v,n) (_MAKE64(v) << _MAKE64(n)) 93 #define _MAKEVALUE_32(v,n) (_MAKE32(v) << _MAKE32(n)) 94 95 #define _GETVALUE_64(v,n,m) ((_MAKE64(v) & _MAKE64(m)) >> _MAKE64(n)) 96 #define _GETVALUE_32(v,n,m) ((_MAKE32(v) & _MAKE32(m)) >> _MAKE32(n)) 97 98 99 /************************************************************************/ 100 /******************** AC97 Controller registers *********************/ 101 /************************************************************************/ 102 #define AC97_BASE 0x10000000 103 104 #define AC97_CONFIG 0x00 105 106 #define M_AC97CFG_RS _MAKEMASK1_32(0) 107 #define M_AC97CFG_SN _MAKEMASK1_32(1) 108 #define M_AC97CFG_SG _MAKEMASK1_32(2) 109 110 #define S_AC97CFG_XS _MAKE32(12) 111 #define M_AC97CFG_XS _MAKEMASK_32(10) 112 #define V_AC97CFG_XS(x) _MAKEVALUE_32(x, S_AC97CFG_XS) 113 #define G_AC97CFG_XS(x) _GETVALUE_32(x, S_AC97CFG_XS, M_AC97CFG_XS) 114 115 #define S_AC97CFG_RC _MAKE32(12) 116 #define M_AC97CFG_RC _MAKEMASK_32(10) 117 #define V_AC97CFG_RC(x) _MAKEVALUE_32(x, S_AC97CFG_RC) 118 #define G_AC97CFG_RC(x) _GETVALUE_32(x, S_AC97CFG_RC, M_AC97CFG_RC) 119 120 #define AC97_STATUS 0x04 121 122 #define M_AC97STAT_RF _MAKEMASK1_32(0) 123 #define M_AC97STAT_RE _MAKEMASK1_32(1) 124 #define M_AC97STAT_TF _MAKEMASK1_32(3) 125 #define M_AC97STAT_TE _MAKEMASK1_32(4) 126 #define M_AC97STAT_CP _MAKEMASK1_32(6) 127 #define M_AC97STAT_RD _MAKEMASK1_32(7) 128 #define M_AC97STAT_RO _MAKEMASK1_32(8) 129 #define M_AC97STAT_RU _MAKEMASK1_32(9) 130 #define M_AC97STAT_XO _MAKEMASK1_32(10) 131 #define M_AC97STAT_XU _MAKEMASK1_32(11) 132 133 #define AC97_DATA 0x08 134 135 #define S_AC97DATA_DATA _MAKE32(0) 136 #define M_AC97DATA_DATA _MAKEMASK_32(16) 137 #define V_AC97DATA_DATA(x) _MAKEVALUE_32(x, S_AC97DATA_DATA) 138 #define G_AC97DATA_DATA(x) _GETVALUE_32(x, S_AC97DATA_DATA, M_AC97DATA_DATA) 139 140 #define AC97_COMMAND 0x0c 141 142 #define S_AC97CMD_INDEX _MAKE32(0) 143 #define M_AC97CMD_INDEX _MAKEMASK_32(7) 144 #define V_AC97CMD_INDEX(x) _MAKEVALUE_32(x, S_AC97CMD_INDEX) 145 #define G_AC97CMD_INDEX(x) _GETVALUE_32(x, S_AC97CMD_INDEX, M_AC97CMD_INDEX) 146 147 #define M_AC97CMD_RW _MAKEMASK1_32(7) 148 149 #define S_AC97CMD_DATA _MAKE32(16) 150 #define M_AC97CMD_DATA _MAKEMASK_32(16) 151 #define V_AC97CMD_DATA(x) _MAKEVALUE_32(x, S_AC97CMD_DATA) 152 #define G_AC97CMD_DATA(x) _GETVALUE_32(x, S_AC97CMD_DATA, M_AC97CMD_DATA) 153 154 #define AC97_COMMAND_RESPONSE 0x0c 155 156 #define S_AC97CMDRESP_DATA _MAKE32(0) 157 #define M_AC97CMDRESP_DATA _MAKEMASK_32(16) 158 #define V_AC97CMDRESP_DATA(x) _MAKEVALUE_32(x, S_AC97CMDRESP_DATA) 159 #define G_AC97CMDRESP_DATA(x) _GETVALUE_32(x, S_AC97CMDRESP_DATA, M_AC97CMDRESP_DATA) 160 161 #define AC97_ENABLE 0x10 162 163 #define M_AC97EN_CE _MAKEMASK1_32(0) 164 #define M_AC97EN_D _MAKEMASK1_32(1) 165 166 #define AC97_SIZE 0x14 /* size of register set */ 167 168 /************************************************************************/ 169 /*********************** USB Host registers *************************/ 170 /************************************************************************/ 171 #define USBH_BASE 0x10100000 172 173 #define USBH_ENABLE 0x7fffc 174 #define UE_RD 0x00000010 /* reset done */ 175 #define UE_CE 0x00000008 /* clock enable */ 176 #define UE_E 0x00000004 /* enable */ 177 #define UE_C 0x00000002 /* coherent */ 178 #define UE_BE 0x00000001 /* big-endian */ 179 180 #define USBH_SIZE 0x100000 /* size of register set */ 181 182 #define AU1550_USBH_BASE 0x14020000 183 #define AU1550_USBH_ENABLE 0x7ffc 184 #define AU1550_USBH_SIZE 0x60000 185 186 /************************************************************************/ 187 /********************** USB Device registers ************************/ 188 /************************************************************************/ 189 #define USBD_BASE 0x10200000 190 191 #define USBD_EP0RD 0x00 /* Read from endpoint 0 */ 192 #define USBD_EP0WR 0x04 /* Write to endpoint 0 */ 193 #define USBD_EP1WR 0x08 /* Write to endpoint 1 */ 194 #define USBD_EP2WR 0x0c /* Write to endpoint 2 */ 195 #define USBD_EP3RD 0x10 /* Read from endpoint 3 */ 196 #define USBD_EP4RD 0x14 /* Read from endpoint 4 */ 197 #define USBD_INTEN 0x18 /* Interrupt Enable Register */ 198 #define USBD_INTSTAT 0x1c /* Interrupt Status Register */ 199 #define USBD_CONFIG 0x20 /* Write Configuration Register */ 200 #define USBD_EP0CS 0x24 /* Endpoint 0 control and status */ 201 #define USBD_EP1CS 0x28 /* Endpoint 1 control and status */ 202 #define USBD_EP2CS 0x2c /* Endpoint 2 control and status */ 203 #define USBD_EP3CS 0x30 /* Endpoint 3 control and status */ 204 #define USBD_EP4CS 0x34 /* Endpoint 4 control and status */ 205 #define USBD_FRAMENUM 0x38 /* Current frame number */ 206 #define USBD_EP0RDSTAT 0x40 /* EP0 Read FIFO Status */ 207 #define USBD_EP0WRSTAT 0x44 /* EP0 Write FIFO Status */ 208 #define USBD_EP1WRSTAT 0x48 /* EP1 Write FIFO Status */ 209 #define USBD_EP2WRSTAT 0x4c /* EP2 Write FIFO Status */ 210 #define USBD_EP3RDSTAT 0x50 /* EP3 Read FIFO Status */ 211 #define USBD_EP4RDSTAT 0x54 /* EP4 Read FIFO Status */ 212 #define USBD_ENABLE 0x58 /* USB Device Controller Enable */ 213 214 /************************************************************************/ 215 /************************* IRDA registers ***************************/ 216 /************************************************************************/ 217 #define IRDA_BASE 0x10300000 218 219 /************************************************************************/ 220 /****************** Interrupt Controller registers ******************/ 221 /************************************************************************/ 222 223 #define IC0_BASE 0x10400000 224 #define IC1_BASE 0x11800000 225 226 /* 227 * The *_READ registers read the current value of the register 228 * The *_SET registers set to 1 all bits that are written 1 229 * The *_CLEAR registers clear to zero all bits that are written as 1 230 */ 231 #define IC_CONFIG0_READ 0x40 /* See table below */ 232 #define IC_CONFIG0_SET 0x40 233 #define IC_CONFIG0_CLEAR 0x44 234 235 #define IC_CONFIG1_READ 0x48 /* See table below */ 236 #define IC_CONFIG1_SET 0x48 237 #define IC_CONFIG1_CLEAR 0x4c 238 239 #define IC_CONFIG2_READ 0x50 /* See table below */ 240 #define IC_CONFIG2_SET 0x50 241 #define IC_CONFIG2_CLEAR 0x54 242 243 #define IC_REQUEST0_INT 0x54 /* Show active interrupts on request 0 */ 244 245 #define IC_SOURCE_READ 0x58 /* Interrupt source */ 246 #define IC_SOURCE_SET 0x58 /* 0 - test bit used as source */ 247 #define IC_SOURCE_CLEAR 0x5c /* 1 - peripheral/GPIO used as source */ 248 249 #define IC_REQUEST1_INT 0x5c /* Show active interrupts on request 1 */ 250 251 #define IC_ASSIGN_REQUEST_READ 0x60 /* Assigns the interrupt to one of the */ 252 #define IC_ASSIGN_REQUEST_SET 0x60 /* CPU requests (0 - assign to request 1, */ 253 #define IC_ASSIGN_REQUEST_CLEAR 0x64 /* 1 - assign to request 0) */ 254 255 #define IC_WAKEUP_READ 0x68 /* Controls whether the interrupt can */ 256 #define IC_WAKEUP_SET 0x68 /* cause a wakeup from IDLE */ 257 #define IC_WAKEUP_CLEAR 0x6c 258 259 #define IC_MASK_READ 0x70 /* Enables/Disables the interrupt */ 260 #define IC_MASK_SET 0x70 261 #define IC_MASK_CLEAR 0x74 262 263 #define IC_RISING_EDGE_DETECT 0x78 /* Check/clear rising edge interrupts */ 264 #define IC_RISING_EDGE_DETECT_CLEAR 0x78 265 266 #define IC_FAILLING_EDGE_DETECT 0x7c /* Check/clear falling edge interrupts */ 267 #define IC_FAILLING_EDGE_DETECT_CLEAR 0x7c 268 269 #define IC_TEST_BIT 0x80 /* single bit source select testing register */ 270 271 /* 272 * Interrupt Configuration Register Functions 273 * 274 * Cfg2[n] Cfg1[n] Cfg0[n] Function 275 * 0 0 0 Interrupts Disabled 276 * 0 0 1 Rising Edge Enabled 277 * 0 1 0 Falling Edge Enabled 278 * 0 1 1 Rising and Falling Edge Enabled 279 * 1 0 0 Interrupts Disabled 280 * 1 0 1 High Level Enabled 281 * 1 1 0 Low Level Enabled 282 * 1 1 1 Both Levels and Both Edges Enabled 283 */ 284 285 /************************************************************************/ 286 /********************** Ethernet MAC registers **********************/ 287 /************************************************************************/ 288 289 #define MAC0_BASE 0x10500000 290 #define MAC1_BASE 0x10510000 291 #define MACx_SIZE 0x28 292 293 #define AU1500_MAC0_BASE 0x11500000 /* Grr, difference on Au1500 */ 294 #define AU1500_MAC1_BASE 0x11510000 /* Grr, difference on Au1500 */ 295 296 #define MAC0_ENABLE 0x10520000 297 #define MAC1_ENABLE 0x10520004 298 #define MACENx_SIZE 0x04 299 300 #define AU1500_MAC0_ENABLE 0x11520000 /* Grr, difference on Au1500 */ 301 #define AU1500_MAC1_ENABLE 0x11520004 /* Grr, difference on Au1500 */ 302 303 #define MAC0_DMA_BASE 0x14004000 304 #define MAC1_DMA_BASE 0x14004200 305 #define MACx_DMA_SIZE 0x140 306 307 /************************************************************************/ 308 /******************** Secure Digital registers **********************/ 309 /************************************************************************/ 310 #define SD0_BASE 0x10600000 311 #define SD1_BASE 0x10680000 312 313 /************************************************************************/ 314 /************************* I^2S registers ***************************/ 315 /************************************************************************/ 316 #define I2S_BASE 0x11000000 317 318 /************************************************************************/ 319 /************************** UART registers **************************/ 320 /************************************************************************/ 321 322 #define UART0_BASE 0x11100000 323 #define UART1_BASE 0x11200000 324 #define UART2_BASE 0x11300000 325 #define UART3_BASE 0x11400000 326 327 /************************************************************************/ 328 /************************* SSI registers ****************************/ 329 /************************************************************************/ 330 #define SSI0_BASE 0x11600000 331 #define SSI1_BASE 0x11680000 332 333 /************************************************************************/ 334 /************************ GPIO2 registers ***************************/ 335 /************************************************************************/ 336 #define GPIO2_BASE 0x11700000 337 338 /************************************************************************/ 339 /************************* PCI registers ****************************/ 340 /************************************************************************/ 341 #define PCI_BASE 0x14005000 342 #define PCI_HEADER 0x14005100 343 #define PCI_MEM_BASE 0x400000000ULL 344 #define PCI_IO_BASE 0x500000000ULL 345 #define PCI_CONFIG_BASE 0x600000000ULL 346 347 /************************************************************************/ 348 /****************** Programmable Counter registers ******************/ 349 /************************************************************************/ 350 351 #define SYS_BASE 0x11900000 352 353 #define PC_BASE SYS_BASE 354 355 #define PC_TRIM0 0x00 /* PC0 Divide (16 bits) */ 356 #define PC_COUNTER_WRITE0 0x04 /* set PC0 */ 357 #define PC_MATCH0_0 0x08 /* match counter & interrupt */ 358 #define PC_MATCH1_0 0x0c /* match counter & interrupt */ 359 #define PC_MATCH2_0 0x10 /* match counter & interrupt */ 360 #define PC_COUNTER_CONTROL 0x14 /* Programmable Counter Control */ 361 #define CC_E1S 0x00800000 /* Enable PC1 write status */ 362 #define CC_T1S 0x00100000 /* Trim PC1 write status */ 363 #define CC_M21 0x00080000 /* Match 2 of PC1 write status */ 364 #define CC_M11 0x00040000 /* Match 1 of PC1 write status */ 365 #define CC_M01 0x00020000 /* Match 0 of PC1 write status */ 366 #define CC_C1S 0x00010000 /* PC1 write status */ 367 #define CC_BP 0x00004000 /* Bypass OSC (use GPIO1) */ 368 #define CC_EN1 0x00002000 /* Enable PC1 */ 369 #define CC_BT1 0x00001000 /* Bypass Trim on PC1 */ 370 #define CC_EN0 0x00000800 /* Enable PC0 */ 371 #define CC_BT0 0x00000400 /* Bypass Trim on PC0 */ 372 #define CC_EO 0x00000100 /* Enable Oscillator */ 373 #define CC_E0S 0x00000080 /* Enable PC0 write status */ 374 #define CC_32S 0x00000020 /* 32.768kHz OSC status */ 375 #define CC_T0S 0x00000010 /* Trim PC0 write status */ 376 #define CC_M20 0x00000008 /* Match 2 of PC0 write status */ 377 #define CC_M10 0x00000004 /* Match 1 of PC0 write status */ 378 #define CC_M00 0x00000002 /* Match 0 of PC0 write status */ 379 #define CC_C0S 0x00000001 /* PC0 write status */ 380 #define PC_COUNTER_READ_0 0x40 /* get PC0 */ 381 #define PC_TRIM1 0x44 /* PC1 Divide (16 bits) */ 382 #define PC_COUNTER_WRITE1 0x48 /* set PC1 */ 383 #define PC_MATCH0_1 0x4c /* match counter & interrupt */ 384 #define PC_MATCH1_1 0x50 /* match counter & interrupt */ 385 #define PC_MATCH2_1 0x54 /* match counter & interrupt */ 386 #define PC_COUNTER_READ_1 0x58 /* get PC1 */ 387 388 #define PC_SIZE 0x5c /* size of register set */ 389 #define PC_RATE 32768 /* counter rate is 32.768kHz */ 390 391 /************************************************************************/ 392 /******************* Frequency Generator Registers ******************/ 393 /************************************************************************/ 394 395 #define SYS_FREQCTRL0 (SYS_BASE + 0x20) 396 #define SFC_FRDIV2(f) (f<<22) /* 29:22. Freq Divider 2 */ 397 #define SFC_FE2 (1<<21) /* Freq generator output enable 2 */ 398 #define SFC_FS2 (1<<20) /* Freq generator source 2 */ 399 #define SFC_FRDIV1(f) (f<<12) /* 19:12. Freq Divider 1 */ 400 #define SFC_FE1 (1<<11) /* Freq generator output enable 1 */ 401 #define SFC_FS1 (1<<10) /* Freq generator source 1 */ 402 #define SFC_FRDIV0(f) (f<<2) /* 9:2. Freq Divider 0 */ 403 #define SFC_FE0 2 /* Freq generator output enable 0 */ 404 #define SFC_FS0 1 /* Freq generator source 0 */ 405 406 #define SYS_FREQCTRL1 (SYS_BASE + 0x24) 407 #define SFC_FRDIV5(f) (f<<22) /* 29:22. Freq Divider 5 */ 408 #define SFC_FE5 (1<<21) /* Freq generator output enable 5 */ 409 #define SFC_FS5 (1<<20) /* Freq generator source 5 */ 410 #define SFC_FRDIV4(f) (f<<12) /* 19:12. Freq Divider 4 */ 411 #define SFC_FE4 (1<<11) /* Freq generator output enable 4 */ 412 #define SFC_FS4 (1<<10) /* Freq generator source 4 */ 413 #define SFC_FRDIV3(f) (f<<2) /* 9:2. Freq Divider 3 */ 414 #define SFC_FE3 2 /* Freq generator output enable 3 */ 415 #define SFC_FS3 1 /* Freq generator source 3 */ 416 417 /************************************************************************/ 418 /****************** Clock Source Control Registers ******************/ 419 /************************************************************************/ 420 421 #define SYS_CLKSRC (SYS_BASE + 0x28) 422 #define SCS_ME1(n) (n<<27) /* EXTCLK1 Clock Mux input select */ 423 #define SCS_ME0(n) (n<<22) /* EXTCLK0 Clock Mux input select */ 424 #define SCS_MPC(n) (n<<17) /* PCI clock mux input select */ 425 #define SCS_MUH(n) (n<<12) /* USB Host clock mux input select */ 426 #define SCS_MUD(n) (n<<7) /* USB Device clock mux input select */ 427 #define SCS_MEx_AUX 0x1 /* Aux clock */ 428 #define SCS_MEx_FREQ0 0x2 /* FREQ0 */ 429 #define SCS_MEx_FREQ1 0x3 /* FREQ1 */ 430 #define SCS_MEx_FREQ2 0x4 /* FREQ2 */ 431 #define SCS_MEx_FREQ3 0x5 /* FREQ3 */ 432 #define SCS_MEx_FREQ4 0x6 /* FREQ4 */ 433 #define SCS_MEx_FREQ5 0x7 /* FREQ5 */ 434 #define SCS_DE1 (1<<26) /* EXTCLK1 clock divider select */ 435 #define SCS_CE1 (1<<25) /* EXTCLK1 clock select */ 436 #define SCS_DE0 (1<<21) /* EXTCLK0 clock divider select */ 437 #define SCS_CE0 (1<<20) /* EXTCLK0 clock select */ 438 #define SCS_DPC (1<<16) /* PCI clock divider select */ 439 #define SCS_CPC (1<<15) /* PCI clock select */ 440 #define SCS_DUH (1<<11) /* USB Host clock divider select */ 441 #define SCS_CUH (1<<10) /* USB Host clock select */ 442 #define SCS_DUD (1<<6) /* USB Device clock divider select */ 443 #define SCS_CUD (1<<5) /* USB Device clock select */ 444 445 /************************************************************************/ 446 /*************************** PLL Control *****************************/ 447 /************************************************************************/ 448 449 #define SYS_CPUPLL (SYS_BASE + 0x60) 450 #define SYS_AUXPLL (SYS_BASE + 0x64) 451
Indexes created Thu Oct 16 14:10:15 GMT 2025