aureg.h revision 1.3
1 /* $NetBSD: aureg.h,v 1.3 2003/04/01 17:30:09 hpeyerl Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* ********************************************************************* 39 * Naming schemes for constants in these files: 40 * 41 * M_xxx MASK constant (identifies bits in a register). 42 * For multi-bit fields, all bits in the field will 43 * be set. 44 * 45 * K_xxx "Code" constant (value for data in a multi-bit 46 * field). The value is right justified. 47 * 48 * V_xxx "Value" constant. This is the same as the 49 * corresponding "K_xxx" constant, except it is 50 * shifted to the correct position in the register. 51 * 52 * S_xxx SHIFT constant. This is the number of bits that 53 * a field value (code) needs to be shifted 54 * (towards the left) to put the value in the right 55 * position for the register. 56 * 57 * A_xxx ADDRESS constant. This will be a physical 58 * address. Use the MIPS_PHYS_TO_KSEG1 macro to 59 * generate a K1SEG address. 60 * 61 * R_xxx RELATIVE offset constant. This is an offset from 62 * an A_xxx constant (usually the first register in 63 * a group). 64 * 65 * G_xxx(X) GET value. This macro obtains a multi-bit field 66 * from a register, masks it, and shifts it to 67 * the bottom of the register (retrieving a K_xxx 68 * value, for example). 69 * 70 * V_xxx(X) VALUE. This macro computes the value of a 71 * K_xxx constant shifted to the correct position 72 * in the register. 73 ********************************************************************* */ 74 75 #if !defined(__ASSEMBLER__) 76 #define _MAKE64(x) ((uint64_t)(x)) 77 #define _MAKE32(x) ((uint32_t)(x)) 78 #else 79 #define _MAKE64(x) (x) 80 #define _MAKE32(x) (x) 81 #endif 82 83 /* Make a mask for 1 bit at position 'n' */ 84 #define _MAKEMASK1_64(n) (_MAKE64(1) << _MAKE64(n)) 85 #define _MAKEMASK1_32(n) (_MAKE32(1) << _MAKE32(n)) 86 87 /* Make a mask for 'v' bits at position 'n' */ 88 #define _MAKEMASK_64(v,n) (_MAKE64((_MAKE64(1)<<(v))-1) << _MAKE64(n)) 89 #define _MAKEMASK_32(v,n) (_MAKE32((_MAKE32(1)<<(v))-1) << _MAKE32(n)) 90 91 /* Make a value at 'v' at bit position 'n' */ 92 #define _MAKEVALUE_64(v,n) (_MAKE64(v) << _MAKE64(n)) 93 #define _MAKEVALUE_32(v,n) (_MAKE32(v) << _MAKE32(n)) 94 95 #define _GETVALUE_64(v,n,m) ((_MAKE64(v) & _MAKE64(m)) >> _MAKE64(n)) 96 #define _GETVALUE_32(v,n,m) ((_MAKE32(v) & _MAKE32(m)) >> _MAKE32(n)) 97 98 99 /************************************************************************/ 100 /******************** AC97 Controller registers *********************/ 101 /************************************************************************/ 102 #define AC97_BASE 0x10000000 103 104 #define AC97_CONFIG 0x00 105 106 #define M_AC97CFG_RS _MAKEMASK1_32(0) 107 #define M_AC97CFG_SN _MAKEMASK1_32(1) 108 #define M_AC97CFG_SG _MAKEMASK1_32(2) 109 110 #define S_AC97CFG_XS _MAKE32(12) 111 #define M_AC97CFG_XS _MAKEMASK_32(10) 112 #define V_AC97CFG_XS(x) _MAKEVALUE_32(x, S_AC97CFG_XS) 113 #define G_AC97CFG_XS(x) _GETVALUE_32(x, S_AC97CFG_XS, M_AC97CFG_XS) 114 115 #define S_AC97CFG_RC _MAKE32(12) 116 #define M_AC97CFG_RC _MAKEMASK_32(10) 117 #define V_AC97CFG_RC(x) _MAKEVALUE_32(x, S_AC97CFG_RC) 118 #define G_AC97CFG_RC(x) _GETVALUE_32(x, S_AC97CFG_RC, M_AC97CFG_RC) 119 120 #define AC97_STATUS 0x04 121 122 #define M_AC97STAT_RF _MAKEMASK1_32(0) 123 #define M_AC97STAT_RE _MAKEMASK1_32(1) 124 #define M_AC97STAT_TF _MAKEMASK1_32(3) 125 #define M_AC97STAT_TE _MAKEMASK1_32(4) 126 #define M_AC97STAT_CP _MAKEMASK1_32(6) 127 #define M_AC97STAT_RD _MAKEMASK1_32(7) 128 #define M_AC97STAT_RO _MAKEMASK1_32(8) 129 #define M_AC97STAT_RU _MAKEMASK1_32(9) 130 #define M_AC97STAT_XO _MAKEMASK1_32(10) 131 #define M_AC97STAT_XU _MAKEMASK1_32(11) 132 133 #define AC97_DATA 0x08 134 135 #define S_AC97DATA_DATA _MAKE32(0) 136 #define M_AC97DATA_DATA _MAKEMASK_32(16) 137 #define V_AC97DATA_DATA(x) _MAKEVALUE_32(x, S_AC97DATA_DATA) 138 #define G_AC97DATA_DATA(x) _GETVALUE_32(x, S_AC97DATA_DATA, M_AC97DATA_DATA) 139 140 #define AC97_COMMAND 0x0c 141 142 #define S_AC97CMD_INDEX _MAKE32(0) 143 #define M_AC97CMD_INDEX _MAKEMASK_32(7) 144 #define V_AC97CMD_INDEX(x) _MAKEVALUE_32(x, S_AC97CMD_INDEX) 145 #define G_AC97CMD_INDEX(x) _GETVALUE_32(x, S_AC97CMD_INDEX, M_AC97CMD_INDEX) 146 147 #define M_AC97CMD_RW _MAKEMASK1_32(7) 148 149 #define S_AC97CMD_DATA _MAKE32(16) 150 #define M_AC97CMD_DATA _MAKEMASK_32(16) 151 #define V_AC97CMD_DATA(x) _MAKEVALUE_32(x, S_AC97CMD_DATA) 152 #define G_AC97CMD_DATA(x) _GETVALUE_32(x, S_AC97CMD_DATA, M_AC97CMD_DATA) 153 154 #define AC97_COMMAND_RESPONSE 0x0c 155 156 #define S_AC97CMDRESP_DATA _MAKE32(0) 157 #define M_AC97CMDRESP_DATA _MAKEMASK_32(16) 158 #define V_AC97CMDRESP_DATA(x) _MAKEVALUE_32(x, S_AC97CMDRESP_DATA) 159 #define G_AC97CMDRESP_DATA(x) _GETVALUE_32(x, S_AC97CMDRESP_DATA, M_AC97CMDRESP_DATA) 160 161 #define AC97_ENABLE 0x10 162 163 #define M_AC97EN_CE _MAKEMASK1_32(0) 164 #define M_AC97EN_D _MAKEMASK1_32(1) 165 166 #define AC97_SIZE 0x14 /* size of register set */ 167 168 /************************************************************************/ 169 /*********************** USB Host registers *************************/ 170 /************************************************************************/ 171 #define USBH_BASE 0x10100000 172 173 #define USBH_ENABLE 0x7fffc 174 #define UE_RD 0x00000010 /* reset done */ 175 #define UE_CE 0x00000008 /* clock enable */ 176 #define UE_E 0x00000004 /* enable */ 177 #define UE_C 0x00000002 /* coherent */ 178 #define UE_BE 0x00000001 /* big-endian */ 179 180 #define USBH_SIZE 0x80000 /* size of register set */ 181 182 /************************************************************************/ 183 /********************** USB Device registers ************************/ 184 /************************************************************************/ 185 #define USBD_BASE 0x10200000 186 187 /************************************************************************/ 188 /************************* IRDA registers ***************************/ 189 /************************************************************************/ 190 #define IRDA_BASE 0x10300000 191 192 /************************************************************************/ 193 /****************** Interrupt Controller registers ******************/ 194 /************************************************************************/ 195 196 #define IC0_BASE 0x10400000 197 #define IC1_BASE 0x11800000 198 199 /* 200 * The *_READ registers read the current value of the register 201 * The *_SET registers set to 1 all bits that are written 1 202 * The *_CLEAR registers clear to zero all bits that are written as 1 203 */ 204 #define IC_CONFIG0_READ 0x40 /* See table below */ 205 #define IC_CONFIG0_SET 0x40 206 #define IC_CONFIG0_CLEAR 0x44 207 208 #define IC_CONFIG1_READ 0x48 /* See table below */ 209 #define IC_CONFIG1_SET 0x48 210 #define IC_CONFIG1_CLEAR 0x4c 211 212 #define IC_CONFIG2_READ 0x50 /* See table below */ 213 #define IC_CONFIG2_SET 0x50 214 #define IC_CONFIG2_CLEAR 0x54 215 216 #define IC_REQUEST0_INT 0x54 /* Show active interrupts on request 0 */ 217 218 #define IC_SOURCE_READ 0x58 /* Interrupt source */ 219 #define IC_SOURCE_SET 0x58 /* 0 - test bit used as source */ 220 #define IC_SOURCE_CLEAR 0x5c /* 1 - peripheral/GPIO used as source */ 221 222 #define IC_REQUEST1_INT 0x5c /* Show active interrupts on request 1 */ 223 224 #define IC_ASSIGN_REQUEST_READ 0x60 /* Assigns the interrupt to one of the */ 225 #define IC_ASSIGN_REQUEST_SET 0x60 /* CPU requests (0 - assign to request 1, */ 226 #define IC_ASSIGN_REQUEST_CLEAR 0x64 /* 1 - assign to request 0) */ 227 228 #define IC_WAKEUP_READ 0x68 /* Controls whether the interrupt can */ 229 #define IC_WAKEUP_SET 0x68 /* cause a wakeup from IDLE */ 230 #define IC_WAKEUP_CLEAR 0x6c 231 232 #define IC_MASK_READ 0x70 /* Enables/Disables the interrupt */ 233 #define IC_MASK_SET 0x70 234 #define IC_MASK_CLEAR 0x74 235 236 #define IC_RISING_EDGE_DETECT 0x78 /* Check/clear rising edge interrupts */ 237 #define IC_RISING_EDGE_DETECT_CLEAR 0x78 238 239 #define IC_FAILLING_EDGE_DETECT 0x7c /* Check/clear falling edge interrupts */ 240 #define IC_FAILLING_EDGE_DETECT_CLEAR 0x7c 241 242 #define IC_TEST_BIT 0x80 /* single bit source select testing register */ 243 244 /* 245 * Interrupt Configuration Register Functions 246 * 247 * Cfg2[n] Cfg1[n] Cfg0[n] Function 248 * 0 0 0 Interrupts Disabled 249 * 0 0 1 Rising Edge Enabled 250 * 0 1 0 Falling Edge Enabled 251 * 0 1 1 Rising and Falling Edge Enabled 252 * 1 0 0 Interrupts Disabled 253 * 1 0 1 High Level Enabled 254 * 1 1 0 Low Level Enabled 255 * 1 1 1 Both Levels and Both Edges Enabled 256 */ 257 258 /************************************************************************/ 259 /********************** Ethernet MAC registers **********************/ 260 /************************************************************************/ 261 262 #define MAC0_BASE 0x10500000 263 #define MAC1_BASE 0x10510000 264 #define MACx_SIZE 0x28 265 266 #define AU1500_MAC0_BASE 0x11500000 /* Grr, difference on Au1500 */ 267 #define AU1500_MAC1_BASE 0x11510000 /* Grr, difference on Au1500 */ 268 269 #if 0 270 #define MAC_CONTROL 0x00 /* operation mode and address filter */ 271 #define MC_RA 0x80000000 /* Receive All */ 272 #define MC_EM 0x40000000 /* Endian Mode - data buffer is big endian */ 273 #define MC_DRO 0x00800000 /* Disable Receive Own */ 274 #define MC_LM_MASK 0x00600000 /* Loopback Operating Mode - mask */ 275 #define MC_LM_NORMAL 0x00600000 276 #define MC_LM_INTERNAL 0x00400000 277 #define MC_LM_EXTERNAL 0x00200000 278 #define MC_F 0x00100000 /* Full duplex mode */ 279 #define MC_PM 0x00080000 /* Pall all Multicast */ 280 #define MC_PR 0x00040000 /* Promiscious Mode */ 281 #define MC_IF 0x00020000 /* Inverse Filtering */ 282 #define MC_PB 0x00010000 /* Pass Bad frames */ 283 #define MC_HO 0x00008000 /* Hash Only filtering mode */ 284 #define MC_HP 0x00002000 /* Hash/Perfect filtering mode */ 285 #define MC_LC 0x00001000 /* Late Collision control */ 286 #define MC_DB 0x00000800 /* Disable Broadcast frames */ 287 #define MC_DR 0x00000400 /* Disable Retry */ 288 #define MC_AP 0x00000100 /* Automatic Pad stripping */ 289 #define MC_BL_MASK 0x000000c0 /* Backoff Limit mask */ 290 #define MC_BL_SHIFT 6 291 #define MC_DC 0x00000020 /* Deferral Check */ 292 #define MC_TE 0x00000008 /* Transmitter Enable */ 293 #define MC_RE 0x00000004 /* Receiver Enable */ 294 #define MAC_ADDRESS_HIGH 0x04 /* high 16 bits of the MAC address */ 295 #define MAC_ADDRESS_LOW 0x08 /* lower 32 bits of the MAC address */ 296 #define MAC_MCAST_HASH_HIGH 0x0c /* high 16 bits of mcat hash address */ 297 #define MAC_MCAST_HASH_LOW 0x10 /* low 32 bits of mcat hash address */ 298 #define MAC_MII_CONTROL 0x14 /* control of PHY management interface */ 299 #define MMC_PHY_ADDR_MASK 0x0000f800 /* PHY Address mask */ 300 #define MMC_PHY_ADDR_SHIFT 11 301 #define MMC_MIIREG_MASK 0x000007c0 /* MII Register mask */ 302 #define MMC_MIIREG_SHIFT 6 303 #define MMC_MW 0x00000002 /* MII Write */ 304 #define MMC_MB 0x00000001 /* MII Busy */ 305 #define MAC_MII_DATA 0x18 /* data to/from PHY */ 306 #define MAC_FLOW_CONTROL 0x1c /* frame generation control */ 307 #define MFC_PT_MASK 0xffff0000 /* Pause Time mask */ 308 #define MFC_PT_SHIFT 16 309 #define MFC_PC 0x00000004 /* Pass Control frame */ 310 #define MFC_FE 0x00000002 /* Flow Control enable */ 311 #define MFC_FB 0x00000001 /* Flow control Busy */ 312 #define MAC_VLAN1_TAG 0x20 /* VLAN1 tag */ 313 #define MAC_VLAN2_TAG 0x24 /* VLAN2 tag */ 314 #endif 315 316 #define MAC0_ENABLE 0x10520000 317 #define MAC1_ENABLE 0x10520004 318 #define MACENx_SIZE 0x04 319 320 #define AU1500_MAC0_ENABLE 0x11520000 /* Grr, difference on Au1500 */ 321 #define AU1500_MAC1_ENABLE 0x11520004 /* Grr, difference on Au1500 */ 322 323 #if 0 324 #define ME_DR 0x40 /* DMA reset */ 325 #define ME_R2 0x20 /* Reset2 */ 326 #define ME_R1 0x10 /* Reset1 */ 327 #define ME_C 0x08 /* Cacheable */ 328 #define ME_TS 0x04 /* Toss */ 329 #define ME_R0 0x02 /* Reset0 */ 330 #define ME_EN 0x01 /* Clock Enable */ 331 #endif 332 333 #define MAC0_DMA_BASE 0x14004000 334 #define MAC1_DMA_BASE 0x14004200 335 #define MACx_DMA_SIZE 0x140 336 #if 0 337 #define MAC_TXDMA 0x000 338 #define MAC_RXDMA 0x100 339 #define MAC_TXQLEN 4 340 #define MAC_RXQLEN 4 341 342 /* MAC Transmit Status registers */ 343 #define MTS_PR 0x80000000 /* Packet Retry */ 344 #define MTS_HB 0x00004000 /* ?!?? */ 345 #define MTS_CC_MASK 0x00003c00 /* Collision Count mask */ 346 #define MTS_CC_SHIFT 10 347 #define MTS_LO 0x00000200 /* Late collision Observed */ 348 #define MTS_DF 0x00000100 /* Deferred */ 349 #define MTS_UR 0x00000080 /* Underrun */ 350 #define MTS_EC 0x00000040 /* Excessive Collisions */ 351 #define MTS_LC 0x00000020 /* Late Collision */ 352 #define MTS_ED 0x00000010 /* Excessive Deferral */ 353 #define MFS_LS 0x00000008 /* LoSs of carrier */ 354 #define MFS_NC 0x00000004 /* No Carrier */ 355 #define MFS_JT 0x00000002 /* Jabber Timeout */ 356 #define MFS_FA 0x00000001 /* Frame Aborted */ 357 358 /* MAC Transmit Buffer Address/Enable registers */ 359 #define MTBAE_ADDR_MASK 0xffffffe0 /* Buffer address */ 360 #define MTBAE_CB_MASK 0x0000000c /* Current (DMA) Buffer */ 361 #define MTBAE_CB_SHIFT 2 362 #define MTBAE_DONE 0x00000002 /* transation DONE */ 363 #define MTBAE_EN 0x00000001 /* MAC DMA Enable */ 364 365 /* MAC Transmit Buffer Length registers */ 366 #define MTBL_LEN_MASK 0x000007ff /* buffer LENgth */ 367 #define MTBL_LEN_SHIFT 0 368 369 /* MAC Receive Status registers */ 370 #define MRS_MI 0x80000000 /* MIssed frame */ 371 #define MRS_PF 0x40000000 /* Packet Filter */ 372 #define MRS_FF 0x20000000 /* Filtering Fail */ 373 #define MRS_BF 0x10000000 /* Broadcast Frame */ 374 #define MRS_MF 0x08000000 /* Multicast Frame */ 375 #define MRS_UC 0x04000000 /* Unsupported Control frame */ 376 #define MRS_CF 0x02000000 /* Control Frame */ 377 #define MRS_LE 0x01000000 /* Length Error */ 378 #define MRS_V2 0x00800000 /* Vlan2 ID */ 379 #define MRS_V1 0x00400000 /* Vlan1 ID */ 380 #define MRS_CR 0x00200000 /* CRC error */ 381 #define MRS_DB 0x00100000 /* Dribbling Bit */ 382 #define MRS_ME 0x00080000 /* MII Error */ 383 #define MRS_FT 0x00040000 /* Frame Type */ 384 #define MRS_CS 0x00020000 /* Collision Seen */ 385 #define MRS_FL 0x00010000 /* Frame too Long */ 386 #define MRS_RF 0x00008000 /* Runt Frame */ 387 #define MRS_WT 0x00004000 /* Watchdog Timeout */ 388 #define MRS_L_MASK 0x00003fff /* frame Length mask*/ 389 #define MRS_L_SHIFT 0 390 391 /* MAC Receive Buffer Address/Enable registers */ 392 #define MRBAE_ADDR_MASK 0xffffffe0 /* Buffer address */ 393 #define MRBAE_CB_MASK 0x0000000c /* Current (DMA) Buffer */ 394 #define MRBAE_CB_SHIFT 2 395 #define MRBAE_DN 0x00000002 /* transation DoNe */ 396 #define MRBAE_EN 0x00000001 /* MAC DMA Enable */ 397 #endif 398 399 /************************************************************************/ 400 /******************** Secure Digital registers **********************/ 401 /************************************************************************/ 402 #define SD0_BASE 0x10600000 403 #define SD1_BASE 0x10680000 404 405 /************************************************************************/ 406 /************************* I^2S registers ***************************/ 407 /************************************************************************/ 408 #define I2S_BASE 0x11000000 409 410 /************************************************************************/ 411 /************************** UART registers **************************/ 412 /************************************************************************/ 413 414 #define UART0_BASE 0x11100000 415 #define UART1_BASE 0x11200000 416 #define UART2_BASE 0x11300000 417 #define UART3_BASE 0x11400000 418 419 #define UART_RXDATA 0x000 /* Received Data FIFO (R) */ 420 #define UART_TXDATA 0x004 /* Transmit Data FIFO (W) */ 421 #define UART_INTERRUPT_ENABLE 0x008 /* Interrupt Enable Register (R/W) */ 422 #define UIE_MIE 0x8 /* Modem Status Interrupt enable */ 423 #define UIE_LIE 0x4 /* Line Status Interrupt enable */ 424 #define UIE_TIE 0x2 /* Transmit Interrupt Enable */ 425 #define UIE_RIE 0x1 /* Receive Interrupt Enable */ 426 #define UART_INTERRUPT_CAUSE 0x00c /* Pending Interrupt Cause Register (R) */ 427 #define UIC_IID_MASK 0xe /* mask for Interrupt IDentifier */ 428 #define UIC_IID_MS 0x0 /* Modem Status */ 429 #define UIC_IID_TBA 0x2 /* Transmit Buffer Available */ 430 #define UIC_IID_RDA 0x4 /* Receive Data Available */ 431 #define UIC_IID_RLS 0x6 /* Receive Line Status */ 432 #define UIC_IID_CTO 0xc /* Character Time Out */ 433 #define UIC_IP 0x1 /* XXX-no?-XXX Interrupt Pending */ 434 #define UART_FIFO_CONTROL 0x010 /* FIFO Control Register (W) */ 435 #define UFC_RFT_0 0x00 /* Receiver FIFO Threshold of 0 chars */ 436 #define UFC_RFT_4 0x40 /* Receiver FIFO Threshold of 4 chars */ 437 #define UFC_RFT_8 0x80 /* Receiver FIFO Threshold of 8 chars */ 438 #define UFC_RFT_12 0xc0 /* Receiver FIFO Threshold of 12 chars */ 439 #define UFC_TFT_0 0x00 /* Transmit FIFO Threshold of 0 chars */ 440 #define UFC_TFT_4 0x10 /* Transmit FIFO Threshold of 4 chars */ 441 #define UFC_TFT_8 0x20 /* Transmit FIFO Threshold of 8 chars */ 442 #define UFC_TFT_12 0x30 /* Transmit FIFO Threshold of 12 chars */ 443 #define UFC_MS 0x08 /* Mode Select */ 444 #define UFC_TR 0x04 /* Transmitter Reset */ 445 #define UFC_RR 0x02 /* Receiver Reset */ 446 #define UFC_FE 0x01 /* FIFO Enable */ 447 #define UART_LINE_CONTROL 0x014 /* Line Control Register (R/W) */ 448 #define ULC_SB 0x40 /* Send Break */ 449 #define ULC_PAR_MASK 0x30 /* mask for PARity select */ 450 #define ULC_PAR_ODD 0x00 /* odd parity */ 451 #define ULC_PAR_EVEN 0x10 /* even parity */ 452 #define ULC_PAR_MARK 0x20 /* mark parity */ 453 #define ULC_PAR_ZERO 0x30 /* zero parity */ 454 #define ULC_PE 0x08 /* Parity Enable */ 455 #define ULC_ST 0x04 /* 1.5 or 2 stop bits */ 456 #define ULC_WLS_MASK 0x03 /* mask for Word Length Select */ 457 #define ULC_WLS_5 0x00 /* 5 bits per serial word */ 458 #define ULC_WLS_6 0x01 /* 6 bits */ 459 #define ULC_WLS_7 0x02 /* 7 bits */ 460 #define ULC_WLS_8 0x03 /* 8 bits */ 461 #define UART_MODEM_CONTROL 0x018 /* Modem Line Control Register (UART 4 only) (R/W) */ 462 #define UMC_LB 0x10 /* Loop Back */ 463 #define UMC_X2 0x08 /* eXternal line 2 state */ 464 #define UMC_X1 0x04 /* eXternal line 1 state */ 465 #define UMC_RT 0x02 /* Request To send */ 466 #define UMC_DT 0x01 /* Data Terminal ready */ 467 #define UART_LINE_STATUS 0x01c /* Line Status Register (R/W) */ 468 #define ULS_RF 0x80 /* Receiver FIFO contains error */ 469 #define ULS_TE 0x40 /* Transmit shift register Empty */ 470 #define ULS_TFE 0x20 /* Transmit FIFO Empty */ 471 #define ULS_BI 0x10 /* Break Indication */ 472 #define ULS_FE 0x08 /* Framing Error */ 473 #define ULS_PE 0x04 /* Parity Error */ 474 #define ULS_OE 0x02 /* Overrun Error */ 475 #define ULS_DR 0x01 /* Data Ready */ 476 #define ULS_RCV_MASK 0x1f /* mask for incoming data or error */ 477 #define UART_MODEM_STATUS 0x020 /* Modem Line Status Register (UART 4 only) (R/W) */ 478 #define UMS_CD 0x80 /* data Carrier Detect */ 479 #define UMS_RI 0x40 /* Ring Indication */ 480 #define UMS_DS 0x20 /* Data Set ready */ 481 #define UMS_CT 0x10 /* Clear To send */ 482 #define UMS_DD 0x08 /* Delta DCD */ 483 #define UMS_TRI 0x04 /* Terminate Ring Indication */ 484 #define UMS_DR 0x02 /* Delta DSR */ 485 #define UMS_DC 0x01 /* Delta CTS */ 486 #define UART_CLOCK_DIVIDER 0x028 /* Baud Rate Clock Divider (16bit) */ 487 #define UART_MODULE_CONTROL 0x100 /* Module Control Register */ 488 #define UMC_CE 0x2 /* Module Clock Enable */ 489 #define UMC_ME 0x1 /* Module Enable */ 490 491 /************************************************************************/ 492 /************************* SSI registers ****************************/ 493 /************************************************************************/ 494 #define SSI0_BASE 0x11600000 495 #define SSI1_BASE 0x11680000 496 497 /************************************************************************/ 498 /************************ GPIO2 registers ***************************/ 499 /************************************************************************/ 500 #define GPIO2_BASE 0x11700000 501 502 /************************************************************************/ 503 /****************** Programmable Counter registers ******************/ 504 /************************************************************************/ 505 506 #define SYS_BASE 0x11900000 507 508 #define PC_BASE SYS_BASE 509 510 #define PC_TRIM0 0x00 /* PC0 Divide (16 bits) */ 511 #define PC_COUNTER_WRITE0 0x04 /* set PC0 */ 512 #define PC_MATCH0_0 0x08 /* match counter & interrupt */ 513 #define PC_MATCH1_0 0x0c /* match counter & interrupt */ 514 #define PC_MATCH2_0 0x10 /* match counter & interrupt */ 515 #define PC_COUNTER_CONTROL 0x14 /* Programmable Counter Control */ 516 #define CC_E1S 0x00800000 /* Enable PC1 write status */ 517 #define CC_T1S 0x00100000 /* Trim PC1 write status */ 518 #define CC_M21 0x00080000 /* Match 2 of PC1 write status */ 519 #define CC_M11 0x00040000 /* Match 1 of PC1 write status */ 520 #define CC_M01 0x00020000 /* Match 0 of PC1 write status */ 521 #define CC_C1S 0x00010000 /* PC1 write status */ 522 #define CC_BP 0x00004000 /* Bypass OSC (use GPIO1) */ 523 #define CC_EN1 0x00002000 /* Enable PC1 */ 524 #define CC_BT1 0x00001000 /* Bypass Trim on PC1 */ 525 #define CC_EN0 0x00000800 /* Enable PC0 */ 526 #define CC_BT0 0x00000400 /* Bypass Trim on PC0 */ 527 #define CC_EO 0x00000100 /* Enable Oscillator */ 528 #define CC_E0S 0x00000080 /* Enable PC0 write status */ 529 #define CC_32S 0x00000020 /* 32.768kHz OSC status */ 530 #define CC_T0S 0x00000010 /* Trim PC0 write status */ 531 #define CC_M20 0x00000008 /* Match 2 of PC0 write status */ 532 #define CC_M10 0x00000004 /* Match 1 of PC0 write status */ 533 #define CC_M00 0x00000002 /* Match 0 of PC0 write status */ 534 #define CC_C0S 0x00000001 /* PC0 write status */ 535 #define PC_COUNTER_READ_0 0x40 /* get PC0 */ 536 #define PC_TRIM1 0x44 /* PC1 Divide (16 bits) */ 537 #define PC_COUNTER_WRITE1 0x48 /* set PC1 */ 538 #define PC_MATCH0_1 0x4c /* match counter & interrupt */ 539 #define PC_MATCH1_1 0x50 /* match counter & interrupt */ 540 #define PC_MATCH2_1 0x54 /* match counter & interrupt */ 541 #define PC_COUNTER_READ_1 0x58 /* get PC1 */ 542 543 #define PC_SIZE 0x5c /* size of register set */ 544 #define PC_RATE 32768 /* counter rate is 32.768kHz */ 545 546 /************************************************************************/ 547 /******************* Frequency Generator Registers ******************/ 548 /************************************************************************/ 549 550 #define SYS_FREQCTRL0 (SYS_BASE + 0x20) 551 #define SFC_FRDIV2(f) (f<<22) /* 29:22. Freq Divider 2 */ 552 #define SFC_FE2 (1<<21) /* Freq generator output enable 2 */ 553 #define SFC_FS2 (1<<20) /* Freq generator source 2 */ 554 #define SFC_FRDIV1(f) (f<<12) /* 19:12. Freq Divider 1 */ 555 #define SFC_FE1 (1<<11) /* Freq generator output enable 1 */ 556 #define SFC_FS1 (1<<10) /* Freq generator source 1 */ 557 #define SFC_FRDIV0(f) (f<<2) /* 9:2. Freq Divider 0 */ 558 #define SFC_FE0 2 /* Freq generator output enable 0 */ 559 #define SFC_FS0 1 /* Freq generator source 0 */ 560 561 #define SYS_FREQCTRL1 (SYS_BASE + 0x24) 562 #define SFC_FRDIV5(f) (f<<22) /* 29:22. Freq Divider 5 */ 563 #define SFC_FE5 (1<<21) /* Freq generator output enable 5 */ 564 #define SFC_FS5 (1<<20) /* Freq generator source 5 */ 565 #define SFC_FRDIV4(f) (f<<12) /* 19:12. Freq Divider 4 */ 566 #define SFC_FE4 (1<<11) /* Freq generator output enable 4 */ 567 #define SFC_FS4 (1<<10) /* Freq generator source 4 */ 568 #define SFC_FRDIV3(f) (f<<2) /* 9:2. Freq Divider 3 */ 569 #define SFC_FE3 2 /* Freq generator output enable 3 */ 570 #define SFC_FS3 1 /* Freq generator source 3 */ 571 572 /************************************************************************/ 573 /****************** Clock Source Control Registers ******************/ 574 /************************************************************************/ 575 576 #define SYS_CLKSRC (SYS_BASE + 0x28) 577 #define SCS_ME1(n) (n<<27) /* EXTCLK1 Clock Mux input select */ 578 #define SCS_ME0(n) (n<<22) /* EXTCLK0 Clock Mux input select */ 579 #define SCS_MPC(n) (n<<17) /* PCI clock mux input select */ 580 #define SCS_MUH(n) (n<<12) /* USB Host clock mux input select */ 581 #define SCS_MUD(n) (n<<7) /* USB Device clock mux input select */ 582 #define SCS_MEx_AUX 0x1 /* Aux clock */ 583 #define SCS_MEx_FREQ0 0x2 /* FREQ0 */ 584 #define SCS_MEx_FREQ1 0x3 /* FREQ1 */ 585 #define SCS_MEx_FREQ2 0x4 /* FREQ2 */ 586 #define SCS_MEx_FREQ3 0x5 /* FREQ3 */ 587 #define SCS_MEx_FREQ4 0x6 /* FREQ4 */ 588 #define SCS_MEx_FREQ5 0x7 /* FREQ5 */ 589 #define SCS_DE1 (1<<26) /* EXTCLK1 clock divider select */ 590 #define SCS_CE1 (1<<25) /* EXTCLK1 clock select */ 591 #define SCS_DE0 (1<<21) /* EXTCLK0 clock divider select */ 592 #define SCS_CE0 (1<<20) /* EXTCLK0 clock select */ 593 #define SCS_DPC (1<<16) /* PCI clock divider select */ 594 #define SCS_CPC (1<<15) /* PCI clock select */ 595 #define SCS_DUH (1<<11) /* USB Host clock divider select */ 596 #define SCS_CUH (1<<10) /* USB Host clock select */ 597 #define SCS_DUD (1<<6) /* USB Device clock divider select */ 598 #define SCS_CUD (1<<5) /* USB Device clock select */ 599 600 /************************************************************************/ 601 /*************************** PLL Control *****************************/ 602 /************************************************************************/ 603 604 #define SYS_CPUPLL (SYS_BASE + 0x60) 605 #define SYS_AUXPLL (SYS_BASE + 0x64) 606
Indexes created Wed Sep 24 22:09:59 GMT 2025