aevar.h revision 1.2.4.2 1 1.2.4.2 rpaulo /* $NetBSD: aevar.h,v 1.2.4.2 2006/09/09 02:41:25 rpaulo Exp $ */
2 1.2.4.2 rpaulo
3 1.2.4.2 rpaulo /*-
4 1.2.4.2 rpaulo * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
5 1.2.4.2 rpaulo * All rights reserved.
6 1.2.4.2 rpaulo *
7 1.2.4.2 rpaulo * This code is derived from software contributed to The NetBSD Foundation
8 1.2.4.2 rpaulo * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.2.4.2 rpaulo * NASA Ames Research Center.
10 1.2.4.2 rpaulo *
11 1.2.4.2 rpaulo * Redistribution and use in source and binary forms, with or without
12 1.2.4.2 rpaulo * modification, are permitted provided that the following conditions
13 1.2.4.2 rpaulo * are met:
14 1.2.4.2 rpaulo * 1. Redistributions of source code must retain the above copyright
15 1.2.4.2 rpaulo * notice, this list of conditions and the following disclaimer.
16 1.2.4.2 rpaulo * 2. Redistributions in binary form must reproduce the above copyright
17 1.2.4.2 rpaulo * notice, this list of conditions and the following disclaimer in the
18 1.2.4.2 rpaulo * documentation and/or other materials provided with the distribution.
19 1.2.4.2 rpaulo * 3. All advertising materials mentioning features or use of this software
20 1.2.4.2 rpaulo * must display the following acknowledgement:
21 1.2.4.2 rpaulo * This product includes software developed by the NetBSD
22 1.2.4.2 rpaulo * Foundation, Inc. and its contributors.
23 1.2.4.2 rpaulo * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.2.4.2 rpaulo * contributors may be used to endorse or promote products derived
25 1.2.4.2 rpaulo * from this software without specific prior written permission.
26 1.2.4.2 rpaulo *
27 1.2.4.2 rpaulo * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.2.4.2 rpaulo * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.2.4.2 rpaulo * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.2.4.2 rpaulo * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.2.4.2 rpaulo * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.2.4.2 rpaulo * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.2.4.2 rpaulo * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.2.4.2 rpaulo * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.2.4.2 rpaulo * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.2.4.2 rpaulo * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.2.4.2 rpaulo * POSSIBILITY OF SUCH DAMAGE.
38 1.2.4.2 rpaulo */
39 1.2.4.2 rpaulo
40 1.2.4.2 rpaulo #ifndef _MIPS_ATHEROS_DEV_AEVAR_H_
41 1.2.4.2 rpaulo #define _MIPS_ATHEROS_DEV_AEVAR_H_
42 1.2.4.2 rpaulo
43 1.2.4.2 rpaulo #include "rnd.h"
44 1.2.4.2 rpaulo
45 1.2.4.2 rpaulo #include <sys/queue.h>
46 1.2.4.2 rpaulo #include <sys/callout.h>
47 1.2.4.2 rpaulo
48 1.2.4.2 rpaulo #if NRND > 0
49 1.2.4.2 rpaulo #include <sys/rnd.h>
50 1.2.4.2 rpaulo #endif
51 1.2.4.2 rpaulo
52 1.2.4.2 rpaulo /*
53 1.2.4.2 rpaulo * Misc. definitions for the Digital Semiconductor ``Tulip'' (21x4x)
54 1.2.4.2 rpaulo * Ethernet controller family driver.
55 1.2.4.2 rpaulo */
56 1.2.4.2 rpaulo
57 1.2.4.2 rpaulo /*
58 1.2.4.2 rpaulo * Transmit descriptor list size. This is arbitrary, but allocate
59 1.2.4.2 rpaulo * enough descriptors for 64 pending transmissions and 16 segments
60 1.2.4.2 rpaulo * per packet. Since a descriptor holds 2 buffer addresses, that's
61 1.2.4.2 rpaulo * 8 descriptors per packet. This MUST work out to a power of 2.
62 1.2.4.2 rpaulo */
63 1.2.4.2 rpaulo #define AE_NTXSEGS 16
64 1.2.4.2 rpaulo
65 1.2.4.2 rpaulo #define AE_TXQUEUELEN 64
66 1.2.4.2 rpaulo #define AE_NTXDESC (AE_TXQUEUELEN * AE_NTXSEGS)
67 1.2.4.2 rpaulo #define AE_NTXDESC_MASK (AE_NTXDESC - 1)
68 1.2.4.2 rpaulo #define AE_NEXTTX(x) ((x + 1) & AE_NTXDESC_MASK)
69 1.2.4.2 rpaulo
70 1.2.4.2 rpaulo /*
71 1.2.4.2 rpaulo * Receive descriptor list size. We have one Rx buffer per incoming
72 1.2.4.2 rpaulo * packet, so this logic is a little simpler.
73 1.2.4.2 rpaulo */
74 1.2.4.2 rpaulo #define AE_NRXDESC 64
75 1.2.4.2 rpaulo #define AE_NRXDESC_MASK (AE_NRXDESC - 1)
76 1.2.4.2 rpaulo #define AE_NEXTRX(x) ((x + 1) & AE_NRXDESC_MASK)
77 1.2.4.2 rpaulo
78 1.2.4.2 rpaulo /*
79 1.2.4.2 rpaulo * Control structures are DMA'd to the TULIP chip. We allocate them in
80 1.2.4.2 rpaulo * a single clump that maps to a single DMA segment to make several things
81 1.2.4.2 rpaulo * easier.
82 1.2.4.2 rpaulo */
83 1.2.4.2 rpaulo struct ae_control_data {
84 1.2.4.2 rpaulo /*
85 1.2.4.2 rpaulo * The transmit descriptors.
86 1.2.4.2 rpaulo */
87 1.2.4.2 rpaulo struct ae_desc acd_txdescs[AE_NTXDESC];
88 1.2.4.2 rpaulo
89 1.2.4.2 rpaulo /*
90 1.2.4.2 rpaulo * The receive descriptors.
91 1.2.4.2 rpaulo */
92 1.2.4.2 rpaulo struct ae_desc acd_rxdescs[AE_NRXDESC];
93 1.2.4.2 rpaulo };
94 1.2.4.2 rpaulo
95 1.2.4.2 rpaulo #define AE_CDOFF(x) offsetof(struct ae_control_data, x)
96 1.2.4.2 rpaulo #define AE_CDTXOFF(x) AE_CDOFF(acd_txdescs[(x)])
97 1.2.4.2 rpaulo #define AE_CDRXOFF(x) AE_CDOFF(acd_rxdescs[(x)])
98 1.2.4.2 rpaulo
99 1.2.4.2 rpaulo /*
100 1.2.4.2 rpaulo * Software state for transmit jobs.
101 1.2.4.2 rpaulo */
102 1.2.4.2 rpaulo struct ae_txsoft {
103 1.2.4.2 rpaulo struct mbuf *txs_mbuf; /* head of our mbuf chain */
104 1.2.4.2 rpaulo bus_dmamap_t txs_dmamap; /* our DMA map */
105 1.2.4.2 rpaulo int txs_firstdesc; /* first descriptor in packet */
106 1.2.4.2 rpaulo int txs_lastdesc; /* last descriptor in packet */
107 1.2.4.2 rpaulo int txs_ndescs; /* number of descriptors */
108 1.2.4.2 rpaulo SIMPLEQ_ENTRY(ae_txsoft) txs_q;
109 1.2.4.2 rpaulo };
110 1.2.4.2 rpaulo
111 1.2.4.2 rpaulo SIMPLEQ_HEAD(ae_txsq, ae_txsoft);
112 1.2.4.2 rpaulo
113 1.2.4.2 rpaulo /*
114 1.2.4.2 rpaulo * Software state for receive jobs.
115 1.2.4.2 rpaulo */
116 1.2.4.2 rpaulo struct ae_rxsoft {
117 1.2.4.2 rpaulo struct mbuf *rxs_mbuf; /* head of our mbuf chain */
118 1.2.4.2 rpaulo bus_dmamap_t rxs_dmamap; /* our DMA map */
119 1.2.4.2 rpaulo };
120 1.2.4.2 rpaulo
121 1.2.4.2 rpaulo struct ae_softc;
122 1.2.4.2 rpaulo
123 1.2.4.2 rpaulo /*
124 1.2.4.2 rpaulo * Some misc. statics, useful for debugging.
125 1.2.4.2 rpaulo */
126 1.2.4.2 rpaulo struct ae_stats {
127 1.2.4.2 rpaulo u_long ts_tx_uf; /* transmit underflow errors */
128 1.2.4.2 rpaulo u_long ts_tx_to; /* transmit jabber timeouts */
129 1.2.4.2 rpaulo u_long ts_tx_ec; /* excessive collision count */
130 1.2.4.2 rpaulo u_long ts_tx_lc; /* late collision count */
131 1.2.4.2 rpaulo };
132 1.2.4.2 rpaulo
133 1.2.4.2 rpaulo #ifndef _STANDALONE
134 1.2.4.2 rpaulo /*
135 1.2.4.2 rpaulo * Software state per device.
136 1.2.4.2 rpaulo */
137 1.2.4.2 rpaulo struct ae_softc {
138 1.2.4.2 rpaulo struct device sc_dev; /* generic device information */
139 1.2.4.2 rpaulo bus_space_tag_t sc_st; /* bus space tag */
140 1.2.4.2 rpaulo bus_space_handle_t sc_sh; /* bus space handle */
141 1.2.4.2 rpaulo bus_size_t sc_size; /* bus space size */
142 1.2.4.2 rpaulo bus_dma_tag_t sc_dmat; /* bus DMA tag */
143 1.2.4.2 rpaulo void *sc_ih; /* interrupt handle */
144 1.2.4.2 rpaulo int sc_cirq; /* interrupt request line (cpu) */
145 1.2.4.2 rpaulo int sc_mirq; /* interrupt request line (misc) */
146 1.2.4.2 rpaulo struct ethercom sc_ethercom; /* ethernet common data */
147 1.2.4.2 rpaulo void *sc_sdhook; /* shutdown hook */
148 1.2.4.2 rpaulo void *sc_powerhook; /* power management hook */
149 1.2.4.2 rpaulo
150 1.2.4.2 rpaulo struct ae_stats sc_stats; /* debugging stats */
151 1.2.4.2 rpaulo
152 1.2.4.2 rpaulo int sc_flags; /* misc flags. */
153 1.2.4.2 rpaulo
154 1.2.4.2 rpaulo struct mii_data sc_mii; /* MII/media information */
155 1.2.4.2 rpaulo
156 1.2.4.2 rpaulo int sc_txthresh; /* current transmit threshold */
157 1.2.4.2 rpaulo
158 1.2.4.2 rpaulo /* Media tick function. */
159 1.2.4.2 rpaulo void (*sc_tick)(void *);
160 1.2.4.2 rpaulo struct callout sc_tick_callout;
161 1.2.4.2 rpaulo
162 1.2.4.2 rpaulo u_int32_t sc_inten; /* copy of CSR_INTEN */
163 1.2.4.2 rpaulo
164 1.2.4.2 rpaulo u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */
165 1.2.4.2 rpaulo u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */
166 1.2.4.2 rpaulo
167 1.2.4.2 rpaulo bus_dma_segment_t sc_cdseg; /* control data memory */
168 1.2.4.2 rpaulo int sc_cdnseg; /* number of segments */
169 1.2.4.2 rpaulo bus_dmamap_t sc_cddmamap; /* control data DMA map */
170 1.2.4.2 rpaulo #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
171 1.2.4.2 rpaulo
172 1.2.4.2 rpaulo /*
173 1.2.4.2 rpaulo * Software state for transmit and receive descriptors.
174 1.2.4.2 rpaulo */
175 1.2.4.2 rpaulo struct ae_txsoft sc_txsoft[AE_TXQUEUELEN];
176 1.2.4.2 rpaulo struct ae_rxsoft sc_rxsoft[AE_NRXDESC];
177 1.2.4.2 rpaulo
178 1.2.4.2 rpaulo /*
179 1.2.4.2 rpaulo * Control data structures.
180 1.2.4.2 rpaulo */
181 1.2.4.2 rpaulo struct ae_control_data *sc_control_data;
182 1.2.4.2 rpaulo #define sc_txdescs sc_control_data->acd_txdescs
183 1.2.4.2 rpaulo #define sc_rxdescs sc_control_data->acd_rxdescs
184 1.2.4.2 rpaulo #define sc_setup_desc sc_control_data->acd_setup_desc
185 1.2.4.2 rpaulo
186 1.2.4.2 rpaulo int sc_txfree; /* number of free Tx descriptors */
187 1.2.4.2 rpaulo int sc_txnext; /* next ready Tx descriptor */
188 1.2.4.2 rpaulo
189 1.2.4.2 rpaulo struct ae_txsq sc_txfreeq; /* free Tx descsofts */
190 1.2.4.2 rpaulo struct ae_txsq sc_txdirtyq; /* dirty Tx descsofts */
191 1.2.4.2 rpaulo
192 1.2.4.2 rpaulo short sc_if_flags;
193 1.2.4.2 rpaulo
194 1.2.4.2 rpaulo int sc_rxptr; /* next ready RX descriptor/descsoft */
195 1.2.4.2 rpaulo
196 1.2.4.2 rpaulo #if NRND > 0
197 1.2.4.2 rpaulo rndsource_element_t sc_rnd_source; /* random source */
198 1.2.4.2 rpaulo #endif
199 1.2.4.2 rpaulo };
200 1.2.4.2 rpaulo #endif
201 1.2.4.2 rpaulo
202 1.2.4.2 rpaulo /* sc_flags */
203 1.2.4.2 rpaulo #define AE_ATTACHED 0x00000800 /* attach has succeeded */
204 1.2.4.2 rpaulo #define AE_ENABLED 0x00001000 /* chip is enabled */
205 1.2.4.2 rpaulo
206 1.2.4.2 rpaulo #define AE_IS_ENABLED(sc) ((sc)->sc_flags & AE_ENABLED)
207 1.2.4.2 rpaulo
208 1.2.4.2 rpaulo /*
209 1.2.4.2 rpaulo * This macro returns the current media entry.
210 1.2.4.2 rpaulo */
211 1.2.4.2 rpaulo #define AE_CURRENT_MEDIA(sc) ((sc)->sc_mii.mii_media.ifm_cur)
212 1.2.4.2 rpaulo
213 1.2.4.2 rpaulo /*
214 1.2.4.2 rpaulo * This macro determines if a change to media-related OPMODE bits requires
215 1.2.4.2 rpaulo * a chip reset.
216 1.2.4.2 rpaulo */
217 1.2.4.2 rpaulo #define TULIP_MEDIA_NEEDSRESET(sc, newbits) \
218 1.2.4.2 rpaulo (((sc)->sc_opmode & OPMODE_MEDIA_BITS) != \
219 1.2.4.2 rpaulo ((newbits) & OPMODE_MEDIA_BITS))
220 1.2.4.2 rpaulo
221 1.2.4.2 rpaulo #define AE_CDTXADDR(sc, x) ((sc)->sc_cddma + AE_CDTXOFF((x)))
222 1.2.4.2 rpaulo #define AE_CDRXADDR(sc, x) ((sc)->sc_cddma + AE_CDRXOFF((x)))
223 1.2.4.2 rpaulo
224 1.2.4.2 rpaulo #define AE_CDTXSYNC(sc, x, n, ops) \
225 1.2.4.2 rpaulo do { \
226 1.2.4.2 rpaulo int __x, __n; \
227 1.2.4.2 rpaulo \
228 1.2.4.2 rpaulo __x = (x); \
229 1.2.4.2 rpaulo __n = (n); \
230 1.2.4.2 rpaulo \
231 1.2.4.2 rpaulo /* If it will wrap around, sync to the end of the ring. */ \
232 1.2.4.2 rpaulo if ((__x + __n) > AE_NTXDESC) { \
233 1.2.4.2 rpaulo bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
234 1.2.4.2 rpaulo AE_CDTXOFF(__x), sizeof(struct ae_desc) * \
235 1.2.4.2 rpaulo (AE_NTXDESC - __x), (ops)); \
236 1.2.4.2 rpaulo __n -= (AE_NTXDESC - __x); \
237 1.2.4.2 rpaulo __x = 0; \
238 1.2.4.2 rpaulo } \
239 1.2.4.2 rpaulo \
240 1.2.4.2 rpaulo /* Now sync whatever is left. */ \
241 1.2.4.2 rpaulo bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
242 1.2.4.2 rpaulo AE_CDTXOFF(__x), sizeof(struct ae_desc) * __n, (ops)); \
243 1.2.4.2 rpaulo } while (0)
244 1.2.4.2 rpaulo
245 1.2.4.2 rpaulo #define AE_CDRXSYNC(sc, x, ops) \
246 1.2.4.2 rpaulo bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
247 1.2.4.2 rpaulo AE_CDRXOFF((x)), sizeof(struct ae_desc), (ops))
248 1.2.4.2 rpaulo
249 1.2.4.2 rpaulo /*
250 1.2.4.2 rpaulo * Note we rely on MCLBYTES being a power of two. Because the `length'
251 1.2.4.2 rpaulo * field is only 11 bits, we must subtract 1 from the length to avoid
252 1.2.4.2 rpaulo * having it truncated to 0!
253 1.2.4.2 rpaulo */
254 1.2.4.2 rpaulo #define AE_INIT_RXDESC(sc, x) \
255 1.2.4.2 rpaulo do { \
256 1.2.4.2 rpaulo struct ae_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
257 1.2.4.2 rpaulo struct ae_desc *__rxd = &sc->sc_rxdescs[(x)]; \
258 1.2.4.2 rpaulo struct mbuf *__m = __rxs->rxs_mbuf; \
259 1.2.4.2 rpaulo \
260 1.2.4.2 rpaulo __m->m_data = __m->m_ext.ext_buf; \
261 1.2.4.2 rpaulo __rxd->ad_bufaddr1 = \
262 1.2.4.2 rpaulo (__rxs->rxs_dmamap->dm_segs[0].ds_addr); \
263 1.2.4.2 rpaulo __rxd->ad_bufaddr2 = \
264 1.2.4.2 rpaulo AE_CDRXADDR((sc), AE_NEXTRX((x))); \
265 1.2.4.2 rpaulo __rxd->ad_ctl = \
266 1.2.4.2 rpaulo ((((__m->m_ext.ext_size - 1) & ~0x3U) \
267 1.2.4.2 rpaulo << ADCTL_SIZE1_SHIFT) | \
268 1.2.4.2 rpaulo ((x) == (AE_NRXDESC - 1) ? ADCTL_ER : 0)); \
269 1.2.4.2 rpaulo __rxd->ad_status = ADSTAT_OWN|ADSTAT_Rx_FS|ADSTAT_Rx_LS; \
270 1.2.4.2 rpaulo AE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
271 1.2.4.2 rpaulo } while (0)
272 1.2.4.2 rpaulo
273 1.2.4.2 rpaulo /* CSR access */
274 1.2.4.2 rpaulo
275 1.2.4.2 rpaulo #define AE_READ(sc, reg) \
276 1.2.4.2 rpaulo bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
277 1.2.4.2 rpaulo
278 1.2.4.2 rpaulo #define AE_WRITE(sc, reg, val) \
279 1.2.4.2 rpaulo bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
280 1.2.4.2 rpaulo
281 1.2.4.2 rpaulo #define AE_SET(sc, reg, mask) \
282 1.2.4.2 rpaulo AE_WRITE((sc), (reg), AE_READ((sc), (reg)) | (mask))
283 1.2.4.2 rpaulo
284 1.2.4.2 rpaulo #define AE_CLR(sc, reg, mask) \
285 1.2.4.2 rpaulo AE_WRITE((sc), (reg), AE_READ((sc), (reg)) & ~(mask))
286 1.2.4.2 rpaulo
287 1.2.4.2 rpaulo #define AE_ISSET(sc, reg, mask) \
288 1.2.4.2 rpaulo (AE_READ((sc), (reg)) & (mask))
289 1.2.4.2 rpaulo
290 1.2.4.2 rpaulo #define AE_BARRIER(sc) \
291 1.2.4.2 rpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_size, \
292 1.2.4.2 rpaulo BUS_SPACE_BARRIER_WRITE)
293 1.2.4.2 rpaulo
294 1.2.4.2 rpaulo #endif /* _MIPS_ATHEROS_DEV_AEVAR_H_ */
295