if_ae.c revision 1.1
1 /* $Id: if_ae.c,v 1.1 2006/03/21 08:15:19 gdamore Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 3. All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the NetBSD 61 * Foundation, Inc. and its contributors. 62 * 4. Neither the name of The NetBSD Foundation nor the names of its 63 * contributors may be used to endorse or promote products derived 64 * from this software without specific prior written permission. 65 * 66 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 67 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 68 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 69 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 70 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 71 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 72 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 73 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 74 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 75 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 76 * POSSIBILITY OF SUCH DAMAGE. 77 */ 78 79 /* 80 * Device driver for the onboard ethernet MAC found on the AR5312 81 * chip's AHB bus. 82 * 83 * This device is very simliar to the tulip in most regards, and 84 * the code is directly derived from NetBSD's tulip.c. However, it 85 * is different enough that it did not seem to be a good idea to 86 * add further complexity to the tulip driver, so we have our own. 87 * 88 * Also tulip has a lot of complexity in it for various parts/options 89 * that we don't need, and on these little boxes with only ~8MB RAM, we 90 * don't want any extra bloat. 91 */ 92 93 /* 94 * TODO: 95 * 96 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 97 * inbound packets on a half-word boundary, which would make life easier 98 * for TCP/IP. (Aligning IP headers on a word.) 99 * 100 * 2) There is stuff in original tulip to shut down the device when reacting 101 * to a a change in link status. Is that needed. 102 * 103 * 3) Test with variety of 10/100 HDX/FDX scenarios. 104 * 105 */ 106 107 #include <sys/cdefs.h> 108 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.1 2006/03/21 08:15:19 gdamore Exp $"); 109 110 #include "bpfilter.h" 111 112 #include <sys/param.h> 113 #include <sys/systm.h> 114 #include <sys/callout.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/kernel.h> 118 #include <sys/socket.h> 119 #include <sys/ioctl.h> 120 #include <sys/errno.h> 121 #include <sys/device.h> 122 123 #include <machine/endian.h> 124 125 #include <uvm/uvm_extern.h> 126 127 #include <net/if.h> 128 #include <net/if_dl.h> 129 #include <net/if_media.h> 130 #include <net/if_ether.h> 131 132 #if NBPFILTER > 0 133 #include <net/bpf.h> 134 #endif 135 136 #include <machine/bus.h> 137 #include <machine/intr.h> 138 139 #include <dev/mii/mii.h> 140 #include <dev/mii/miivar.h> 141 #include <dev/mii/mii_bitbang.h> 142 143 #include <mips/atheros/include/arbusvar.h> 144 #include <mips/atheros/dev/aereg.h> 145 #include <mips/atheros/dev/aevar.h> 146 147 static const struct { 148 u_int32_t txth_opmode; /* OPMODE bits */ 149 const char *txth_name; /* name of mode */ 150 } ae_txthresh[] = { 151 { OPMODE_TR_32, "32 words" }, 152 { OPMODE_TR_64, "64 words" }, 153 { OPMODE_TR_128, "128 words" }, 154 { OPMODE_TR_256, "256 words" }, 155 { OPMODE_SF, "store and forward mode" }, 156 { 0, NULL }, 157 }; 158 159 static int ae_match(struct device *, struct cfdata *, void *); 160 static void ae_attach(struct device *, struct device *, void *); 161 static int ae_detach(struct device *, int); 162 static int ae_activate(struct device *, enum devact); 163 164 static void ae_reset(struct ae_softc *); 165 static void ae_idle(struct ae_softc *, u_int32_t); 166 167 static int ae_mediachange(struct ifnet *); 168 static void ae_mediastatus(struct ifnet *, struct ifmediareq *); 169 170 static void ae_start(struct ifnet *); 171 static void ae_watchdog(struct ifnet *); 172 static int ae_ioctl(struct ifnet *, u_long, caddr_t); 173 static int ae_init(struct ifnet *); 174 static void ae_stop(struct ifnet *, int); 175 176 static void ae_shutdown(void *); 177 178 static void ae_rxdrain(struct ae_softc *); 179 static int ae_add_rxbuf(struct ae_softc *, int); 180 181 static int ae_enable(struct ae_softc *); 182 static void ae_disable(struct ae_softc *); 183 static void ae_power(int, void *); 184 185 static void ae_filter_setup(struct ae_softc *); 186 187 static int ae_intr(void *); 188 static void ae_rxintr(struct ae_softc *); 189 static void ae_txintr(struct ae_softc *); 190 191 static void ae_mii_tick(void *); 192 static void ae_mii_statchg(struct device *); 193 194 static int ae_mii_readreg(struct device *, int, int); 195 static void ae_mii_writereg(struct device *, int, int, int); 196 197 #ifdef AE_DEBUG 198 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 199 printf x 200 #else 201 #define DPRINTF(sc, x) /* nothing */ 202 #endif 203 204 #ifdef AE_STATS 205 static void ae_print_stats(struct ae_softc *); 206 #endif 207 208 CFATTACH_DECL(ae, sizeof(struct ae_softc), 209 ae_match, ae_attach, ae_detach, ae_activate); 210 211 /* 212 * ae_match: 213 * 214 * Check for a device match. 215 */ 216 int 217 ae_match(struct device *parent, struct cfdata *cf, void *aux) 218 { 219 struct arbus_attach_args *aa = aux; 220 221 if (strcmp(aa->aa_name, cf->cf_name) == 0) 222 return 1; 223 224 return 0; 225 226 } 227 228 /* 229 * ae_attach: 230 * 231 * Attach an ae interface to the system. 232 */ 233 void 234 ae_attach(struct device *parent, struct device *self, void *aux) 235 { 236 uint8_t enaddr[ETHER_ADDR_LEN]; 237 struct ae_softc *sc = (void *)self; 238 struct arbus_attach_args *aa = aux; 239 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 240 int i, error; 241 242 callout_init(&sc->sc_tick_callout); 243 244 printf(": Atheros AR531X 10/100 Ethernet\n"); 245 246 /* 247 * Try to MAC address. 248 */ 249 if (devprop_get(&sc->sc_dev, "mac-addr", enaddr, 250 sizeof (enaddr), NULL) != sizeof (enaddr)) { 251 printf("%s: unable to get mac-addr property\n", 252 sc->sc_dev.dv_xname); 253 return; 254 } 255 256 /* Announce ourselves. */ 257 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 258 ether_sprintf(enaddr)); 259 260 sc->sc_irq = aa->aa_irq; 261 sc->sc_st = aa->aa_bst; 262 sc->sc_dmat = aa->aa_dmat; 263 264 SIMPLEQ_INIT(&sc->sc_txfreeq); 265 SIMPLEQ_INIT(&sc->sc_txdirtyq); 266 267 /* 268 * Map registers. 269 */ 270 sc->sc_size = aa->aa_size; 271 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 272 &sc->sc_sh)) != 0) { 273 printf("%s: unable to map registers, error = %d\n", 274 sc->sc_dev.dv_xname, error); 275 goto fail_0; 276 } 277 278 /* 279 * Allocate the control data structures, and create and load the 280 * DMA map for it. 281 */ 282 if ((error = bus_dmamem_alloc(sc->sc_dmat, 283 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 284 1, &sc->sc_cdnseg, 0)) != 0) { 285 printf("%s: unable to allocate control data, error = %d\n", 286 sc->sc_dev.dv_xname, error); 287 goto fail_1; 288 } 289 290 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 291 sizeof(struct ae_control_data), (caddr_t *)&sc->sc_control_data, 292 BUS_DMA_COHERENT)) != 0) { 293 printf("%s: unable to map control data, error = %d\n", 294 sc->sc_dev.dv_xname, error); 295 goto fail_2; 296 } 297 298 if ((error = bus_dmamap_create(sc->sc_dmat, 299 sizeof(struct ae_control_data), 1, 300 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 301 printf("%s: unable to create control data DMA map, " 302 "error = %d\n", sc->sc_dev.dv_xname, error); 303 goto fail_3; 304 } 305 306 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 307 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 308 0)) != 0) { 309 printf("%s: unable to load control data DMA map, error = %d\n", 310 sc->sc_dev.dv_xname, error); 311 goto fail_4; 312 } 313 314 /* 315 * Create the transmit buffer DMA maps. 316 */ 317 for (i = 0; i < AE_TXQUEUELEN; i++) { 318 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 319 AE_NTXSEGS, MCLBYTES, 0, 0, 320 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 321 printf("%s: unable to create tx DMA map %d, " 322 "error = %d\n", sc->sc_dev.dv_xname, i, error); 323 goto fail_5; 324 } 325 } 326 327 /* 328 * Create the receive buffer DMA maps. 329 */ 330 for (i = 0; i < AE_NRXDESC; i++) { 331 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 332 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 333 printf("%s: unable to create rx DMA map %d, " 334 "error = %d\n", sc->sc_dev.dv_xname, i, error); 335 goto fail_6; 336 } 337 sc->sc_rxsoft[i].rxs_mbuf = NULL; 338 } 339 340 /* 341 * Reset the chip to a known state. 342 */ 343 ae_reset(sc); 344 345 /* 346 * From this point forward, the attachment cannot fail. A failure 347 * before this point releases all resources that may have been 348 * allocated. 349 */ 350 sc->sc_flags |= AE_ATTACHED; 351 352 /* 353 * Initialize our media structures. This may probe the MII, if 354 * present. 355 */ 356 sc->sc_mii.mii_ifp = ifp; 357 sc->sc_mii.mii_readreg = ae_mii_readreg; 358 sc->sc_mii.mii_writereg = ae_mii_writereg; 359 sc->sc_mii.mii_statchg = ae_mii_statchg; 360 ifmedia_init(&sc->sc_mii.mii_media, 0, ae_mediachange, 361 ae_mediastatus); 362 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 363 MII_OFFSET_ANY, 0); 364 365 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 366 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 367 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 368 } else 369 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 370 371 sc->sc_tick = ae_mii_tick; 372 373 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 374 ifp->if_softc = sc; 375 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 376 sc->sc_if_flags = ifp->if_flags; 377 ifp->if_ioctl = ae_ioctl; 378 ifp->if_start = ae_start; 379 ifp->if_watchdog = ae_watchdog; 380 ifp->if_init = ae_init; 381 ifp->if_stop = ae_stop; 382 IFQ_SET_READY(&ifp->if_snd); 383 384 /* 385 * We can support 802.1Q VLAN-sized frames. 386 */ 387 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 388 389 /* 390 * Attach the interface. 391 */ 392 if_attach(ifp); 393 ether_ifattach(ifp, enaddr); 394 395 #if NRND > 0 396 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 397 RND_TYPE_NET, 0); 398 #endif 399 400 /* 401 * Make sure the interface is shutdown during reboot. 402 */ 403 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 404 if (sc->sc_sdhook == NULL) 405 printf("%s: WARNING: unable to establish shutdown hook\n", 406 sc->sc_dev.dv_xname); 407 408 /* 409 * Add a suspend hook to make sure we come back up after a 410 * resume. 411 */ 412 sc->sc_powerhook = powerhook_establish(ae_power, sc); 413 if (sc->sc_powerhook == NULL) 414 printf("%s: WARNING: unable to establish power hook\n", 415 sc->sc_dev.dv_xname); 416 return; 417 418 /* 419 * Free any resources we've allocated during the failed attach 420 * attempt. Do this in reverse order and fall through. 421 */ 422 fail_6: 423 for (i = 0; i < AE_NRXDESC; i++) { 424 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 425 bus_dmamap_destroy(sc->sc_dmat, 426 sc->sc_rxsoft[i].rxs_dmamap); 427 } 428 fail_5: 429 for (i = 0; i < AE_TXQUEUELEN; i++) { 430 if (sc->sc_txsoft[i].txs_dmamap != NULL) 431 bus_dmamap_destroy(sc->sc_dmat, 432 sc->sc_txsoft[i].txs_dmamap); 433 } 434 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 435 fail_4: 436 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 437 fail_3: 438 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 439 sizeof(struct ae_control_data)); 440 fail_2: 441 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 442 fail_1: 443 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 444 fail_0: 445 return; 446 } 447 448 /* 449 * ae_activate: 450 * 451 * Handle device activation/deactivation requests. 452 */ 453 int 454 ae_activate(struct device *self, enum devact act) 455 { 456 struct ae_softc *sc = (void *) self; 457 int s, error = 0; 458 459 s = splnet(); 460 switch (act) { 461 case DVACT_ACTIVATE: 462 error = EOPNOTSUPP; 463 break; 464 465 case DVACT_DEACTIVATE: 466 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 467 if_deactivate(&sc->sc_ethercom.ec_if); 468 break; 469 } 470 splx(s); 471 472 return (error); 473 } 474 475 /* 476 * ae_detach: 477 * 478 * Detach a device interface. 479 */ 480 int 481 ae_detach(struct device *self, int flags) 482 { 483 struct ae_softc *sc = (void *)self; 484 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 485 struct ae_rxsoft *rxs; 486 struct ae_txsoft *txs; 487 int i; 488 489 /* 490 * Succeed now if there isn't any work to do. 491 */ 492 if ((sc->sc_flags & AE_ATTACHED) == 0) 493 return (0); 494 495 /* Unhook our tick handler. */ 496 if (sc->sc_tick) 497 callout_stop(&sc->sc_tick_callout); 498 499 /* Detach all PHYs */ 500 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 501 502 /* Delete all remaining media. */ 503 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 504 505 #if NRND > 0 506 rnd_detach_source(&sc->sc_rnd_source); 507 #endif 508 ether_ifdetach(ifp); 509 if_detach(ifp); 510 511 for (i = 0; i < AE_NRXDESC; i++) { 512 rxs = &sc->sc_rxsoft[i]; 513 if (rxs->rxs_mbuf != NULL) { 514 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 515 m_freem(rxs->rxs_mbuf); 516 rxs->rxs_mbuf = NULL; 517 } 518 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 519 } 520 for (i = 0; i < AE_TXQUEUELEN; i++) { 521 txs = &sc->sc_txsoft[i]; 522 if (txs->txs_mbuf != NULL) { 523 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 524 m_freem(txs->txs_mbuf); 525 txs->txs_mbuf = NULL; 526 } 527 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 528 } 529 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 530 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 531 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 532 sizeof(struct ae_control_data)); 533 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 534 535 shutdownhook_disestablish(sc->sc_sdhook); 536 powerhook_disestablish(sc->sc_powerhook); 537 538 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 539 540 541 return (0); 542 } 543 544 /* 545 * ae_shutdown: 546 * 547 * Make sure the interface is stopped at reboot time. 548 */ 549 static void 550 ae_shutdown(void *arg) 551 { 552 struct ae_softc *sc = arg; 553 554 ae_stop(&sc->sc_ethercom.ec_if, 1); 555 } 556 557 /* 558 * ae_start: [ifnet interface function] 559 * 560 * Start packet transmission on the interface. 561 */ 562 static void 563 ae_start(struct ifnet *ifp) 564 { 565 struct ae_softc *sc = ifp->if_softc; 566 struct mbuf *m0, *m; 567 struct ae_txsoft *txs, *last_txs = NULL; 568 bus_dmamap_t dmamap; 569 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 570 571 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 572 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 573 574 575 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 576 return; 577 578 /* 579 * Remember the previous number of free descriptors and 580 * the first descriptor we'll use. 581 */ 582 ofree = sc->sc_txfree; 583 firsttx = sc->sc_txnext; 584 585 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 586 sc->sc_dev.dv_xname, ofree, firsttx)); 587 588 /* 589 * Loop through the send queue, setting up transmit descriptors 590 * until we drain the queue, or use up all available transmit 591 * descriptors. 592 */ 593 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 594 sc->sc_txfree != 0) { 595 /* 596 * Grab a packet off the queue. 597 */ 598 IFQ_POLL(&ifp->if_snd, m0); 599 if (m0 == NULL) 600 break; 601 m = NULL; 602 603 dmamap = txs->txs_dmamap; 604 605 /* 606 * Load the DMA map. If this fails, the packet either 607 * didn't fit in the alloted number of segments, or we were 608 * short on resources. In this case, we'll copy and try 609 * again. 610 */ 611 if (((mtod(m0, uintptr_t) & 3) != 0) || 612 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 613 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 614 MGETHDR(m, M_DONTWAIT, MT_DATA); 615 if (m == NULL) { 616 printf("%s: unable to allocate Tx mbuf\n", 617 sc->sc_dev.dv_xname); 618 break; 619 } 620 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 621 if (m0->m_pkthdr.len > MHLEN) { 622 MCLGET(m, M_DONTWAIT); 623 if ((m->m_flags & M_EXT) == 0) { 624 printf("%s: unable to allocate Tx " 625 "cluster\n", sc->sc_dev.dv_xname); 626 m_freem(m); 627 break; 628 } 629 } 630 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 631 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 632 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 633 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 634 if (error) { 635 printf("%s: unable to load Tx buffer, " 636 "error = %d\n", sc->sc_dev.dv_xname, 637 error); 638 break; 639 } 640 } 641 642 /* 643 * Ensure we have enough descriptors free to describe 644 * the packet. 645 */ 646 if (dmamap->dm_nsegs > sc->sc_txfree) { 647 /* 648 * Not enough free descriptors to transmit this 649 * packet. We haven't committed to anything yet, 650 * so just unload the DMA map, put the packet 651 * back on the queue, and punt. Notify the upper 652 * layer that there are no more slots left. 653 * 654 * XXX We could allocate an mbuf and copy, but 655 * XXX it is worth it? 656 */ 657 ifp->if_flags |= IFF_OACTIVE; 658 bus_dmamap_unload(sc->sc_dmat, dmamap); 659 if (m != NULL) 660 m_freem(m); 661 break; 662 } 663 664 IFQ_DEQUEUE(&ifp->if_snd, m0); 665 if (m != NULL) { 666 m_freem(m0); 667 m0 = m; 668 } 669 670 /* 671 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 672 */ 673 674 /* Sync the DMA map. */ 675 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 676 BUS_DMASYNC_PREWRITE); 677 678 /* 679 * Initialize the transmit descriptors. 680 */ 681 for (nexttx = sc->sc_txnext, seg = 0; 682 seg < dmamap->dm_nsegs; 683 seg++, nexttx = AE_NEXTTX(nexttx)) { 684 /* 685 * If this is the first descriptor we're 686 * enqueueing, don't set the OWN bit just 687 * yet. That could cause a race condition. 688 * We'll do it below. 689 */ 690 sc->sc_txdescs[nexttx].ad_status = 691 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 692 sc->sc_txdescs[nexttx].ad_bufaddr1 = 693 dmamap->dm_segs[seg].ds_addr; 694 sc->sc_txdescs[nexttx].ad_ctl = 695 (dmamap->dm_segs[seg].ds_len << 696 ADCTL_SIZE1_SHIFT) | 697 (nexttx == (AE_NTXDESC - 1) ? 698 ADCTL_ER : 0); 699 lasttx = nexttx; 700 } 701 702 KASSERT(lasttx != -1); 703 704 /* Set `first segment' and `last segment' appropriately. */ 705 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 706 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 707 708 #ifdef AE_DEBUG 709 if (ifp->if_flags & IFF_DEBUG) { 710 printf(" txsoft %p transmit chain:\n", txs); 711 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 712 printf(" descriptor %d:\n", seg); 713 printf(" ad_status: 0x%08x\n", 714 sc->sc_txdescs[seg].ad_status); 715 printf(" ad_ctl: 0x%08x\n", 716 sc->sc_txdescs[seg].ad_ctl); 717 printf(" ad_bufaddr1: 0x%08x\n", 718 sc->sc_txdescs[seg].ad_bufaddr1); 719 printf(" ad_bufaddr2: 0x%08x\n", 720 sc->sc_txdescs[seg].ad_bufaddr2); 721 if (seg == lasttx) 722 break; 723 } 724 } 725 #endif 726 727 /* Sync the descriptors we're using. */ 728 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 729 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 730 731 /* 732 * Store a pointer to the packet so we can free it later, 733 * and remember what txdirty will be once the packet is 734 * done. 735 */ 736 txs->txs_mbuf = m0; 737 txs->txs_firstdesc = sc->sc_txnext; 738 txs->txs_lastdesc = lasttx; 739 txs->txs_ndescs = dmamap->dm_nsegs; 740 741 /* Advance the tx pointer. */ 742 sc->sc_txfree -= dmamap->dm_nsegs; 743 sc->sc_txnext = nexttx; 744 745 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 746 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 747 748 last_txs = txs; 749 750 #if NBPFILTER > 0 751 /* 752 * Pass the packet to any BPF listeners. 753 */ 754 if (ifp->if_bpf) 755 bpf_mtap(ifp->if_bpf, m0); 756 #endif /* NBPFILTER > 0 */ 757 } 758 759 if (txs == NULL || sc->sc_txfree == 0) { 760 /* No more slots left; notify upper layer. */ 761 ifp->if_flags |= IFF_OACTIVE; 762 } 763 764 if (sc->sc_txfree != ofree) { 765 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 766 sc->sc_dev.dv_xname, lasttx, firsttx)); 767 /* 768 * Cause a transmit interrupt to happen on the 769 * last packet we enqueued. 770 */ 771 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 772 AE_CDTXSYNC(sc, lasttx, 1, 773 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 774 775 /* 776 * The entire packet chain is set up. Give the 777 * first descriptor to the chip now. 778 */ 779 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 780 AE_CDTXSYNC(sc, firsttx, 1, 781 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 782 783 /* Wake up the transmitter. */ 784 /* XXX USE AUTOPOLLING? */ 785 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 786 AE_BARRIER(sc); 787 788 /* Set a watchdog timer in case the chip flakes out. */ 789 ifp->if_timer = 5; 790 } 791 } 792 793 /* 794 * ae_watchdog: [ifnet interface function] 795 * 796 * Watchdog timer handler. 797 */ 798 static void 799 ae_watchdog(struct ifnet *ifp) 800 { 801 struct ae_softc *sc = ifp->if_softc; 802 int doing_transmit; 803 804 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 805 806 if (doing_transmit) { 807 printf("%s: transmit timeout\n", sc->sc_dev.dv_xname); 808 ifp->if_oerrors++; 809 } 810 else 811 printf("%s: spurious watchdog timeout\n", sc->sc_dev.dv_xname); 812 813 (void) ae_init(ifp); 814 815 /* Try to get more packets going. */ 816 ae_start(ifp); 817 } 818 819 /* 820 * ae_ioctl: [ifnet interface function] 821 * 822 * Handle control requests from the operator. 823 */ 824 static int 825 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 826 { 827 struct ae_softc *sc = ifp->if_softc; 828 struct ifreq *ifr = (struct ifreq *)data; 829 int s, error; 830 831 s = splnet(); 832 833 switch (cmd) { 834 case SIOCSIFMEDIA: 835 case SIOCGIFMEDIA: 836 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 837 break; 838 case SIOCSIFFLAGS: 839 /* If the interface is up and running, only modify the receive 840 * filter when setting promiscuous or debug mode. Otherwise 841 * fall through to ether_ioctl, which will reset the chip. 842 */ 843 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 844 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 845 == (IFF_UP|IFF_RUNNING)) 846 && ((ifp->if_flags & (~RESETIGN)) 847 == (sc->sc_if_flags & (~RESETIGN)))) { 848 /* Set up the receive filter. */ 849 ae_filter_setup(sc); 850 error = 0; 851 break; 852 #undef RESETIGN 853 } 854 /* FALLTHROUGH */ 855 default: 856 error = ether_ioctl(ifp, cmd, data); 857 if (error == ENETRESET) { 858 if (ifp->if_flags & IFF_RUNNING) { 859 /* 860 * Multicast list has changed. Set the 861 * hardware filter accordingly. 862 */ 863 ae_filter_setup(sc); 864 } 865 error = 0; 866 } 867 break; 868 } 869 870 /* Try to get more packets going. */ 871 if (AE_IS_ENABLED(sc)) 872 ae_start(ifp); 873 874 sc->sc_if_flags = ifp->if_flags; 875 splx(s); 876 return (error); 877 } 878 879 /* 880 * ae_intr: 881 * 882 * Interrupt service routine. 883 */ 884 int 885 ae_intr(void *arg) 886 { 887 struct ae_softc *sc = arg; 888 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 889 u_int32_t status, rxstatus, txstatus; 890 int handled = 0, txthresh; 891 892 DPRINTF(sc, ("%s: ae_intr\n", sc->sc_dev.dv_xname)); 893 894 #ifdef DEBUG 895 if (AE_IS_ENABLED(sc) == 0) 896 panic("%s: ae_intr: not enabled", sc->sc_dev.dv_xname); 897 #endif 898 899 /* 900 * If the interface isn't running, the interrupt couldn't 901 * possibly have come from us. 902 */ 903 if ((ifp->if_flags & IFF_RUNNING) == 0 || 904 !device_is_active(&sc->sc_dev)) { 905 printf("spurious?!?\n"); 906 return (0); 907 } 908 909 for (;;) { 910 status = AE_READ(sc, CSR_STATUS); 911 if (status) { 912 AE_WRITE(sc, CSR_STATUS, status); 913 AE_BARRIER(sc); 914 } 915 916 if ((status & sc->sc_inten) == 0) 917 break; 918 919 handled = 1; 920 921 rxstatus = status & sc->sc_rxint_mask; 922 txstatus = status & sc->sc_txint_mask; 923 924 if (rxstatus) { 925 /* Grab new any new packets. */ 926 ae_rxintr(sc); 927 928 if (rxstatus & STATUS_RU) { 929 printf("%s: receive ring overrun\n", 930 sc->sc_dev.dv_xname); 931 /* Get the receive process going again. */ 932 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 933 AE_BARRIER(sc); 934 break; 935 } 936 } 937 938 if (txstatus) { 939 /* Sweep up transmit descriptors. */ 940 ae_txintr(sc); 941 942 if (txstatus & STATUS_TJT) 943 printf("%s: transmit jabber timeout\n", 944 sc->sc_dev.dv_xname); 945 946 if (txstatus & STATUS_UNF) { 947 /* 948 * Increase our transmit threshold if 949 * another is available. 950 */ 951 txthresh = sc->sc_txthresh + 1; 952 if (ae_txthresh[txthresh].txth_name != NULL) { 953 uint32_t opmode; 954 /* Idle the transmit process. */ 955 opmode = AE_READ(sc, CSR_OPMODE); 956 ae_idle(sc, OPMODE_ST); 957 958 sc->sc_txthresh = txthresh; 959 opmode &= 960 ~(OPMODE_TR|OPMODE_SF); 961 opmode |= 962 ae_txthresh[txthresh].txth_opmode; 963 printf("%s: transmit underrun; new " 964 "threshold: %s\n", 965 sc->sc_dev.dv_xname, 966 ae_txthresh[txthresh].txth_name); 967 968 /* 969 * Set the new threshold and restart 970 * the transmit process. 971 */ 972 AE_WRITE(sc, CSR_OPMODE, opmode); 973 AE_BARRIER(sc); 974 } 975 /* 976 * XXX Log every Nth underrun from 977 * XXX now on? 978 */ 979 } 980 } 981 982 if (status & (STATUS_TPS|STATUS_RPS)) { 983 if (status & STATUS_TPS) 984 printf("%s: transmit process stopped\n", 985 sc->sc_dev.dv_xname); 986 if (status & STATUS_RPS) 987 printf("%s: receive process stopped\n", 988 sc->sc_dev.dv_xname); 989 (void) ae_init(ifp); 990 break; 991 } 992 993 if (status & STATUS_SE) { 994 const char *str; 995 996 if (status & STATUS_TX_ABORT) 997 str = "tx abort"; 998 else if (status & STATUS_RX_ABORT) 999 str = "rx abort"; 1000 else 1001 str = "unknown error"; 1002 1003 printf("%s: fatal system error: %s\n", 1004 sc->sc_dev.dv_xname, str); 1005 (void) ae_init(ifp); 1006 break; 1007 } 1008 1009 /* 1010 * Not handled: 1011 * 1012 * Transmit buffer unavailable -- normal 1013 * condition, nothing to do, really. 1014 * 1015 * General purpose timer experied -- we don't 1016 * use the general purpose timer. 1017 * 1018 * Early receive interrupt -- not available on 1019 * all chips, we just use RI. We also only 1020 * use single-segment receive DMA, so this 1021 * is mostly useless. 1022 */ 1023 } 1024 1025 /* Try to get more packets going. */ 1026 ae_start(ifp); 1027 1028 #if NRND > 0 1029 if (handled) 1030 rnd_add_uint32(&sc->sc_rnd_source, status); 1031 #endif 1032 return (handled); 1033 } 1034 1035 /* 1036 * ae_rxintr: 1037 * 1038 * Helper; handle receive interrupts. 1039 */ 1040 static void 1041 ae_rxintr(struct ae_softc *sc) 1042 { 1043 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1044 struct ether_header *eh; 1045 struct ae_rxsoft *rxs; 1046 struct mbuf *m; 1047 u_int32_t rxstat; 1048 int i, len; 1049 1050 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1051 rxs = &sc->sc_rxsoft[i]; 1052 1053 AE_CDRXSYNC(sc, i, 1054 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1055 1056 rxstat = sc->sc_rxdescs[i].ad_status; 1057 1058 if (rxstat & ADSTAT_OWN) { 1059 /* 1060 * We have processed all of the receive buffers. 1061 */ 1062 break; 1063 } 1064 1065 /* 1066 * If any collisions were seen on the wire, count one. 1067 */ 1068 if (rxstat & ADSTAT_Rx_CS) 1069 ifp->if_collisions++; 1070 1071 /* 1072 * If an error occurred, update stats, clear the status 1073 * word, and leave the packet buffer in place. It will 1074 * simply be reused the next time the ring comes around. 1075 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1076 * error. 1077 */ 1078 if (rxstat & ADSTAT_ES && 1079 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1080 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1081 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1082 #define PRINTERR(bit, str) \ 1083 if (rxstat & (bit)) \ 1084 printf("%s: receive error: %s\n", \ 1085 sc->sc_dev.dv_xname, str) 1086 ifp->if_ierrors++; 1087 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1088 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1089 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1090 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1091 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1092 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1093 #undef PRINTERR 1094 AE_INIT_RXDESC(sc, i); 1095 continue; 1096 } 1097 1098 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1099 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1100 1101 /* 1102 * No errors; receive the packet. Note the chip 1103 * includes the CRC with every packet. 1104 */ 1105 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1106 1107 /* 1108 * XXX: the Atheros part can align on half words. what 1109 * is the performance implication of this? Probably 1110 * minimal, and we should use it... 1111 */ 1112 #ifdef __NO_STRICT_ALIGNMENT 1113 /* 1114 * Allocate a new mbuf cluster. If that fails, we are 1115 * out of memory, and must drop the packet and recycle 1116 * the buffer that's already attached to this descriptor. 1117 */ 1118 m = rxs->rxs_mbuf; 1119 if (ae_add_rxbuf(sc, i) != 0) { 1120 ifp->if_ierrors++; 1121 AE_INIT_RXDESC(sc, i); 1122 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1123 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1124 continue; 1125 } 1126 #else 1127 /* 1128 * The chip's receive buffers must be 4-byte aligned. 1129 * But this means that the data after the Ethernet header 1130 * is misaligned. We must allocate a new buffer and 1131 * copy the data, shifted forward 2 bytes. 1132 */ 1133 MGETHDR(m, M_DONTWAIT, MT_DATA); 1134 if (m == NULL) { 1135 dropit: 1136 ifp->if_ierrors++; 1137 AE_INIT_RXDESC(sc, i); 1138 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1139 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1140 continue; 1141 } 1142 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1143 if (len > (MHLEN - 2)) { 1144 MCLGET(m, M_DONTWAIT); 1145 if ((m->m_flags & M_EXT) == 0) { 1146 m_freem(m); 1147 goto dropit; 1148 } 1149 } 1150 m->m_data += 2; 1151 1152 /* 1153 * Note that we use clusters for incoming frames, so the 1154 * buffer is virtually contiguous. 1155 */ 1156 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1157 1158 /* Allow the receive descriptor to continue using its mbuf. */ 1159 AE_INIT_RXDESC(sc, i); 1160 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1161 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1162 #endif /* __NO_STRICT_ALIGNMENT */ 1163 1164 ifp->if_ipackets++; 1165 eh = mtod(m, struct ether_header *); 1166 m->m_pkthdr.rcvif = ifp; 1167 m->m_pkthdr.len = m->m_len = len; 1168 1169 #if NBPFILTER > 0 1170 /* 1171 * Pass this up to any BPF listeners, but only 1172 * pass it up the stack if its for us. 1173 */ 1174 if (ifp->if_bpf) 1175 bpf_mtap(ifp->if_bpf, m); 1176 #endif /* NPBFILTER > 0 */ 1177 1178 /* Pass it on. */ 1179 (*ifp->if_input)(ifp, m); 1180 } 1181 1182 /* Update the receive pointer. */ 1183 sc->sc_rxptr = i; 1184 } 1185 1186 /* 1187 * ae_txintr: 1188 * 1189 * Helper; handle transmit interrupts. 1190 */ 1191 static void 1192 ae_txintr(struct ae_softc *sc) 1193 { 1194 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1195 struct ae_txsoft *txs; 1196 u_int32_t txstat; 1197 1198 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1199 sc->sc_dev.dv_xname, sc->sc_flags)); 1200 1201 ifp->if_flags &= ~IFF_OACTIVE; 1202 1203 /* 1204 * Go through our Tx list and free mbufs for those 1205 * frames that have been transmitted. 1206 */ 1207 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1208 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1209 txs->txs_ndescs, 1210 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1211 1212 #ifdef AE_DEBUG 1213 if (ifp->if_flags & IFF_DEBUG) { 1214 int i; 1215 printf(" txsoft %p transmit chain:\n", txs); 1216 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1217 printf(" descriptor %d:\n", i); 1218 printf(" ad_status: 0x%08x\n", 1219 sc->sc_txdescs[i].ad_status); 1220 printf(" ad_ctl: 0x%08x\n", 1221 sc->sc_txdescs[i].ad_ctl); 1222 printf(" ad_bufaddr1: 0x%08x\n", 1223 sc->sc_txdescs[i].ad_bufaddr1); 1224 printf(" ad_bufaddr2: 0x%08x\n", 1225 sc->sc_txdescs[i].ad_bufaddr2); 1226 if (i == txs->txs_lastdesc) 1227 break; 1228 } 1229 } 1230 #endif 1231 1232 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1233 if (txstat & ADSTAT_OWN) 1234 break; 1235 1236 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1237 1238 sc->sc_txfree += txs->txs_ndescs; 1239 1240 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1241 0, txs->txs_dmamap->dm_mapsize, 1242 BUS_DMASYNC_POSTWRITE); 1243 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1244 m_freem(txs->txs_mbuf); 1245 txs->txs_mbuf = NULL; 1246 1247 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1248 1249 /* 1250 * Check for errors and collisions. 1251 */ 1252 #ifdef AE_STATS 1253 if (txstat & ADSTAT_Tx_UF) 1254 sc->sc_stats.ts_tx_uf++; 1255 if (txstat & ADSTAT_Tx_TO) 1256 sc->sc_stats.ts_tx_to++; 1257 if (txstat & ADSTAT_Tx_EC) 1258 sc->sc_stats.ts_tx_ec++; 1259 if (txstat & ADSTAT_Tx_LC) 1260 sc->sc_stats.ts_tx_lc++; 1261 #endif 1262 1263 if (txstat & (ADSTAT_Tx_UF|ADSTAT_Tx_TO)) 1264 ifp->if_oerrors++; 1265 1266 if (txstat & ADSTAT_Tx_EC) 1267 ifp->if_collisions += 16; 1268 else 1269 ifp->if_collisions += ADSTAT_Tx_COLLISIONS(txstat); 1270 if (txstat & ADSTAT_Tx_LC) 1271 ifp->if_collisions++; 1272 1273 ifp->if_opackets++; 1274 } 1275 1276 /* 1277 * If there are no more pending transmissions, cancel the watchdog 1278 * timer. 1279 */ 1280 if (txs == NULL) 1281 ifp->if_timer = 0; 1282 } 1283 1284 #ifdef AE_STATS 1285 void 1286 ae_print_stats(struct ae_softc *sc) 1287 { 1288 1289 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1290 sc->sc_dev.dv_xname, 1291 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1292 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1293 } 1294 #endif 1295 1296 /* 1297 * ae_reset: 1298 * 1299 * Perform a soft reset on the chip. 1300 */ 1301 void 1302 ae_reset(struct ae_softc *sc) 1303 { 1304 int i; 1305 1306 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1307 AE_BARRIER(sc); 1308 1309 /* 1310 * The chip doesn't take itself out of reset automatically. 1311 * We need to do so after 2us. 1312 */ 1313 delay(10); 1314 AE_WRITE(sc, CSR_BUSMODE, 0); 1315 AE_BARRIER(sc); 1316 1317 for (i = 0; i < 1000; i++) { 1318 /* 1319 * Wait a bit for the reset to complete before peeking 1320 * at the chip again. 1321 */ 1322 delay(10); 1323 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1324 break; 1325 } 1326 1327 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1328 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1329 1330 delay(1000); 1331 } 1332 1333 /* 1334 * ae_init: [ ifnet interface function ] 1335 * 1336 * Initialize the interface. Must be called at splnet(). 1337 */ 1338 static int 1339 ae_init(struct ifnet *ifp) 1340 { 1341 struct ae_softc *sc = ifp->if_softc; 1342 struct ae_txsoft *txs; 1343 struct ae_rxsoft *rxs; 1344 uint8_t *enaddr; 1345 int i, error = 0; 1346 1347 if ((error = ae_enable(sc)) != 0) 1348 goto out; 1349 1350 /* 1351 * Cancel any pending I/O. 1352 */ 1353 ae_stop(ifp, 0); 1354 1355 /* 1356 * Reset the chip to a known state. 1357 */ 1358 ae_reset(sc); 1359 1360 /* 1361 * Initialize the BUSMODE register. 1362 */ 1363 AE_WRITE(sc, CSR_BUSMODE, 1364 /* XXX: not sure if this is a good thing or not... */ 1365 //BUSMODE_ALIGN_16B | 1366 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1367 AE_BARRIER(sc); 1368 1369 /* 1370 * Initialize the transmit descriptor ring. 1371 */ 1372 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1373 for (i = 0; i < AE_NTXDESC; i++) { 1374 sc->sc_txdescs[i].ad_ctl = 0; 1375 sc->sc_txdescs[i].ad_bufaddr2 = 1376 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1377 } 1378 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1379 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1380 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1381 sc->sc_txfree = AE_NTXDESC; 1382 sc->sc_txnext = 0; 1383 1384 /* 1385 * Initialize the transmit job descriptors. 1386 */ 1387 SIMPLEQ_INIT(&sc->sc_txfreeq); 1388 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1389 for (i = 0; i < AE_TXQUEUELEN; i++) { 1390 txs = &sc->sc_txsoft[i]; 1391 txs->txs_mbuf = NULL; 1392 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1393 } 1394 1395 /* 1396 * Initialize the receive descriptor and receive job 1397 * descriptor rings. 1398 */ 1399 for (i = 0; i < AE_NRXDESC; i++) { 1400 rxs = &sc->sc_rxsoft[i]; 1401 if (rxs->rxs_mbuf == NULL) { 1402 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1403 printf("%s: unable to allocate or map rx " 1404 "buffer %d, error = %d\n", 1405 sc->sc_dev.dv_xname, i, error); 1406 /* 1407 * XXX Should attempt to run with fewer receive 1408 * XXX buffers instead of just failing. 1409 */ 1410 ae_rxdrain(sc); 1411 goto out; 1412 } 1413 } else 1414 AE_INIT_RXDESC(sc, i); 1415 } 1416 sc->sc_rxptr = 0; 1417 1418 /* 1419 * Initialize the interrupt mask and enable interrupts. 1420 */ 1421 /* normal interrupts */ 1422 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1423 1424 /* abnormal interrupts */ 1425 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1426 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1427 1428 sc->sc_rxint_mask = STATUS_RI|STATUS_RU; 1429 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT; 1430 1431 sc->sc_rxint_mask &= sc->sc_inten; 1432 sc->sc_txint_mask &= sc->sc_inten; 1433 1434 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1435 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1436 1437 /* 1438 * Give the transmit and receive rings to the chip. 1439 */ 1440 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1441 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1442 AE_BARRIER(sc); 1443 1444 /* 1445 * Set the station address. 1446 */ 1447 enaddr = LLADDR(ifp->if_sadl); 1448 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1449 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1450 enaddr[1] << 8 | enaddr[0]); 1451 AE_BARRIER(sc); 1452 1453 /* 1454 * Set the receive filter. This will start the transmit and 1455 * receive processes. 1456 */ 1457 ae_filter_setup(sc); 1458 1459 /* 1460 * Set the current media. 1461 */ 1462 ae_mediachange(ifp); 1463 1464 /* 1465 * Start the mac. 1466 */ 1467 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1468 AE_BARRIER(sc); 1469 1470 /* 1471 * Write out the opmode. 1472 */ 1473 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1474 ae_txthresh[sc->sc_txthresh].txth_opmode); 1475 /* 1476 * Start the receive process. 1477 */ 1478 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1479 AE_BARRIER(sc); 1480 1481 if (sc->sc_tick != NULL) { 1482 /* Start the one second clock. */ 1483 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1484 } 1485 1486 /* 1487 * Note that the interface is now running. 1488 */ 1489 ifp->if_flags |= IFF_RUNNING; 1490 ifp->if_flags &= ~IFF_OACTIVE; 1491 sc->sc_if_flags = ifp->if_flags; 1492 1493 out: 1494 if (error) { 1495 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1496 ifp->if_timer = 0; 1497 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1498 } 1499 return (error); 1500 } 1501 1502 /* 1503 * ae_enable: 1504 * 1505 * Enable the chip. 1506 */ 1507 static int 1508 ae_enable(struct ae_softc *sc) 1509 { 1510 1511 if (AE_IS_ENABLED(sc) == 0) { 1512 sc->sc_ih = arbus_intr_establish(sc->sc_irq, ae_intr, sc); 1513 if (sc->sc_ih == NULL) { 1514 printf("%s: unable to establish interrupt\n", 1515 sc->sc_dev.dv_xname); 1516 return (EIO); 1517 } 1518 sc->sc_flags |= AE_ENABLED; 1519 } 1520 return (0); 1521 } 1522 1523 /* 1524 * ae_disable: 1525 * 1526 * Disable the chip. 1527 */ 1528 static void 1529 ae_disable(struct ae_softc *sc) 1530 { 1531 1532 if (AE_IS_ENABLED(sc)) { 1533 arbus_intr_disestablish(sc->sc_ih); 1534 sc->sc_flags &= ~AE_ENABLED; 1535 } 1536 } 1537 1538 /* 1539 * ae_power: 1540 * 1541 * Power management (suspend/resume) hook. 1542 */ 1543 static void 1544 ae_power(int why, void *arg) 1545 { 1546 struct ae_softc *sc = arg; 1547 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1548 int s; 1549 1550 printf("power called: %d, %x\n", why, (uint32_t)arg); 1551 s = splnet(); 1552 switch (why) { 1553 case PWR_STANDBY: 1554 /* do nothing! */ 1555 break; 1556 case PWR_SUSPEND: 1557 ae_stop(ifp, 0); 1558 ae_disable(sc); 1559 break; 1560 case PWR_RESUME: 1561 if (ifp->if_flags & IFF_UP) { 1562 ae_enable(sc); 1563 ae_init(ifp); 1564 } 1565 break; 1566 case PWR_SOFTSUSPEND: 1567 case PWR_SOFTSTANDBY: 1568 case PWR_SOFTRESUME: 1569 break; 1570 } 1571 splx(s); 1572 } 1573 1574 /* 1575 * ae_rxdrain: 1576 * 1577 * Drain the receive queue. 1578 */ 1579 static void 1580 ae_rxdrain(struct ae_softc *sc) 1581 { 1582 struct ae_rxsoft *rxs; 1583 int i; 1584 1585 for (i = 0; i < AE_NRXDESC; i++) { 1586 rxs = &sc->sc_rxsoft[i]; 1587 if (rxs->rxs_mbuf != NULL) { 1588 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1589 m_freem(rxs->rxs_mbuf); 1590 rxs->rxs_mbuf = NULL; 1591 } 1592 } 1593 } 1594 1595 /* 1596 * ae_stop: [ ifnet interface function ] 1597 * 1598 * Stop transmission on the interface. 1599 */ 1600 static void 1601 ae_stop(struct ifnet *ifp, int disable) 1602 { 1603 struct ae_softc *sc = ifp->if_softc; 1604 struct ae_txsoft *txs; 1605 1606 if (sc->sc_tick != NULL) { 1607 /* Stop the one second clock. */ 1608 callout_stop(&sc->sc_tick_callout); 1609 } 1610 1611 /* Down the MII. */ 1612 mii_down(&sc->sc_mii); 1613 1614 /* Disable interrupts. */ 1615 AE_WRITE(sc, CSR_INTEN, 0); 1616 1617 /* Stop the transmit and receive processes. */ 1618 AE_WRITE(sc, CSR_OPMODE, 0); 1619 AE_WRITE(sc, CSR_RXLIST, 0); 1620 AE_WRITE(sc, CSR_TXLIST, 0); 1621 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1622 AE_BARRIER(sc); 1623 1624 /* 1625 * Release any queued transmit buffers. 1626 */ 1627 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1628 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1629 if (txs->txs_mbuf != NULL) { 1630 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1631 m_freem(txs->txs_mbuf); 1632 txs->txs_mbuf = NULL; 1633 } 1634 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1635 } 1636 1637 if (disable) { 1638 ae_rxdrain(sc); 1639 ae_disable(sc); 1640 } 1641 1642 /* 1643 * Mark the interface down and cancel the watchdog timer. 1644 */ 1645 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1646 sc->sc_if_flags = ifp->if_flags; 1647 ifp->if_timer = 0; 1648 1649 /* 1650 * Reset the chip (needed on some flavors to actually disable it). 1651 */ 1652 ae_reset(sc); 1653 } 1654 1655 /* 1656 * ae_add_rxbuf: 1657 * 1658 * Add a receive buffer to the indicated descriptor. 1659 */ 1660 static int 1661 ae_add_rxbuf(struct ae_softc *sc, int idx) 1662 { 1663 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1664 struct mbuf *m; 1665 int error; 1666 1667 MGETHDR(m, M_DONTWAIT, MT_DATA); 1668 if (m == NULL) 1669 return (ENOBUFS); 1670 1671 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1672 MCLGET(m, M_DONTWAIT); 1673 if ((m->m_flags & M_EXT) == 0) { 1674 m_freem(m); 1675 return (ENOBUFS); 1676 } 1677 1678 if (rxs->rxs_mbuf != NULL) 1679 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1680 1681 rxs->rxs_mbuf = m; 1682 1683 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1684 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1685 BUS_DMA_READ|BUS_DMA_NOWAIT); 1686 if (error) { 1687 printf("%s: can't load rx DMA map %d, error = %d\n", 1688 sc->sc_dev.dv_xname, idx, error); 1689 panic("ae_add_rxbuf"); /* XXX */ 1690 } 1691 1692 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1693 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1694 1695 AE_INIT_RXDESC(sc, idx); 1696 1697 return (0); 1698 } 1699 1700 /* 1701 * ae_filter_setup: 1702 * 1703 * Set the chip's receive filter. 1704 */ 1705 static void 1706 ae_filter_setup(struct ae_softc *sc) 1707 { 1708 struct ethercom *ec = &sc->sc_ethercom; 1709 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1710 struct ether_multi *enm; 1711 struct ether_multistep step; 1712 uint32_t hash, mchash[2]; 1713 uint32_t macctl = 0; 1714 1715 /* 1716 * If the chip is running, we need to reset the interface, 1717 * and will revisit here (with IFF_RUNNING) clear. The 1718 * chip seems to really not like to have its multicast 1719 * filter programmed without a reset. 1720 */ 1721 if (ifp->if_flags & IFF_RUNNING) { 1722 (void) ae_init(ifp); 1723 return; 1724 } 1725 1726 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1727 sc->sc_dev.dv_xname, sc->sc_flags)); 1728 1729 macctl = AE_READ(sc, CSR_MACCTL); 1730 macctl &= ~(MACCTL_PR | MACCTL_PM); 1731 macctl |= MACCTL_HASH; 1732 macctl |= MACCTL_HBD; 1733 macctl |= MACCTL_PR; 1734 1735 if (ifp->if_flags & IFF_PROMISC) { 1736 macctl |= MACCTL_PR; 1737 goto allmulti; 1738 } 1739 1740 mchash[0] = mchash[1] = 0; 1741 1742 ETHER_FIRST_MULTI(step, ec, enm); 1743 while (enm != NULL) { 1744 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1745 /* 1746 * We must listen to a range of multicast addresses. 1747 * For now, just accept all multicasts, rather than 1748 * trying to set only those filter bits needed to match 1749 * the range. (At this time, the only use of address 1750 * ranges is for IP multicast routing, for which the 1751 * range is big enough to require all bits set.) 1752 */ 1753 goto allmulti; 1754 } 1755 1756 /* Verify whether we use big or little endian hashes */ 1757 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1758 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1759 ETHER_NEXT_MULTI(step, enm); 1760 } 1761 ifp->if_flags &= ~IFF_ALLMULTI; 1762 goto setit; 1763 1764 allmulti: 1765 ifp->if_flags |= IFF_ALLMULTI; 1766 mchash[0] = mchash[1] = 0xffffffff; 1767 macctl |= MACCTL_PM; 1768 1769 setit: 1770 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1771 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1772 1773 AE_WRITE(sc, CSR_MACCTL, macctl); 1774 AE_BARRIER(sc); 1775 1776 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1777 sc->sc_dev.dv_xname, macctl)); 1778 } 1779 1780 /* 1781 * ae_idle: 1782 * 1783 * Cause the transmit and/or receive processes to go idle. 1784 */ 1785 void 1786 ae_idle(struct ae_softc *sc, u_int32_t bits) 1787 { 1788 static const char * const txstate_names[] = { 1789 "STOPPED", 1790 "RUNNING - FETCH", 1791 "RUNNING - WAIT", 1792 "RUNNING - READING", 1793 "-- RESERVED --", 1794 "RUNNING - SETUP", 1795 "SUSPENDED", 1796 "RUNNING - CLOSE", 1797 }; 1798 static const char * const rxstate_names[] = { 1799 "STOPPED", 1800 "RUNNING - FETCH", 1801 "RUNNING - CHECK", 1802 "RUNNING - WAIT", 1803 "SUSPENDED", 1804 "RUNNING - CLOSE", 1805 "RUNNING - FLUSH", 1806 "RUNNING - QUEUE", 1807 }; 1808 1809 u_int32_t csr, ackmask = 0; 1810 int i; 1811 1812 if (bits & OPMODE_ST) 1813 ackmask |= STATUS_TPS; 1814 1815 if (bits & OPMODE_SR) 1816 ackmask |= STATUS_RPS; 1817 1818 AE_CLR(sc, CSR_OPMODE, bits); 1819 1820 for (i = 0; i < 1000; i++) { 1821 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1822 break; 1823 delay(10); 1824 } 1825 1826 csr = AE_READ(sc, CSR_STATUS); 1827 if ((csr & ackmask) != ackmask) { 1828 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1829 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1830 printf("%s: transmit process failed to idle: " 1831 "state %s\n", sc->sc_dev.dv_xname, 1832 txstate_names[(csr & STATUS_TS) >> 20]); 1833 } 1834 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1835 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1836 printf("%s: receive process failed to idle: " 1837 "state %s\n", sc->sc_dev.dv_xname, 1838 rxstate_names[(csr & STATUS_RS) >> 17]); 1839 } 1840 } 1841 } 1842 1843 /***************************************************************************** 1844 * Generic media support functions. 1845 *****************************************************************************/ 1846 1847 /* 1848 * ae_mediastatus: [ifmedia interface function] 1849 * 1850 * Query the current media. 1851 */ 1852 void 1853 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1854 { 1855 struct ae_softc *sc = ifp->if_softc; 1856 1857 if (AE_IS_ENABLED(sc) == 0) { 1858 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1859 ifmr->ifm_status = 0; 1860 return; 1861 } 1862 1863 mii_pollstat(&sc->sc_mii); 1864 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1865 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1866 } 1867 1868 /* 1869 * ae_mediachange: [ifmedia interface function] 1870 * 1871 * Update the current media. 1872 */ 1873 int 1874 ae_mediachange(struct ifnet *ifp) 1875 { 1876 struct ae_softc *sc = ifp->if_softc; 1877 1878 if ((ifp->if_flags & IFF_UP) == 0) 1879 return (0); 1880 1881 mii_mediachg(&sc->sc_mii); 1882 return (0); 1883 } 1884 1885 /***************************************************************************** 1886 * Support functions for MII-attached media. 1887 *****************************************************************************/ 1888 1889 /* 1890 * ae_mii_tick: 1891 * 1892 * One second timer, used to tick the MII. 1893 */ 1894 static void 1895 ae_mii_tick(void *arg) 1896 { 1897 struct ae_softc *sc = arg; 1898 int s; 1899 1900 if (!device_is_active(&sc->sc_dev)) 1901 return; 1902 1903 s = splnet(); 1904 mii_tick(&sc->sc_mii); 1905 splx(s); 1906 1907 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1908 } 1909 1910 /* 1911 * ae_mii_statchg: [mii interface function] 1912 * 1913 * Callback from PHY when media changes. 1914 */ 1915 static void 1916 ae_mii_statchg(struct device *self) 1917 { 1918 struct ae_softc *sc = (struct ae_softc *)self; 1919 uint32_t macctl, flowc; 1920 1921 //opmode = AE_READ(sc, CSR_OPMODE); 1922 macctl = AE_READ(sc, CSR_MACCTL); 1923 1924 /* XXX: do we need to do this? */ 1925 /* Idle the transmit and receive processes. */ 1926 //ae_idle(sc, OPMODE_ST|OPMODE_SR); 1927 1928 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1929 flowc = FLOWC_FCE; 1930 macctl &= ~MACCTL_DRO; 1931 macctl |= MACCTL_FDX; 1932 } else { 1933 flowc = 0; /* cannot do flow control in HDX */ 1934 macctl |= MACCTL_DRO; 1935 macctl &= ~MACCTL_FDX; 1936 } 1937 1938 AE_WRITE(sc, CSR_FLOWC, flowc); 1939 AE_WRITE(sc, CSR_MACCTL, macctl); 1940 1941 /* restore operational mode */ 1942 //AE_WRITE(sc, CSR_OPMODE, opmode); 1943 AE_BARRIER(sc); 1944 } 1945 1946 /* 1947 * ae_mii_readreg: 1948 * 1949 * Read a PHY register. 1950 */ 1951 static int 1952 ae_mii_readreg(struct device *self, int phy, int reg) 1953 { 1954 struct ae_softc *sc = (struct ae_softc *)self; 1955 uint32_t addr; 1956 int i; 1957 1958 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1959 AE_WRITE(sc, CSR_MIIADDR, addr); 1960 AE_BARRIER(sc); 1961 for (i = 0; i < 100000000; i++) { 1962 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1963 break; 1964 } 1965 1966 return (AE_READ(sc, CSR_MIIDATA) & 0xffff); 1967 } 1968 1969 /* 1970 * ae_mii_writereg: 1971 * 1972 * Write a PHY register. 1973 */ 1974 static void 1975 ae_mii_writereg(struct device *self, int phy, int reg, int val) 1976 { 1977 struct ae_softc *sc = (struct ae_softc *)self; 1978 uint32_t addr; 1979 int i; 1980 1981 /* write the data register */ 1982 AE_WRITE(sc, CSR_MIIDATA, val); 1983 1984 /* write the address to latch it in */ 1985 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1986 MIIADDR_WRITE; 1987 AE_WRITE(sc, CSR_MIIADDR, addr); 1988 AE_BARRIER(sc); 1989 1990 for (i = 0; i < 100000000; i++) { 1991 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1992 break; 1993 } 1994 } 1995
Indexes created Wed Sep 24 02:09:48 GMT 2025