if_ae.c revision 1.13
1 /* $Id: if_ae.c,v 1.13 2008/03/11 23:58:06 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 3. All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the NetBSD 61 * Foundation, Inc. and its contributors. 62 * 4. Neither the name of The NetBSD Foundation nor the names of its 63 * contributors may be used to endorse or promote products derived 64 * from this software without specific prior written permission. 65 * 66 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 67 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 68 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 69 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 70 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 71 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 72 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 73 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 74 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 75 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 76 * POSSIBILITY OF SUCH DAMAGE. 77 */ 78 79 /* 80 * Device driver for the onboard ethernet MAC found on the AR5312 81 * chip's AHB bus. 82 * 83 * This device is very simliar to the tulip in most regards, and 84 * the code is directly derived from NetBSD's tulip.c. However, it 85 * is different enough that it did not seem to be a good idea to 86 * add further complexity to the tulip driver, so we have our own. 87 * 88 * Also tulip has a lot of complexity in it for various parts/options 89 * that we don't need, and on these little boxes with only ~8MB RAM, we 90 * don't want any extra bloat. 91 */ 92 93 /* 94 * TODO: 95 * 96 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 97 * inbound packets on a half-word boundary, which would make life easier 98 * for TCP/IP. (Aligning IP headers on a word.) 99 * 100 * 2) There is stuff in original tulip to shut down the device when reacting 101 * to a a change in link status. Is that needed. 102 * 103 * 3) Test with variety of 10/100 HDX/FDX scenarios. 104 * 105 */ 106 107 #include <sys/cdefs.h> 108 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.13 2008/03/11 23:58:06 dyoung Exp $"); 109 110 #include "bpfilter.h" 111 112 #include <sys/param.h> 113 #include <sys/systm.h> 114 #include <sys/callout.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/kernel.h> 118 #include <sys/socket.h> 119 #include <sys/ioctl.h> 120 #include <sys/errno.h> 121 #include <sys/device.h> 122 123 #include <machine/endian.h> 124 125 #include <uvm/uvm_extern.h> 126 127 #include <net/if.h> 128 #include <net/if_dl.h> 129 #include <net/if_media.h> 130 #include <net/if_ether.h> 131 132 #if NBPFILTER > 0 133 #include <net/bpf.h> 134 #endif 135 136 #include <machine/bus.h> 137 #include <machine/intr.h> 138 139 #include <dev/mii/mii.h> 140 #include <dev/mii/miivar.h> 141 #include <dev/mii/mii_bitbang.h> 142 143 #include <mips/atheros/include/arbusvar.h> 144 #include <mips/atheros/dev/aereg.h> 145 #include <mips/atheros/dev/aevar.h> 146 147 static const struct { 148 u_int32_t txth_opmode; /* OPMODE bits */ 149 const char *txth_name; /* name of mode */ 150 } ae_txthresh[] = { 151 { OPMODE_TR_32, "32 words" }, 152 { OPMODE_TR_64, "64 words" }, 153 { OPMODE_TR_128, "128 words" }, 154 { OPMODE_TR_256, "256 words" }, 155 { OPMODE_SF, "store and forward mode" }, 156 { 0, NULL }, 157 }; 158 159 static int ae_match(device_t, struct cfdata *, void *); 160 static void ae_attach(device_t, device_t, void *); 161 static int ae_detach(device_t, int); 162 static int ae_activate(device_t, enum devact); 163 164 static void ae_reset(struct ae_softc *); 165 static void ae_idle(struct ae_softc *, u_int32_t); 166 167 static void ae_start(struct ifnet *); 168 static void ae_watchdog(struct ifnet *); 169 static int ae_ioctl(struct ifnet *, u_long, void *); 170 static int ae_init(struct ifnet *); 171 static void ae_stop(struct ifnet *, int); 172 173 static void ae_shutdown(void *); 174 175 static void ae_rxdrain(struct ae_softc *); 176 static int ae_add_rxbuf(struct ae_softc *, int); 177 178 static int ae_enable(struct ae_softc *); 179 static void ae_disable(struct ae_softc *); 180 static void ae_power(int, void *); 181 182 static void ae_filter_setup(struct ae_softc *); 183 184 static int ae_intr(void *); 185 static void ae_rxintr(struct ae_softc *); 186 static void ae_txintr(struct ae_softc *); 187 188 static void ae_mii_tick(void *); 189 static void ae_mii_statchg(device_t); 190 191 static int ae_mii_readreg(device_t, int, int); 192 static void ae_mii_writereg(device_t, int, int, int); 193 194 #ifdef AE_DEBUG 195 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 196 printf x 197 #else 198 #define DPRINTF(sc, x) /* nothing */ 199 #endif 200 201 #ifdef AE_STATS 202 static void ae_print_stats(struct ae_softc *); 203 #endif 204 205 CFATTACH_DECL(ae, sizeof(struct ae_softc), 206 ae_match, ae_attach, ae_detach, ae_activate); 207 208 /* 209 * ae_match: 210 * 211 * Check for a device match. 212 */ 213 int 214 ae_match(device_t parent, struct cfdata *cf, void *aux) 215 { 216 struct arbus_attach_args *aa = aux; 217 218 if (strcmp(aa->aa_name, cf->cf_name) == 0) 219 return 1; 220 221 return 0; 222 223 } 224 225 /* 226 * ae_attach: 227 * 228 * Attach an ae interface to the system. 229 */ 230 void 231 ae_attach(device_t parent, device_t self, void *aux) 232 { 233 const uint8_t *enaddr; 234 prop_data_t ea; 235 struct ae_softc *sc = device_private(self); 236 struct arbus_attach_args *aa = aux; 237 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 238 int i, error; 239 240 callout_init(&sc->sc_tick_callout, 0); 241 242 printf(": Atheros AR531X 10/100 Ethernet\n"); 243 244 /* 245 * Try to get MAC address. 246 */ 247 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 248 if (ea == NULL) { 249 printf("%s: unable to get mac-addr property\n", 250 sc->sc_dev.dv_xname); 251 return; 252 } 253 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 254 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 255 enaddr = prop_data_data_nocopy(ea); 256 257 /* Announce ourselves. */ 258 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 259 ether_sprintf(enaddr)); 260 261 sc->sc_cirq = aa->aa_cirq; 262 sc->sc_mirq = aa->aa_mirq; 263 sc->sc_st = aa->aa_bst; 264 sc->sc_dmat = aa->aa_dmat; 265 266 SIMPLEQ_INIT(&sc->sc_txfreeq); 267 SIMPLEQ_INIT(&sc->sc_txdirtyq); 268 269 /* 270 * Map registers. 271 */ 272 sc->sc_size = aa->aa_size; 273 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 274 &sc->sc_sh)) != 0) { 275 printf("%s: unable to map registers, error = %d\n", 276 sc->sc_dev.dv_xname, error); 277 goto fail_0; 278 } 279 280 /* 281 * Allocate the control data structures, and create and load the 282 * DMA map for it. 283 */ 284 if ((error = bus_dmamem_alloc(sc->sc_dmat, 285 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 286 1, &sc->sc_cdnseg, 0)) != 0) { 287 printf("%s: unable to allocate control data, error = %d\n", 288 sc->sc_dev.dv_xname, error); 289 goto fail_1; 290 } 291 292 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 293 sizeof(struct ae_control_data), (void **)&sc->sc_control_data, 294 BUS_DMA_COHERENT)) != 0) { 295 printf("%s: unable to map control data, error = %d\n", 296 sc->sc_dev.dv_xname, error); 297 goto fail_2; 298 } 299 300 if ((error = bus_dmamap_create(sc->sc_dmat, 301 sizeof(struct ae_control_data), 1, 302 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 303 printf("%s: unable to create control data DMA map, " 304 "error = %d\n", sc->sc_dev.dv_xname, error); 305 goto fail_3; 306 } 307 308 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 309 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 310 0)) != 0) { 311 printf("%s: unable to load control data DMA map, error = %d\n", 312 sc->sc_dev.dv_xname, error); 313 goto fail_4; 314 } 315 316 /* 317 * Create the transmit buffer DMA maps. 318 */ 319 for (i = 0; i < AE_TXQUEUELEN; i++) { 320 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 321 AE_NTXSEGS, MCLBYTES, 0, 0, 322 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 323 printf("%s: unable to create tx DMA map %d, " 324 "error = %d\n", sc->sc_dev.dv_xname, i, error); 325 goto fail_5; 326 } 327 } 328 329 /* 330 * Create the receive buffer DMA maps. 331 */ 332 for (i = 0; i < AE_NRXDESC; i++) { 333 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 334 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 335 printf("%s: unable to create rx DMA map %d, " 336 "error = %d\n", sc->sc_dev.dv_xname, i, error); 337 goto fail_6; 338 } 339 sc->sc_rxsoft[i].rxs_mbuf = NULL; 340 } 341 342 /* 343 * Reset the chip to a known state. 344 */ 345 ae_reset(sc); 346 347 /* 348 * From this point forward, the attachment cannot fail. A failure 349 * before this point releases all resources that may have been 350 * allocated. 351 */ 352 sc->sc_flags |= AE_ATTACHED; 353 354 /* 355 * Initialize our media structures. This may probe the MII, if 356 * present. 357 */ 358 sc->sc_mii.mii_ifp = ifp; 359 sc->sc_mii.mii_readreg = ae_mii_readreg; 360 sc->sc_mii.mii_writereg = ae_mii_writereg; 361 sc->sc_mii.mii_statchg = ae_mii_statchg; 362 sc->sc_ethercom.ec_mii = &sc->sc_mii; 363 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 364 ether_mediastatus); 365 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 366 MII_OFFSET_ANY, 0); 367 368 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 369 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 370 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 371 } else 372 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 373 374 sc->sc_tick = ae_mii_tick; 375 376 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 377 ifp->if_softc = sc; 378 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 379 sc->sc_if_flags = ifp->if_flags; 380 ifp->if_ioctl = ae_ioctl; 381 ifp->if_start = ae_start; 382 ifp->if_watchdog = ae_watchdog; 383 ifp->if_init = ae_init; 384 ifp->if_stop = ae_stop; 385 IFQ_SET_READY(&ifp->if_snd); 386 387 /* 388 * We can support 802.1Q VLAN-sized frames. 389 */ 390 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 391 392 /* 393 * Attach the interface. 394 */ 395 if_attach(ifp); 396 ether_ifattach(ifp, enaddr); 397 398 #if NRND > 0 399 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 400 RND_TYPE_NET, 0); 401 #endif 402 403 /* 404 * Make sure the interface is shutdown during reboot. 405 */ 406 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 407 if (sc->sc_sdhook == NULL) 408 printf("%s: WARNING: unable to establish shutdown hook\n", 409 sc->sc_dev.dv_xname); 410 411 /* 412 * Add a suspend hook to make sure we come back up after a 413 * resume. 414 */ 415 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 416 ae_power, sc); 417 if (sc->sc_powerhook == NULL) 418 printf("%s: WARNING: unable to establish power hook\n", 419 sc->sc_dev.dv_xname); 420 return; 421 422 /* 423 * Free any resources we've allocated during the failed attach 424 * attempt. Do this in reverse order and fall through. 425 */ 426 fail_6: 427 for (i = 0; i < AE_NRXDESC; i++) { 428 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 429 bus_dmamap_destroy(sc->sc_dmat, 430 sc->sc_rxsoft[i].rxs_dmamap); 431 } 432 fail_5: 433 for (i = 0; i < AE_TXQUEUELEN; i++) { 434 if (sc->sc_txsoft[i].txs_dmamap != NULL) 435 bus_dmamap_destroy(sc->sc_dmat, 436 sc->sc_txsoft[i].txs_dmamap); 437 } 438 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 439 fail_4: 440 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 441 fail_3: 442 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 443 sizeof(struct ae_control_data)); 444 fail_2: 445 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 446 fail_1: 447 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 448 fail_0: 449 return; 450 } 451 452 /* 453 * ae_activate: 454 * 455 * Handle device activation/deactivation requests. 456 */ 457 int 458 ae_activate(device_t self, enum devact act) 459 { 460 struct ae_softc *sc = device_private(self); 461 int s, error = 0; 462 463 s = splnet(); 464 switch (act) { 465 case DVACT_ACTIVATE: 466 error = EOPNOTSUPP; 467 break; 468 469 case DVACT_DEACTIVATE: 470 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 471 if_deactivate(&sc->sc_ethercom.ec_if); 472 break; 473 } 474 splx(s); 475 476 return (error); 477 } 478 479 /* 480 * ae_detach: 481 * 482 * Detach a device interface. 483 */ 484 int 485 ae_detach(device_t self, int flags) 486 { 487 struct ae_softc *sc = device_private(self); 488 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 489 struct ae_rxsoft *rxs; 490 struct ae_txsoft *txs; 491 int i; 492 493 /* 494 * Succeed now if there isn't any work to do. 495 */ 496 if ((sc->sc_flags & AE_ATTACHED) == 0) 497 return (0); 498 499 /* Unhook our tick handler. */ 500 if (sc->sc_tick) 501 callout_stop(&sc->sc_tick_callout); 502 503 /* Detach all PHYs */ 504 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 505 506 /* Delete all remaining media. */ 507 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 508 509 #if NRND > 0 510 rnd_detach_source(&sc->sc_rnd_source); 511 #endif 512 ether_ifdetach(ifp); 513 if_detach(ifp); 514 515 for (i = 0; i < AE_NRXDESC; i++) { 516 rxs = &sc->sc_rxsoft[i]; 517 if (rxs->rxs_mbuf != NULL) { 518 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 519 m_freem(rxs->rxs_mbuf); 520 rxs->rxs_mbuf = NULL; 521 } 522 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 523 } 524 for (i = 0; i < AE_TXQUEUELEN; i++) { 525 txs = &sc->sc_txsoft[i]; 526 if (txs->txs_mbuf != NULL) { 527 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 528 m_freem(txs->txs_mbuf); 529 txs->txs_mbuf = NULL; 530 } 531 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 532 } 533 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 534 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 535 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 536 sizeof(struct ae_control_data)); 537 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 538 539 shutdownhook_disestablish(sc->sc_sdhook); 540 powerhook_disestablish(sc->sc_powerhook); 541 542 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 543 544 545 return (0); 546 } 547 548 /* 549 * ae_shutdown: 550 * 551 * Make sure the interface is stopped at reboot time. 552 */ 553 static void 554 ae_shutdown(void *arg) 555 { 556 struct ae_softc *sc = arg; 557 558 ae_stop(&sc->sc_ethercom.ec_if, 1); 559 } 560 561 /* 562 * ae_start: [ifnet interface function] 563 * 564 * Start packet transmission on the interface. 565 */ 566 static void 567 ae_start(struct ifnet *ifp) 568 { 569 struct ae_softc *sc = ifp->if_softc; 570 struct mbuf *m0, *m; 571 struct ae_txsoft *txs, *last_txs = NULL; 572 bus_dmamap_t dmamap; 573 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 574 575 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 576 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 577 578 579 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 580 return; 581 582 /* 583 * Remember the previous number of free descriptors and 584 * the first descriptor we'll use. 585 */ 586 ofree = sc->sc_txfree; 587 firsttx = sc->sc_txnext; 588 589 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 590 sc->sc_dev.dv_xname, ofree, firsttx)); 591 592 /* 593 * Loop through the send queue, setting up transmit descriptors 594 * until we drain the queue, or use up all available transmit 595 * descriptors. 596 */ 597 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 598 sc->sc_txfree != 0) { 599 /* 600 * Grab a packet off the queue. 601 */ 602 IFQ_POLL(&ifp->if_snd, m0); 603 if (m0 == NULL) 604 break; 605 m = NULL; 606 607 dmamap = txs->txs_dmamap; 608 609 /* 610 * Load the DMA map. If this fails, the packet either 611 * didn't fit in the alloted number of segments, or we were 612 * short on resources. In this case, we'll copy and try 613 * again. 614 */ 615 if (((mtod(m0, uintptr_t) & 3) != 0) || 616 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 617 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 618 MGETHDR(m, M_DONTWAIT, MT_DATA); 619 if (m == NULL) { 620 printf("%s: unable to allocate Tx mbuf\n", 621 sc->sc_dev.dv_xname); 622 break; 623 } 624 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 625 if (m0->m_pkthdr.len > MHLEN) { 626 MCLGET(m, M_DONTWAIT); 627 if ((m->m_flags & M_EXT) == 0) { 628 printf("%s: unable to allocate Tx " 629 "cluster\n", sc->sc_dev.dv_xname); 630 m_freem(m); 631 break; 632 } 633 } 634 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 635 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 636 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 637 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 638 if (error) { 639 printf("%s: unable to load Tx buffer, " 640 "error = %d\n", sc->sc_dev.dv_xname, 641 error); 642 break; 643 } 644 } 645 646 /* 647 * Ensure we have enough descriptors free to describe 648 * the packet. 649 */ 650 if (dmamap->dm_nsegs > sc->sc_txfree) { 651 /* 652 * Not enough free descriptors to transmit this 653 * packet. We haven't committed to anything yet, 654 * so just unload the DMA map, put the packet 655 * back on the queue, and punt. Notify the upper 656 * layer that there are no more slots left. 657 * 658 * XXX We could allocate an mbuf and copy, but 659 * XXX it is worth it? 660 */ 661 ifp->if_flags |= IFF_OACTIVE; 662 bus_dmamap_unload(sc->sc_dmat, dmamap); 663 if (m != NULL) 664 m_freem(m); 665 break; 666 } 667 668 IFQ_DEQUEUE(&ifp->if_snd, m0); 669 if (m != NULL) { 670 m_freem(m0); 671 m0 = m; 672 } 673 674 /* 675 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 676 */ 677 678 /* Sync the DMA map. */ 679 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 680 BUS_DMASYNC_PREWRITE); 681 682 /* 683 * Initialize the transmit descriptors. 684 */ 685 for (nexttx = sc->sc_txnext, seg = 0; 686 seg < dmamap->dm_nsegs; 687 seg++, nexttx = AE_NEXTTX(nexttx)) { 688 /* 689 * If this is the first descriptor we're 690 * enqueueing, don't set the OWN bit just 691 * yet. That could cause a race condition. 692 * We'll do it below. 693 */ 694 sc->sc_txdescs[nexttx].ad_status = 695 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 696 sc->sc_txdescs[nexttx].ad_bufaddr1 = 697 dmamap->dm_segs[seg].ds_addr; 698 sc->sc_txdescs[nexttx].ad_ctl = 699 (dmamap->dm_segs[seg].ds_len << 700 ADCTL_SIZE1_SHIFT) | 701 (nexttx == (AE_NTXDESC - 1) ? 702 ADCTL_ER : 0); 703 lasttx = nexttx; 704 } 705 706 KASSERT(lasttx != -1); 707 708 /* Set `first segment' and `last segment' appropriately. */ 709 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 710 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 711 712 #ifdef AE_DEBUG 713 if (ifp->if_flags & IFF_DEBUG) { 714 printf(" txsoft %p transmit chain:\n", txs); 715 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 716 printf(" descriptor %d:\n", seg); 717 printf(" ad_status: 0x%08x\n", 718 sc->sc_txdescs[seg].ad_status); 719 printf(" ad_ctl: 0x%08x\n", 720 sc->sc_txdescs[seg].ad_ctl); 721 printf(" ad_bufaddr1: 0x%08x\n", 722 sc->sc_txdescs[seg].ad_bufaddr1); 723 printf(" ad_bufaddr2: 0x%08x\n", 724 sc->sc_txdescs[seg].ad_bufaddr2); 725 if (seg == lasttx) 726 break; 727 } 728 } 729 #endif 730 731 /* Sync the descriptors we're using. */ 732 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 733 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 734 735 /* 736 * Store a pointer to the packet so we can free it later, 737 * and remember what txdirty will be once the packet is 738 * done. 739 */ 740 txs->txs_mbuf = m0; 741 txs->txs_firstdesc = sc->sc_txnext; 742 txs->txs_lastdesc = lasttx; 743 txs->txs_ndescs = dmamap->dm_nsegs; 744 745 /* Advance the tx pointer. */ 746 sc->sc_txfree -= dmamap->dm_nsegs; 747 sc->sc_txnext = nexttx; 748 749 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 750 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 751 752 last_txs = txs; 753 754 #if NBPFILTER > 0 755 /* 756 * Pass the packet to any BPF listeners. 757 */ 758 if (ifp->if_bpf) 759 bpf_mtap(ifp->if_bpf, m0); 760 #endif /* NBPFILTER > 0 */ 761 } 762 763 if (txs == NULL || sc->sc_txfree == 0) { 764 /* No more slots left; notify upper layer. */ 765 ifp->if_flags |= IFF_OACTIVE; 766 } 767 768 if (sc->sc_txfree != ofree) { 769 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 770 sc->sc_dev.dv_xname, lasttx, firsttx)); 771 /* 772 * Cause a transmit interrupt to happen on the 773 * last packet we enqueued. 774 */ 775 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 776 AE_CDTXSYNC(sc, lasttx, 1, 777 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 778 779 /* 780 * The entire packet chain is set up. Give the 781 * first descriptor to the chip now. 782 */ 783 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 784 AE_CDTXSYNC(sc, firsttx, 1, 785 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 786 787 /* Wake up the transmitter. */ 788 /* XXX USE AUTOPOLLING? */ 789 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 790 AE_BARRIER(sc); 791 792 /* Set a watchdog timer in case the chip flakes out. */ 793 ifp->if_timer = 5; 794 } 795 } 796 797 /* 798 * ae_watchdog: [ifnet interface function] 799 * 800 * Watchdog timer handler. 801 */ 802 static void 803 ae_watchdog(struct ifnet *ifp) 804 { 805 struct ae_softc *sc = ifp->if_softc; 806 int doing_transmit; 807 808 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 809 810 if (doing_transmit) { 811 printf("%s: transmit timeout\n", sc->sc_dev.dv_xname); 812 ifp->if_oerrors++; 813 } 814 else 815 printf("%s: spurious watchdog timeout\n", sc->sc_dev.dv_xname); 816 817 (void) ae_init(ifp); 818 819 /* Try to get more packets going. */ 820 ae_start(ifp); 821 } 822 823 /* 824 * ae_ioctl: [ifnet interface function] 825 * 826 * Handle control requests from the operator. 827 */ 828 static int 829 ae_ioctl(struct ifnet *ifp, u_long cmd, void *data) 830 { 831 struct ae_softc *sc = ifp->if_softc; 832 int s, error; 833 834 s = splnet(); 835 836 switch (cmd) { 837 case SIOCSIFFLAGS: 838 /* If the interface is up and running, only modify the receive 839 * filter when setting promiscuous or debug mode. Otherwise 840 * fall through to ether_ioctl, which will reset the chip. 841 */ 842 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 843 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 844 == (IFF_UP|IFF_RUNNING)) 845 && ((ifp->if_flags & (~RESETIGN)) 846 == (sc->sc_if_flags & (~RESETIGN)))) { 847 /* Set up the receive filter. */ 848 ae_filter_setup(sc); 849 error = 0; 850 break; 851 #undef RESETIGN 852 } 853 /* FALLTHROUGH */ 854 default: 855 error = ether_ioctl(ifp, cmd, data); 856 if (error == ENETRESET) { 857 if (ifp->if_flags & IFF_RUNNING) { 858 /* 859 * Multicast list has changed. Set the 860 * hardware filter accordingly. 861 */ 862 ae_filter_setup(sc); 863 } 864 error = 0; 865 } 866 break; 867 } 868 869 /* Try to get more packets going. */ 870 if (AE_IS_ENABLED(sc)) 871 ae_start(ifp); 872 873 sc->sc_if_flags = ifp->if_flags; 874 splx(s); 875 return (error); 876 } 877 878 /* 879 * ae_intr: 880 * 881 * Interrupt service routine. 882 */ 883 int 884 ae_intr(void *arg) 885 { 886 struct ae_softc *sc = arg; 887 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 888 u_int32_t status, rxstatus, txstatus; 889 int handled = 0, txthresh; 890 891 DPRINTF(sc, ("%s: ae_intr\n", sc->sc_dev.dv_xname)); 892 893 #ifdef DEBUG 894 if (AE_IS_ENABLED(sc) == 0) 895 panic("%s: ae_intr: not enabled", sc->sc_dev.dv_xname); 896 #endif 897 898 /* 899 * If the interface isn't running, the interrupt couldn't 900 * possibly have come from us. 901 */ 902 if ((ifp->if_flags & IFF_RUNNING) == 0 || 903 !device_is_active(&sc->sc_dev)) { 904 printf("spurious?!?\n"); 905 return (0); 906 } 907 908 for (;;) { 909 status = AE_READ(sc, CSR_STATUS); 910 if (status) { 911 AE_WRITE(sc, CSR_STATUS, status); 912 AE_BARRIER(sc); 913 } 914 915 if ((status & sc->sc_inten) == 0) 916 break; 917 918 handled = 1; 919 920 rxstatus = status & sc->sc_rxint_mask; 921 txstatus = status & sc->sc_txint_mask; 922 923 if (rxstatus) { 924 /* Grab new any new packets. */ 925 ae_rxintr(sc); 926 927 if (rxstatus & STATUS_RU) { 928 printf("%s: receive ring overrun\n", 929 sc->sc_dev.dv_xname); 930 /* Get the receive process going again. */ 931 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 932 AE_BARRIER(sc); 933 break; 934 } 935 } 936 937 if (txstatus) { 938 /* Sweep up transmit descriptors. */ 939 ae_txintr(sc); 940 941 if (txstatus & STATUS_TJT) 942 printf("%s: transmit jabber timeout\n", 943 sc->sc_dev.dv_xname); 944 945 if (txstatus & STATUS_UNF) { 946 /* 947 * Increase our transmit threshold if 948 * another is available. 949 */ 950 txthresh = sc->sc_txthresh + 1; 951 if (ae_txthresh[txthresh].txth_name != NULL) { 952 uint32_t opmode; 953 /* Idle the transmit process. */ 954 opmode = AE_READ(sc, CSR_OPMODE); 955 ae_idle(sc, OPMODE_ST); 956 957 sc->sc_txthresh = txthresh; 958 opmode &= 959 ~(OPMODE_TR|OPMODE_SF); 960 opmode |= 961 ae_txthresh[txthresh].txth_opmode; 962 printf("%s: transmit underrun; new " 963 "threshold: %s\n", 964 sc->sc_dev.dv_xname, 965 ae_txthresh[txthresh].txth_name); 966 967 /* 968 * Set the new threshold and restart 969 * the transmit process. 970 */ 971 AE_WRITE(sc, CSR_OPMODE, opmode); 972 AE_BARRIER(sc); 973 } 974 /* 975 * XXX Log every Nth underrun from 976 * XXX now on? 977 */ 978 } 979 } 980 981 if (status & (STATUS_TPS|STATUS_RPS)) { 982 if (status & STATUS_TPS) 983 printf("%s: transmit process stopped\n", 984 sc->sc_dev.dv_xname); 985 if (status & STATUS_RPS) 986 printf("%s: receive process stopped\n", 987 sc->sc_dev.dv_xname); 988 (void) ae_init(ifp); 989 break; 990 } 991 992 if (status & STATUS_SE) { 993 const char *str; 994 995 if (status & STATUS_TX_ABORT) 996 str = "tx abort"; 997 else if (status & STATUS_RX_ABORT) 998 str = "rx abort"; 999 else 1000 str = "unknown error"; 1001 1002 printf("%s: fatal system error: %s\n", 1003 sc->sc_dev.dv_xname, str); 1004 (void) ae_init(ifp); 1005 break; 1006 } 1007 1008 /* 1009 * Not handled: 1010 * 1011 * Transmit buffer unavailable -- normal 1012 * condition, nothing to do, really. 1013 * 1014 * General purpose timer experied -- we don't 1015 * use the general purpose timer. 1016 * 1017 * Early receive interrupt -- not available on 1018 * all chips, we just use RI. We also only 1019 * use single-segment receive DMA, so this 1020 * is mostly useless. 1021 */ 1022 } 1023 1024 /* Try to get more packets going. */ 1025 ae_start(ifp); 1026 1027 #if NRND > 0 1028 if (handled) 1029 rnd_add_uint32(&sc->sc_rnd_source, status); 1030 #endif 1031 return (handled); 1032 } 1033 1034 /* 1035 * ae_rxintr: 1036 * 1037 * Helper; handle receive interrupts. 1038 */ 1039 static void 1040 ae_rxintr(struct ae_softc *sc) 1041 { 1042 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1043 struct ether_header *eh; 1044 struct ae_rxsoft *rxs; 1045 struct mbuf *m; 1046 u_int32_t rxstat; 1047 int i, len; 1048 1049 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1050 rxs = &sc->sc_rxsoft[i]; 1051 1052 AE_CDRXSYNC(sc, i, 1053 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1054 1055 rxstat = sc->sc_rxdescs[i].ad_status; 1056 1057 if (rxstat & ADSTAT_OWN) { 1058 /* 1059 * We have processed all of the receive buffers. 1060 */ 1061 break; 1062 } 1063 1064 /* 1065 * If any collisions were seen on the wire, count one. 1066 */ 1067 if (rxstat & ADSTAT_Rx_CS) 1068 ifp->if_collisions++; 1069 1070 /* 1071 * If an error occurred, update stats, clear the status 1072 * word, and leave the packet buffer in place. It will 1073 * simply be reused the next time the ring comes around. 1074 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1075 * error. 1076 */ 1077 if (rxstat & ADSTAT_ES && 1078 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1079 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1080 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1081 #define PRINTERR(bit, str) \ 1082 if (rxstat & (bit)) \ 1083 printf("%s: receive error: %s\n", \ 1084 sc->sc_dev.dv_xname, str) 1085 ifp->if_ierrors++; 1086 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1087 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1088 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1089 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1090 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1091 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1092 #undef PRINTERR 1093 AE_INIT_RXDESC(sc, i); 1094 continue; 1095 } 1096 1097 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1098 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1099 1100 /* 1101 * No errors; receive the packet. Note the chip 1102 * includes the CRC with every packet. 1103 */ 1104 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1105 1106 /* 1107 * XXX: the Atheros part can align on half words. what 1108 * is the performance implication of this? Probably 1109 * minimal, and we should use it... 1110 */ 1111 #ifdef __NO_STRICT_ALIGNMENT 1112 /* 1113 * Allocate a new mbuf cluster. If that fails, we are 1114 * out of memory, and must drop the packet and recycle 1115 * the buffer that's already attached to this descriptor. 1116 */ 1117 m = rxs->rxs_mbuf; 1118 if (ae_add_rxbuf(sc, i) != 0) { 1119 ifp->if_ierrors++; 1120 AE_INIT_RXDESC(sc, i); 1121 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1122 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1123 continue; 1124 } 1125 #else 1126 /* 1127 * The chip's receive buffers must be 4-byte aligned. 1128 * But this means that the data after the Ethernet header 1129 * is misaligned. We must allocate a new buffer and 1130 * copy the data, shifted forward 2 bytes. 1131 */ 1132 MGETHDR(m, M_DONTWAIT, MT_DATA); 1133 if (m == NULL) { 1134 dropit: 1135 ifp->if_ierrors++; 1136 AE_INIT_RXDESC(sc, i); 1137 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1138 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1139 continue; 1140 } 1141 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1142 if (len > (MHLEN - 2)) { 1143 MCLGET(m, M_DONTWAIT); 1144 if ((m->m_flags & M_EXT) == 0) { 1145 m_freem(m); 1146 goto dropit; 1147 } 1148 } 1149 m->m_data += 2; 1150 1151 /* 1152 * Note that we use clusters for incoming frames, so the 1153 * buffer is virtually contiguous. 1154 */ 1155 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 1156 1157 /* Allow the receive descriptor to continue using its mbuf. */ 1158 AE_INIT_RXDESC(sc, i); 1159 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1160 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1161 #endif /* __NO_STRICT_ALIGNMENT */ 1162 1163 ifp->if_ipackets++; 1164 eh = mtod(m, struct ether_header *); 1165 m->m_pkthdr.rcvif = ifp; 1166 m->m_pkthdr.len = m->m_len = len; 1167 1168 #if NBPFILTER > 0 1169 /* 1170 * Pass this up to any BPF listeners, but only 1171 * pass it up the stack if its for us. 1172 */ 1173 if (ifp->if_bpf) 1174 bpf_mtap(ifp->if_bpf, m); 1175 #endif /* NBPFILTER > 0 */ 1176 1177 /* Pass it on. */ 1178 (*ifp->if_input)(ifp, m); 1179 } 1180 1181 /* Update the receive pointer. */ 1182 sc->sc_rxptr = i; 1183 } 1184 1185 /* 1186 * ae_txintr: 1187 * 1188 * Helper; handle transmit interrupts. 1189 */ 1190 static void 1191 ae_txintr(struct ae_softc *sc) 1192 { 1193 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1194 struct ae_txsoft *txs; 1195 u_int32_t txstat; 1196 1197 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1198 sc->sc_dev.dv_xname, sc->sc_flags)); 1199 1200 ifp->if_flags &= ~IFF_OACTIVE; 1201 1202 /* 1203 * Go through our Tx list and free mbufs for those 1204 * frames that have been transmitted. 1205 */ 1206 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1207 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1208 txs->txs_ndescs, 1209 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1210 1211 #ifdef AE_DEBUG 1212 if (ifp->if_flags & IFF_DEBUG) { 1213 int i; 1214 printf(" txsoft %p transmit chain:\n", txs); 1215 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1216 printf(" descriptor %d:\n", i); 1217 printf(" ad_status: 0x%08x\n", 1218 sc->sc_txdescs[i].ad_status); 1219 printf(" ad_ctl: 0x%08x\n", 1220 sc->sc_txdescs[i].ad_ctl); 1221 printf(" ad_bufaddr1: 0x%08x\n", 1222 sc->sc_txdescs[i].ad_bufaddr1); 1223 printf(" ad_bufaddr2: 0x%08x\n", 1224 sc->sc_txdescs[i].ad_bufaddr2); 1225 if (i == txs->txs_lastdesc) 1226 break; 1227 } 1228 } 1229 #endif 1230 1231 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1232 if (txstat & ADSTAT_OWN) 1233 break; 1234 1235 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1236 1237 sc->sc_txfree += txs->txs_ndescs; 1238 1239 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1240 0, txs->txs_dmamap->dm_mapsize, 1241 BUS_DMASYNC_POSTWRITE); 1242 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1243 m_freem(txs->txs_mbuf); 1244 txs->txs_mbuf = NULL; 1245 1246 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1247 1248 /* 1249 * Check for errors and collisions. 1250 */ 1251 #ifdef AE_STATS 1252 if (txstat & ADSTAT_Tx_UF) 1253 sc->sc_stats.ts_tx_uf++; 1254 if (txstat & ADSTAT_Tx_TO) 1255 sc->sc_stats.ts_tx_to++; 1256 if (txstat & ADSTAT_Tx_EC) 1257 sc->sc_stats.ts_tx_ec++; 1258 if (txstat & ADSTAT_Tx_LC) 1259 sc->sc_stats.ts_tx_lc++; 1260 #endif 1261 1262 if (txstat & (ADSTAT_Tx_UF|ADSTAT_Tx_TO)) 1263 ifp->if_oerrors++; 1264 1265 if (txstat & ADSTAT_Tx_EC) 1266 ifp->if_collisions += 16; 1267 else 1268 ifp->if_collisions += ADSTAT_Tx_COLLISIONS(txstat); 1269 if (txstat & ADSTAT_Tx_LC) 1270 ifp->if_collisions++; 1271 1272 ifp->if_opackets++; 1273 } 1274 1275 /* 1276 * If there are no more pending transmissions, cancel the watchdog 1277 * timer. 1278 */ 1279 if (txs == NULL) 1280 ifp->if_timer = 0; 1281 } 1282 1283 #ifdef AE_STATS 1284 void 1285 ae_print_stats(struct ae_softc *sc) 1286 { 1287 1288 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1289 sc->sc_dev.dv_xname, 1290 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1291 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1292 } 1293 #endif 1294 1295 /* 1296 * ae_reset: 1297 * 1298 * Perform a soft reset on the chip. 1299 */ 1300 void 1301 ae_reset(struct ae_softc *sc) 1302 { 1303 int i; 1304 1305 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1306 AE_BARRIER(sc); 1307 1308 /* 1309 * The chip doesn't take itself out of reset automatically. 1310 * We need to do so after 2us. 1311 */ 1312 delay(10); 1313 AE_WRITE(sc, CSR_BUSMODE, 0); 1314 AE_BARRIER(sc); 1315 1316 for (i = 0; i < 1000; i++) { 1317 /* 1318 * Wait a bit for the reset to complete before peeking 1319 * at the chip again. 1320 */ 1321 delay(10); 1322 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1323 break; 1324 } 1325 1326 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1327 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1328 1329 delay(1000); 1330 } 1331 1332 /* 1333 * ae_init: [ ifnet interface function ] 1334 * 1335 * Initialize the interface. Must be called at splnet(). 1336 */ 1337 static int 1338 ae_init(struct ifnet *ifp) 1339 { 1340 struct ae_softc *sc = ifp->if_softc; 1341 struct ae_txsoft *txs; 1342 struct ae_rxsoft *rxs; 1343 const uint8_t *enaddr; 1344 int i, error = 0; 1345 1346 if ((error = ae_enable(sc)) != 0) 1347 goto out; 1348 1349 /* 1350 * Cancel any pending I/O. 1351 */ 1352 ae_stop(ifp, 0); 1353 1354 /* 1355 * Reset the chip to a known state. 1356 */ 1357 ae_reset(sc); 1358 1359 /* 1360 * Initialize the BUSMODE register. 1361 */ 1362 AE_WRITE(sc, CSR_BUSMODE, 1363 /* XXX: not sure if this is a good thing or not... */ 1364 //BUSMODE_ALIGN_16B | 1365 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1366 AE_BARRIER(sc); 1367 1368 /* 1369 * Initialize the transmit descriptor ring. 1370 */ 1371 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1372 for (i = 0; i < AE_NTXDESC; i++) { 1373 sc->sc_txdescs[i].ad_ctl = 0; 1374 sc->sc_txdescs[i].ad_bufaddr2 = 1375 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1376 } 1377 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1378 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1379 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1380 sc->sc_txfree = AE_NTXDESC; 1381 sc->sc_txnext = 0; 1382 1383 /* 1384 * Initialize the transmit job descriptors. 1385 */ 1386 SIMPLEQ_INIT(&sc->sc_txfreeq); 1387 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1388 for (i = 0; i < AE_TXQUEUELEN; i++) { 1389 txs = &sc->sc_txsoft[i]; 1390 txs->txs_mbuf = NULL; 1391 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1392 } 1393 1394 /* 1395 * Initialize the receive descriptor and receive job 1396 * descriptor rings. 1397 */ 1398 for (i = 0; i < AE_NRXDESC; i++) { 1399 rxs = &sc->sc_rxsoft[i]; 1400 if (rxs->rxs_mbuf == NULL) { 1401 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1402 printf("%s: unable to allocate or map rx " 1403 "buffer %d, error = %d\n", 1404 sc->sc_dev.dv_xname, i, error); 1405 /* 1406 * XXX Should attempt to run with fewer receive 1407 * XXX buffers instead of just failing. 1408 */ 1409 ae_rxdrain(sc); 1410 goto out; 1411 } 1412 } else 1413 AE_INIT_RXDESC(sc, i); 1414 } 1415 sc->sc_rxptr = 0; 1416 1417 /* 1418 * Initialize the interrupt mask and enable interrupts. 1419 */ 1420 /* normal interrupts */ 1421 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1422 1423 /* abnormal interrupts */ 1424 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1425 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1426 1427 sc->sc_rxint_mask = STATUS_RI|STATUS_RU; 1428 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT; 1429 1430 sc->sc_rxint_mask &= sc->sc_inten; 1431 sc->sc_txint_mask &= sc->sc_inten; 1432 1433 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1434 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1435 1436 /* 1437 * Give the transmit and receive rings to the chip. 1438 */ 1439 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1440 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1441 AE_BARRIER(sc); 1442 1443 /* 1444 * Set the station address. 1445 */ 1446 enaddr = CLLADDR(ifp->if_sadl); 1447 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1448 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1449 enaddr[1] << 8 | enaddr[0]); 1450 AE_BARRIER(sc); 1451 1452 /* 1453 * Set the receive filter. This will start the transmit and 1454 * receive processes. 1455 */ 1456 ae_filter_setup(sc); 1457 1458 /* 1459 * Set the current media. 1460 */ 1461 if ((error = ether_mediachange(ifp)) != 0) 1462 goto out; 1463 1464 /* 1465 * Start the mac. 1466 */ 1467 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1468 AE_BARRIER(sc); 1469 1470 /* 1471 * Write out the opmode. 1472 */ 1473 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1474 ae_txthresh[sc->sc_txthresh].txth_opmode); 1475 /* 1476 * Start the receive process. 1477 */ 1478 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1479 AE_BARRIER(sc); 1480 1481 if (sc->sc_tick != NULL) { 1482 /* Start the one second clock. */ 1483 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1484 } 1485 1486 /* 1487 * Note that the interface is now running. 1488 */ 1489 ifp->if_flags |= IFF_RUNNING; 1490 ifp->if_flags &= ~IFF_OACTIVE; 1491 sc->sc_if_flags = ifp->if_flags; 1492 1493 out: 1494 if (error) { 1495 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1496 ifp->if_timer = 0; 1497 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1498 } 1499 return (error); 1500 } 1501 1502 /* 1503 * ae_enable: 1504 * 1505 * Enable the chip. 1506 */ 1507 static int 1508 ae_enable(struct ae_softc *sc) 1509 { 1510 1511 if (AE_IS_ENABLED(sc) == 0) { 1512 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1513 ae_intr, sc); 1514 if (sc->sc_ih == NULL) { 1515 printf("%s: unable to establish interrupt\n", 1516 sc->sc_dev.dv_xname); 1517 return (EIO); 1518 } 1519 sc->sc_flags |= AE_ENABLED; 1520 } 1521 return (0); 1522 } 1523 1524 /* 1525 * ae_disable: 1526 * 1527 * Disable the chip. 1528 */ 1529 static void 1530 ae_disable(struct ae_softc *sc) 1531 { 1532 1533 if (AE_IS_ENABLED(sc)) { 1534 arbus_intr_disestablish(sc->sc_ih); 1535 sc->sc_flags &= ~AE_ENABLED; 1536 } 1537 } 1538 1539 /* 1540 * ae_power: 1541 * 1542 * Power management (suspend/resume) hook. 1543 */ 1544 static void 1545 ae_power(int why, void *arg) 1546 { 1547 struct ae_softc *sc = arg; 1548 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1549 int s; 1550 1551 printf("power called: %d, %x\n", why, (uint32_t)arg); 1552 s = splnet(); 1553 switch (why) { 1554 case PWR_STANDBY: 1555 /* do nothing! */ 1556 break; 1557 case PWR_SUSPEND: 1558 ae_stop(ifp, 0); 1559 ae_disable(sc); 1560 break; 1561 case PWR_RESUME: 1562 if (ifp->if_flags & IFF_UP) { 1563 ae_enable(sc); 1564 ae_init(ifp); 1565 } 1566 break; 1567 case PWR_SOFTSUSPEND: 1568 case PWR_SOFTSTANDBY: 1569 case PWR_SOFTRESUME: 1570 break; 1571 } 1572 splx(s); 1573 } 1574 1575 /* 1576 * ae_rxdrain: 1577 * 1578 * Drain the receive queue. 1579 */ 1580 static void 1581 ae_rxdrain(struct ae_softc *sc) 1582 { 1583 struct ae_rxsoft *rxs; 1584 int i; 1585 1586 for (i = 0; i < AE_NRXDESC; i++) { 1587 rxs = &sc->sc_rxsoft[i]; 1588 if (rxs->rxs_mbuf != NULL) { 1589 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1590 m_freem(rxs->rxs_mbuf); 1591 rxs->rxs_mbuf = NULL; 1592 } 1593 } 1594 } 1595 1596 /* 1597 * ae_stop: [ ifnet interface function ] 1598 * 1599 * Stop transmission on the interface. 1600 */ 1601 static void 1602 ae_stop(struct ifnet *ifp, int disable) 1603 { 1604 struct ae_softc *sc = ifp->if_softc; 1605 struct ae_txsoft *txs; 1606 1607 if (sc->sc_tick != NULL) { 1608 /* Stop the one second clock. */ 1609 callout_stop(&sc->sc_tick_callout); 1610 } 1611 1612 /* Down the MII. */ 1613 mii_down(&sc->sc_mii); 1614 1615 /* Disable interrupts. */ 1616 AE_WRITE(sc, CSR_INTEN, 0); 1617 1618 /* Stop the transmit and receive processes. */ 1619 AE_WRITE(sc, CSR_OPMODE, 0); 1620 AE_WRITE(sc, CSR_RXLIST, 0); 1621 AE_WRITE(sc, CSR_TXLIST, 0); 1622 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1623 AE_BARRIER(sc); 1624 1625 /* 1626 * Release any queued transmit buffers. 1627 */ 1628 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1629 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1630 if (txs->txs_mbuf != NULL) { 1631 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1632 m_freem(txs->txs_mbuf); 1633 txs->txs_mbuf = NULL; 1634 } 1635 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1636 } 1637 1638 /* 1639 * Mark the interface down and cancel the watchdog timer. 1640 */ 1641 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1642 sc->sc_if_flags = ifp->if_flags; 1643 ifp->if_timer = 0; 1644 1645 if (disable) { 1646 ae_rxdrain(sc); 1647 ae_disable(sc); 1648 } 1649 1650 /* 1651 * Reset the chip (needed on some flavors to actually disable it). 1652 */ 1653 ae_reset(sc); 1654 } 1655 1656 /* 1657 * ae_add_rxbuf: 1658 * 1659 * Add a receive buffer to the indicated descriptor. 1660 */ 1661 static int 1662 ae_add_rxbuf(struct ae_softc *sc, int idx) 1663 { 1664 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1665 struct mbuf *m; 1666 int error; 1667 1668 MGETHDR(m, M_DONTWAIT, MT_DATA); 1669 if (m == NULL) 1670 return (ENOBUFS); 1671 1672 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1673 MCLGET(m, M_DONTWAIT); 1674 if ((m->m_flags & M_EXT) == 0) { 1675 m_freem(m); 1676 return (ENOBUFS); 1677 } 1678 1679 if (rxs->rxs_mbuf != NULL) 1680 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1681 1682 rxs->rxs_mbuf = m; 1683 1684 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1685 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1686 BUS_DMA_READ|BUS_DMA_NOWAIT); 1687 if (error) { 1688 printf("%s: can't load rx DMA map %d, error = %d\n", 1689 sc->sc_dev.dv_xname, idx, error); 1690 panic("ae_add_rxbuf"); /* XXX */ 1691 } 1692 1693 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1694 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1695 1696 AE_INIT_RXDESC(sc, idx); 1697 1698 return (0); 1699 } 1700 1701 /* 1702 * ae_filter_setup: 1703 * 1704 * Set the chip's receive filter. 1705 */ 1706 static void 1707 ae_filter_setup(struct ae_softc *sc) 1708 { 1709 struct ethercom *ec = &sc->sc_ethercom; 1710 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1711 struct ether_multi *enm; 1712 struct ether_multistep step; 1713 uint32_t hash, mchash[2]; 1714 uint32_t macctl = 0; 1715 1716 /* 1717 * If the chip is running, we need to reset the interface, 1718 * and will revisit here (with IFF_RUNNING) clear. The 1719 * chip seems to really not like to have its multicast 1720 * filter programmed without a reset. 1721 */ 1722 if (ifp->if_flags & IFF_RUNNING) { 1723 (void) ae_init(ifp); 1724 return; 1725 } 1726 1727 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1728 sc->sc_dev.dv_xname, sc->sc_flags)); 1729 1730 macctl = AE_READ(sc, CSR_MACCTL); 1731 macctl &= ~(MACCTL_PR | MACCTL_PM); 1732 macctl |= MACCTL_HASH; 1733 macctl |= MACCTL_HBD; 1734 macctl |= MACCTL_PR; 1735 1736 if (ifp->if_flags & IFF_PROMISC) { 1737 macctl |= MACCTL_PR; 1738 goto allmulti; 1739 } 1740 1741 mchash[0] = mchash[1] = 0; 1742 1743 ETHER_FIRST_MULTI(step, ec, enm); 1744 while (enm != NULL) { 1745 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1746 /* 1747 * We must listen to a range of multicast addresses. 1748 * For now, just accept all multicasts, rather than 1749 * trying to set only those filter bits needed to match 1750 * the range. (At this time, the only use of address 1751 * ranges is for IP multicast routing, for which the 1752 * range is big enough to require all bits set.) 1753 */ 1754 goto allmulti; 1755 } 1756 1757 /* Verify whether we use big or little endian hashes */ 1758 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1759 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1760 ETHER_NEXT_MULTI(step, enm); 1761 } 1762 ifp->if_flags &= ~IFF_ALLMULTI; 1763 goto setit; 1764 1765 allmulti: 1766 ifp->if_flags |= IFF_ALLMULTI; 1767 mchash[0] = mchash[1] = 0xffffffff; 1768 macctl |= MACCTL_PM; 1769 1770 setit: 1771 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1772 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1773 1774 AE_WRITE(sc, CSR_MACCTL, macctl); 1775 AE_BARRIER(sc); 1776 1777 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1778 sc->sc_dev.dv_xname, macctl)); 1779 } 1780 1781 /* 1782 * ae_idle: 1783 * 1784 * Cause the transmit and/or receive processes to go idle. 1785 */ 1786 void 1787 ae_idle(struct ae_softc *sc, u_int32_t bits) 1788 { 1789 static const char * const txstate_names[] = { 1790 "STOPPED", 1791 "RUNNING - FETCH", 1792 "RUNNING - WAIT", 1793 "RUNNING - READING", 1794 "-- RESERVED --", 1795 "RUNNING - SETUP", 1796 "SUSPENDED", 1797 "RUNNING - CLOSE", 1798 }; 1799 static const char * const rxstate_names[] = { 1800 "STOPPED", 1801 "RUNNING - FETCH", 1802 "RUNNING - CHECK", 1803 "RUNNING - WAIT", 1804 "SUSPENDED", 1805 "RUNNING - CLOSE", 1806 "RUNNING - FLUSH", 1807 "RUNNING - QUEUE", 1808 }; 1809 1810 u_int32_t csr, ackmask = 0; 1811 int i; 1812 1813 if (bits & OPMODE_ST) 1814 ackmask |= STATUS_TPS; 1815 1816 if (bits & OPMODE_SR) 1817 ackmask |= STATUS_RPS; 1818 1819 AE_CLR(sc, CSR_OPMODE, bits); 1820 1821 for (i = 0; i < 1000; i++) { 1822 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1823 break; 1824 delay(10); 1825 } 1826 1827 csr = AE_READ(sc, CSR_STATUS); 1828 if ((csr & ackmask) != ackmask) { 1829 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1830 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1831 printf("%s: transmit process failed to idle: " 1832 "state %s\n", sc->sc_dev.dv_xname, 1833 txstate_names[(csr & STATUS_TS) >> 20]); 1834 } 1835 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1836 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1837 printf("%s: receive process failed to idle: " 1838 "state %s\n", sc->sc_dev.dv_xname, 1839 rxstate_names[(csr & STATUS_RS) >> 17]); 1840 } 1841 } 1842 } 1843 1844 /***************************************************************************** 1845 * Support functions for MII-attached media. 1846 *****************************************************************************/ 1847 1848 /* 1849 * ae_mii_tick: 1850 * 1851 * One second timer, used to tick the MII. 1852 */ 1853 static void 1854 ae_mii_tick(void *arg) 1855 { 1856 struct ae_softc *sc = arg; 1857 int s; 1858 1859 if (!device_is_active(&sc->sc_dev)) 1860 return; 1861 1862 s = splnet(); 1863 mii_tick(&sc->sc_mii); 1864 splx(s); 1865 1866 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1867 } 1868 1869 /* 1870 * ae_mii_statchg: [mii interface function] 1871 * 1872 * Callback from PHY when media changes. 1873 */ 1874 static void 1875 ae_mii_statchg(device_t self) 1876 { 1877 struct ae_softc *sc = device_private(self); 1878 uint32_t macctl, flowc; 1879 1880 //opmode = AE_READ(sc, CSR_OPMODE); 1881 macctl = AE_READ(sc, CSR_MACCTL); 1882 1883 /* XXX: do we need to do this? */ 1884 /* Idle the transmit and receive processes. */ 1885 //ae_idle(sc, OPMODE_ST|OPMODE_SR); 1886 1887 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1888 flowc = FLOWC_FCE; 1889 macctl &= ~MACCTL_DRO; 1890 macctl |= MACCTL_FDX; 1891 } else { 1892 flowc = 0; /* cannot do flow control in HDX */ 1893 macctl |= MACCTL_DRO; 1894 macctl &= ~MACCTL_FDX; 1895 } 1896 1897 AE_WRITE(sc, CSR_FLOWC, flowc); 1898 AE_WRITE(sc, CSR_MACCTL, macctl); 1899 1900 /* restore operational mode */ 1901 //AE_WRITE(sc, CSR_OPMODE, opmode); 1902 AE_BARRIER(sc); 1903 } 1904 1905 /* 1906 * ae_mii_readreg: 1907 * 1908 * Read a PHY register. 1909 */ 1910 static int 1911 ae_mii_readreg(device_t self, int phy, int reg) 1912 { 1913 struct ae_softc *sc = device_private(self); 1914 uint32_t addr; 1915 int i; 1916 1917 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1918 AE_WRITE(sc, CSR_MIIADDR, addr); 1919 AE_BARRIER(sc); 1920 for (i = 0; i < 100000000; i++) { 1921 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1922 break; 1923 } 1924 1925 return (AE_READ(sc, CSR_MIIDATA) & 0xffff); 1926 } 1927 1928 /* 1929 * ae_mii_writereg: 1930 * 1931 * Write a PHY register. 1932 */ 1933 static void 1934 ae_mii_writereg(device_t self, int phy, int reg, int val) 1935 { 1936 struct ae_softc *sc = device_private(self); 1937 uint32_t addr; 1938 int i; 1939 1940 /* write the data register */ 1941 AE_WRITE(sc, CSR_MIIDATA, val); 1942 1943 /* write the address to latch it in */ 1944 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1945 MIIADDR_WRITE; 1946 AE_WRITE(sc, CSR_MIIADDR, addr); 1947 AE_BARRIER(sc); 1948 1949 for (i = 0; i < 100000000; i++) { 1950 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1951 break; 1952 } 1953 } 1954
Indexes created Wed Sep 24 15:09:51 GMT 2025