if_ae.c revision 1.13.4.2
1 /* $Id: if_ae.c,v 1.13.4.2 2009/05/04 08:11:31 yamt Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the onboard ethernet MAC found on the AR5312 74 * chip's AHB bus. 75 * 76 * This device is very simliar to the tulip in most regards, and 77 * the code is directly derived from NetBSD's tulip.c. However, it 78 * is different enough that it did not seem to be a good idea to 79 * add further complexity to the tulip driver, so we have our own. 80 * 81 * Also tulip has a lot of complexity in it for various parts/options 82 * that we don't need, and on these little boxes with only ~8MB RAM, we 83 * don't want any extra bloat. 84 */ 85 86 /* 87 * TODO: 88 * 89 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 90 * inbound packets on a half-word boundary, which would make life easier 91 * for TCP/IP. (Aligning IP headers on a word.) 92 * 93 * 2) There is stuff in original tulip to shut down the device when reacting 94 * to a a change in link status. Is that needed. 95 * 96 * 3) Test with variety of 10/100 HDX/FDX scenarios. 97 * 98 */ 99 100 #include <sys/cdefs.h> 101 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.13.4.2 2009/05/04 08:11:31 yamt Exp $"); 102 103 #include "bpfilter.h" 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/callout.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/ioctl.h> 113 #include <sys/errno.h> 114 #include <sys/device.h> 115 116 #include <machine/endian.h> 117 118 #include <uvm/uvm_extern.h> 119 120 #include <net/if.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_ether.h> 124 125 #if NBPFILTER > 0 126 #include <net/bpf.h> 127 #endif 128 129 #include <machine/bus.h> 130 #include <machine/intr.h> 131 132 #include <dev/mii/mii.h> 133 #include <dev/mii/miivar.h> 134 #include <dev/mii/mii_bitbang.h> 135 136 #include <mips/atheros/include/arbusvar.h> 137 #include <mips/atheros/dev/aereg.h> 138 #include <mips/atheros/dev/aevar.h> 139 140 static const struct { 141 u_int32_t txth_opmode; /* OPMODE bits */ 142 const char *txth_name; /* name of mode */ 143 } ae_txthresh[] = { 144 { OPMODE_TR_32, "32 words" }, 145 { OPMODE_TR_64, "64 words" }, 146 { OPMODE_TR_128, "128 words" }, 147 { OPMODE_TR_256, "256 words" }, 148 { OPMODE_SF, "store and forward mode" }, 149 { 0, NULL }, 150 }; 151 152 static int ae_match(device_t, struct cfdata *, void *); 153 static void ae_attach(device_t, device_t, void *); 154 static int ae_detach(device_t, int); 155 static int ae_activate(device_t, enum devact); 156 157 static int ae_ifflags_cb(struct ethercom *); 158 static void ae_reset(struct ae_softc *); 159 static void ae_idle(struct ae_softc *, u_int32_t); 160 161 static void ae_start(struct ifnet *); 162 static void ae_watchdog(struct ifnet *); 163 static int ae_ioctl(struct ifnet *, u_long, void *); 164 static int ae_init(struct ifnet *); 165 static void ae_stop(struct ifnet *, int); 166 167 static void ae_shutdown(void *); 168 169 static void ae_rxdrain(struct ae_softc *); 170 static int ae_add_rxbuf(struct ae_softc *, int); 171 172 static int ae_enable(struct ae_softc *); 173 static void ae_disable(struct ae_softc *); 174 static void ae_power(int, void *); 175 176 static void ae_filter_setup(struct ae_softc *); 177 178 static int ae_intr(void *); 179 static void ae_rxintr(struct ae_softc *); 180 static void ae_txintr(struct ae_softc *); 181 182 static void ae_mii_tick(void *); 183 static void ae_mii_statchg(device_t); 184 185 static int ae_mii_readreg(device_t, int, int); 186 static void ae_mii_writereg(device_t, int, int, int); 187 188 #ifdef AE_DEBUG 189 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 190 printf x 191 #else 192 #define DPRINTF(sc, x) /* nothing */ 193 #endif 194 195 #ifdef AE_STATS 196 static void ae_print_stats(struct ae_softc *); 197 #endif 198 199 CFATTACH_DECL(ae, sizeof(struct ae_softc), 200 ae_match, ae_attach, ae_detach, ae_activate); 201 202 /* 203 * ae_match: 204 * 205 * Check for a device match. 206 */ 207 int 208 ae_match(device_t parent, struct cfdata *cf, void *aux) 209 { 210 struct arbus_attach_args *aa = aux; 211 212 if (strcmp(aa->aa_name, cf->cf_name) == 0) 213 return 1; 214 215 return 0; 216 217 } 218 219 /* 220 * ae_attach: 221 * 222 * Attach an ae interface to the system. 223 */ 224 void 225 ae_attach(device_t parent, device_t self, void *aux) 226 { 227 const uint8_t *enaddr; 228 prop_data_t ea; 229 struct ae_softc *sc = device_private(self); 230 struct arbus_attach_args *aa = aux; 231 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 232 int i, error; 233 234 callout_init(&sc->sc_tick_callout, 0); 235 236 printf(": Atheros AR531X 10/100 Ethernet\n"); 237 238 /* 239 * Try to get MAC address. 240 */ 241 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 242 if (ea == NULL) { 243 printf("%s: unable to get mac-addr property\n", 244 sc->sc_dev.dv_xname); 245 return; 246 } 247 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 248 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 249 enaddr = prop_data_data_nocopy(ea); 250 251 /* Announce ourselves. */ 252 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 253 ether_sprintf(enaddr)); 254 255 sc->sc_cirq = aa->aa_cirq; 256 sc->sc_mirq = aa->aa_mirq; 257 sc->sc_st = aa->aa_bst; 258 sc->sc_dmat = aa->aa_dmat; 259 260 SIMPLEQ_INIT(&sc->sc_txfreeq); 261 SIMPLEQ_INIT(&sc->sc_txdirtyq); 262 263 /* 264 * Map registers. 265 */ 266 sc->sc_size = aa->aa_size; 267 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 268 &sc->sc_sh)) != 0) { 269 printf("%s: unable to map registers, error = %d\n", 270 sc->sc_dev.dv_xname, error); 271 goto fail_0; 272 } 273 274 /* 275 * Allocate the control data structures, and create and load the 276 * DMA map for it. 277 */ 278 if ((error = bus_dmamem_alloc(sc->sc_dmat, 279 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 280 1, &sc->sc_cdnseg, 0)) != 0) { 281 printf("%s: unable to allocate control data, error = %d\n", 282 sc->sc_dev.dv_xname, error); 283 goto fail_1; 284 } 285 286 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 287 sizeof(struct ae_control_data), (void **)&sc->sc_control_data, 288 BUS_DMA_COHERENT)) != 0) { 289 printf("%s: unable to map control data, error = %d\n", 290 sc->sc_dev.dv_xname, error); 291 goto fail_2; 292 } 293 294 if ((error = bus_dmamap_create(sc->sc_dmat, 295 sizeof(struct ae_control_data), 1, 296 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 297 printf("%s: unable to create control data DMA map, " 298 "error = %d\n", sc->sc_dev.dv_xname, error); 299 goto fail_3; 300 } 301 302 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 303 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 304 0)) != 0) { 305 printf("%s: unable to load control data DMA map, error = %d\n", 306 sc->sc_dev.dv_xname, error); 307 goto fail_4; 308 } 309 310 /* 311 * Create the transmit buffer DMA maps. 312 */ 313 for (i = 0; i < AE_TXQUEUELEN; i++) { 314 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 315 AE_NTXSEGS, MCLBYTES, 0, 0, 316 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 317 printf("%s: unable to create tx DMA map %d, " 318 "error = %d\n", sc->sc_dev.dv_xname, i, error); 319 goto fail_5; 320 } 321 } 322 323 /* 324 * Create the receive buffer DMA maps. 325 */ 326 for (i = 0; i < AE_NRXDESC; i++) { 327 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 328 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 329 printf("%s: unable to create rx DMA map %d, " 330 "error = %d\n", sc->sc_dev.dv_xname, i, error); 331 goto fail_6; 332 } 333 sc->sc_rxsoft[i].rxs_mbuf = NULL; 334 } 335 336 /* 337 * Reset the chip to a known state. 338 */ 339 ae_reset(sc); 340 341 /* 342 * From this point forward, the attachment cannot fail. A failure 343 * before this point releases all resources that may have been 344 * allocated. 345 */ 346 sc->sc_flags |= AE_ATTACHED; 347 348 /* 349 * Initialize our media structures. This may probe the MII, if 350 * present. 351 */ 352 sc->sc_mii.mii_ifp = ifp; 353 sc->sc_mii.mii_readreg = ae_mii_readreg; 354 sc->sc_mii.mii_writereg = ae_mii_writereg; 355 sc->sc_mii.mii_statchg = ae_mii_statchg; 356 sc->sc_ethercom.ec_mii = &sc->sc_mii; 357 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 358 ether_mediastatus); 359 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 360 MII_OFFSET_ANY, 0); 361 362 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 363 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 364 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 365 } else 366 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 367 368 sc->sc_tick = ae_mii_tick; 369 370 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 371 ifp->if_softc = sc; 372 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 373 sc->sc_if_flags = ifp->if_flags; 374 ifp->if_ioctl = ae_ioctl; 375 ifp->if_start = ae_start; 376 ifp->if_watchdog = ae_watchdog; 377 ifp->if_init = ae_init; 378 ifp->if_stop = ae_stop; 379 IFQ_SET_READY(&ifp->if_snd); 380 381 /* 382 * We can support 802.1Q VLAN-sized frames. 383 */ 384 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 385 386 /* 387 * Attach the interface. 388 */ 389 if_attach(ifp); 390 ether_ifattach(ifp, enaddr); 391 ether_set_ifflags_cb(&sc->sc_ethercom, ae_ifflags_cb); 392 393 #if NRND > 0 394 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 395 RND_TYPE_NET, 0); 396 #endif 397 398 /* 399 * Make sure the interface is shutdown during reboot. 400 */ 401 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 402 if (sc->sc_sdhook == NULL) 403 printf("%s: WARNING: unable to establish shutdown hook\n", 404 sc->sc_dev.dv_xname); 405 406 /* 407 * Add a suspend hook to make sure we come back up after a 408 * resume. 409 */ 410 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 411 ae_power, sc); 412 if (sc->sc_powerhook == NULL) 413 printf("%s: WARNING: unable to establish power hook\n", 414 sc->sc_dev.dv_xname); 415 return; 416 417 /* 418 * Free any resources we've allocated during the failed attach 419 * attempt. Do this in reverse order and fall through. 420 */ 421 fail_6: 422 for (i = 0; i < AE_NRXDESC; i++) { 423 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 424 bus_dmamap_destroy(sc->sc_dmat, 425 sc->sc_rxsoft[i].rxs_dmamap); 426 } 427 fail_5: 428 for (i = 0; i < AE_TXQUEUELEN; i++) { 429 if (sc->sc_txsoft[i].txs_dmamap != NULL) 430 bus_dmamap_destroy(sc->sc_dmat, 431 sc->sc_txsoft[i].txs_dmamap); 432 } 433 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 434 fail_4: 435 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 436 fail_3: 437 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 438 sizeof(struct ae_control_data)); 439 fail_2: 440 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 441 fail_1: 442 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 443 fail_0: 444 return; 445 } 446 447 /* 448 * ae_activate: 449 * 450 * Handle device activation/deactivation requests. 451 */ 452 int 453 ae_activate(device_t self, enum devact act) 454 { 455 struct ae_softc *sc = device_private(self); 456 int s, error = 0; 457 458 s = splnet(); 459 switch (act) { 460 case DVACT_ACTIVATE: 461 error = EOPNOTSUPP; 462 break; 463 464 case DVACT_DEACTIVATE: 465 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 466 if_deactivate(&sc->sc_ethercom.ec_if); 467 break; 468 } 469 splx(s); 470 471 return (error); 472 } 473 474 /* 475 * ae_detach: 476 * 477 * Detach a device interface. 478 */ 479 int 480 ae_detach(device_t self, int flags) 481 { 482 struct ae_softc *sc = device_private(self); 483 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 484 struct ae_rxsoft *rxs; 485 struct ae_txsoft *txs; 486 int i; 487 488 /* 489 * Succeed now if there isn't any work to do. 490 */ 491 if ((sc->sc_flags & AE_ATTACHED) == 0) 492 return (0); 493 494 /* Unhook our tick handler. */ 495 if (sc->sc_tick) 496 callout_stop(&sc->sc_tick_callout); 497 498 /* Detach all PHYs */ 499 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 500 501 /* Delete all remaining media. */ 502 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 503 504 #if NRND > 0 505 rnd_detach_source(&sc->sc_rnd_source); 506 #endif 507 ether_ifdetach(ifp); 508 if_detach(ifp); 509 510 for (i = 0; i < AE_NRXDESC; i++) { 511 rxs = &sc->sc_rxsoft[i]; 512 if (rxs->rxs_mbuf != NULL) { 513 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 514 m_freem(rxs->rxs_mbuf); 515 rxs->rxs_mbuf = NULL; 516 } 517 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 518 } 519 for (i = 0; i < AE_TXQUEUELEN; i++) { 520 txs = &sc->sc_txsoft[i]; 521 if (txs->txs_mbuf != NULL) { 522 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 523 m_freem(txs->txs_mbuf); 524 txs->txs_mbuf = NULL; 525 } 526 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 527 } 528 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 529 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 530 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 531 sizeof(struct ae_control_data)); 532 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 533 534 shutdownhook_disestablish(sc->sc_sdhook); 535 powerhook_disestablish(sc->sc_powerhook); 536 537 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 538 539 540 return (0); 541 } 542 543 /* 544 * ae_shutdown: 545 * 546 * Make sure the interface is stopped at reboot time. 547 */ 548 static void 549 ae_shutdown(void *arg) 550 { 551 struct ae_softc *sc = arg; 552 553 ae_stop(&sc->sc_ethercom.ec_if, 1); 554 } 555 556 /* 557 * ae_start: [ifnet interface function] 558 * 559 * Start packet transmission on the interface. 560 */ 561 static void 562 ae_start(struct ifnet *ifp) 563 { 564 struct ae_softc *sc = ifp->if_softc; 565 struct mbuf *m0, *m; 566 struct ae_txsoft *txs, *last_txs = NULL; 567 bus_dmamap_t dmamap; 568 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 569 570 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 571 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 572 573 574 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 575 return; 576 577 /* 578 * Remember the previous number of free descriptors and 579 * the first descriptor we'll use. 580 */ 581 ofree = sc->sc_txfree; 582 firsttx = sc->sc_txnext; 583 584 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 585 sc->sc_dev.dv_xname, ofree, firsttx)); 586 587 /* 588 * Loop through the send queue, setting up transmit descriptors 589 * until we drain the queue, or use up all available transmit 590 * descriptors. 591 */ 592 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 593 sc->sc_txfree != 0) { 594 /* 595 * Grab a packet off the queue. 596 */ 597 IFQ_POLL(&ifp->if_snd, m0); 598 if (m0 == NULL) 599 break; 600 m = NULL; 601 602 dmamap = txs->txs_dmamap; 603 604 /* 605 * Load the DMA map. If this fails, the packet either 606 * didn't fit in the alloted number of segments, or we were 607 * short on resources. In this case, we'll copy and try 608 * again. 609 */ 610 if (((mtod(m0, uintptr_t) & 3) != 0) || 611 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 612 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 613 MGETHDR(m, M_DONTWAIT, MT_DATA); 614 if (m == NULL) { 615 printf("%s: unable to allocate Tx mbuf\n", 616 sc->sc_dev.dv_xname); 617 break; 618 } 619 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 620 if (m0->m_pkthdr.len > MHLEN) { 621 MCLGET(m, M_DONTWAIT); 622 if ((m->m_flags & M_EXT) == 0) { 623 printf("%s: unable to allocate Tx " 624 "cluster\n", sc->sc_dev.dv_xname); 625 m_freem(m); 626 break; 627 } 628 } 629 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 630 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 631 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 632 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 633 if (error) { 634 printf("%s: unable to load Tx buffer, " 635 "error = %d\n", sc->sc_dev.dv_xname, 636 error); 637 break; 638 } 639 } 640 641 /* 642 * Ensure we have enough descriptors free to describe 643 * the packet. 644 */ 645 if (dmamap->dm_nsegs > sc->sc_txfree) { 646 /* 647 * Not enough free descriptors to transmit this 648 * packet. We haven't committed to anything yet, 649 * so just unload the DMA map, put the packet 650 * back on the queue, and punt. Notify the upper 651 * layer that there are no more slots left. 652 * 653 * XXX We could allocate an mbuf and copy, but 654 * XXX it is worth it? 655 */ 656 ifp->if_flags |= IFF_OACTIVE; 657 bus_dmamap_unload(sc->sc_dmat, dmamap); 658 if (m != NULL) 659 m_freem(m); 660 break; 661 } 662 663 IFQ_DEQUEUE(&ifp->if_snd, m0); 664 if (m != NULL) { 665 m_freem(m0); 666 m0 = m; 667 } 668 669 /* 670 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 671 */ 672 673 /* Sync the DMA map. */ 674 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 675 BUS_DMASYNC_PREWRITE); 676 677 /* 678 * Initialize the transmit descriptors. 679 */ 680 for (nexttx = sc->sc_txnext, seg = 0; 681 seg < dmamap->dm_nsegs; 682 seg++, nexttx = AE_NEXTTX(nexttx)) { 683 /* 684 * If this is the first descriptor we're 685 * enqueueing, don't set the OWN bit just 686 * yet. That could cause a race condition. 687 * We'll do it below. 688 */ 689 sc->sc_txdescs[nexttx].ad_status = 690 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 691 sc->sc_txdescs[nexttx].ad_bufaddr1 = 692 dmamap->dm_segs[seg].ds_addr; 693 sc->sc_txdescs[nexttx].ad_ctl = 694 (dmamap->dm_segs[seg].ds_len << 695 ADCTL_SIZE1_SHIFT) | 696 (nexttx == (AE_NTXDESC - 1) ? 697 ADCTL_ER : 0); 698 lasttx = nexttx; 699 } 700 701 KASSERT(lasttx != -1); 702 703 /* Set `first segment' and `last segment' appropriately. */ 704 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 705 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 706 707 #ifdef AE_DEBUG 708 if (ifp->if_flags & IFF_DEBUG) { 709 printf(" txsoft %p transmit chain:\n", txs); 710 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 711 printf(" descriptor %d:\n", seg); 712 printf(" ad_status: 0x%08x\n", 713 sc->sc_txdescs[seg].ad_status); 714 printf(" ad_ctl: 0x%08x\n", 715 sc->sc_txdescs[seg].ad_ctl); 716 printf(" ad_bufaddr1: 0x%08x\n", 717 sc->sc_txdescs[seg].ad_bufaddr1); 718 printf(" ad_bufaddr2: 0x%08x\n", 719 sc->sc_txdescs[seg].ad_bufaddr2); 720 if (seg == lasttx) 721 break; 722 } 723 } 724 #endif 725 726 /* Sync the descriptors we're using. */ 727 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 728 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 729 730 /* 731 * Store a pointer to the packet so we can free it later, 732 * and remember what txdirty will be once the packet is 733 * done. 734 */ 735 txs->txs_mbuf = m0; 736 txs->txs_firstdesc = sc->sc_txnext; 737 txs->txs_lastdesc = lasttx; 738 txs->txs_ndescs = dmamap->dm_nsegs; 739 740 /* Advance the tx pointer. */ 741 sc->sc_txfree -= dmamap->dm_nsegs; 742 sc->sc_txnext = nexttx; 743 744 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 745 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 746 747 last_txs = txs; 748 749 #if NBPFILTER > 0 750 /* 751 * Pass the packet to any BPF listeners. 752 */ 753 if (ifp->if_bpf) 754 bpf_mtap(ifp->if_bpf, m0); 755 #endif /* NBPFILTER > 0 */ 756 } 757 758 if (txs == NULL || sc->sc_txfree == 0) { 759 /* No more slots left; notify upper layer. */ 760 ifp->if_flags |= IFF_OACTIVE; 761 } 762 763 if (sc->sc_txfree != ofree) { 764 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 765 sc->sc_dev.dv_xname, lasttx, firsttx)); 766 /* 767 * Cause a transmit interrupt to happen on the 768 * last packet we enqueued. 769 */ 770 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 771 AE_CDTXSYNC(sc, lasttx, 1, 772 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 773 774 /* 775 * The entire packet chain is set up. Give the 776 * first descriptor to the chip now. 777 */ 778 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 779 AE_CDTXSYNC(sc, firsttx, 1, 780 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 781 782 /* Wake up the transmitter. */ 783 /* XXX USE AUTOPOLLING? */ 784 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 785 AE_BARRIER(sc); 786 787 /* Set a watchdog timer in case the chip flakes out. */ 788 ifp->if_timer = 5; 789 } 790 } 791 792 /* 793 * ae_watchdog: [ifnet interface function] 794 * 795 * Watchdog timer handler. 796 */ 797 static void 798 ae_watchdog(struct ifnet *ifp) 799 { 800 struct ae_softc *sc = ifp->if_softc; 801 int doing_transmit; 802 803 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 804 805 if (doing_transmit) { 806 printf("%s: transmit timeout\n", sc->sc_dev.dv_xname); 807 ifp->if_oerrors++; 808 } 809 else 810 printf("%s: spurious watchdog timeout\n", sc->sc_dev.dv_xname); 811 812 (void) ae_init(ifp); 813 814 /* Try to get more packets going. */ 815 ae_start(ifp); 816 } 817 818 /* If the interface is up and running, only modify the receive 819 * filter when changing to/from promiscuous mode. Otherwise return 820 * ENETRESET so that ether_ioctl will reset the chip. 821 */ 822 static int 823 ae_ifflags_cb(struct ethercom *ec) 824 { 825 struct ifnet *ifp = &ec->ec_if; 826 struct ae_softc *sc = ifp->if_softc; 827 int change = ifp->if_flags ^ sc->sc_if_flags; 828 829 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 830 return ENETRESET; 831 else if ((change & IFF_PROMISC) != 0) 832 ae_filter_setup(sc); 833 return 0; 834 } 835 836 /* 837 * ae_ioctl: [ifnet interface function] 838 * 839 * Handle control requests from the operator. 840 */ 841 static int 842 ae_ioctl(struct ifnet *ifp, u_long cmd, void *data) 843 { 844 struct ae_softc *sc = ifp->if_softc; 845 int s, error; 846 847 s = splnet(); 848 849 error = ether_ioctl(ifp, cmd, data); 850 if (error == ENETRESET) { 851 if (ifp->if_flags & IFF_RUNNING) { 852 /* 853 * Multicast list has changed. Set the 854 * hardware filter accordingly. 855 */ 856 ae_filter_setup(sc); 857 } 858 error = 0; 859 } 860 861 /* Try to get more packets going. */ 862 if (AE_IS_ENABLED(sc)) 863 ae_start(ifp); 864 865 sc->sc_if_flags = ifp->if_flags; 866 splx(s); 867 return (error); 868 } 869 870 /* 871 * ae_intr: 872 * 873 * Interrupt service routine. 874 */ 875 int 876 ae_intr(void *arg) 877 { 878 struct ae_softc *sc = arg; 879 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 880 u_int32_t status, rxstatus, txstatus; 881 int handled = 0, txthresh; 882 883 DPRINTF(sc, ("%s: ae_intr\n", sc->sc_dev.dv_xname)); 884 885 #ifdef DEBUG 886 if (AE_IS_ENABLED(sc) == 0) 887 panic("%s: ae_intr: not enabled", sc->sc_dev.dv_xname); 888 #endif 889 890 /* 891 * If the interface isn't running, the interrupt couldn't 892 * possibly have come from us. 893 */ 894 if ((ifp->if_flags & IFF_RUNNING) == 0 || 895 !device_is_active(&sc->sc_dev)) { 896 printf("spurious?!?\n"); 897 return (0); 898 } 899 900 for (;;) { 901 status = AE_READ(sc, CSR_STATUS); 902 if (status) { 903 AE_WRITE(sc, CSR_STATUS, status); 904 AE_BARRIER(sc); 905 } 906 907 if ((status & sc->sc_inten) == 0) 908 break; 909 910 handled = 1; 911 912 rxstatus = status & sc->sc_rxint_mask; 913 txstatus = status & sc->sc_txint_mask; 914 915 if (rxstatus) { 916 /* Grab new any new packets. */ 917 ae_rxintr(sc); 918 919 if (rxstatus & STATUS_RU) { 920 printf("%s: receive ring overrun\n", 921 sc->sc_dev.dv_xname); 922 /* Get the receive process going again. */ 923 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 924 AE_BARRIER(sc); 925 break; 926 } 927 } 928 929 if (txstatus) { 930 /* Sweep up transmit descriptors. */ 931 ae_txintr(sc); 932 933 if (txstatus & STATUS_TJT) 934 printf("%s: transmit jabber timeout\n", 935 sc->sc_dev.dv_xname); 936 937 if (txstatus & STATUS_UNF) { 938 /* 939 * Increase our transmit threshold if 940 * another is available. 941 */ 942 txthresh = sc->sc_txthresh + 1; 943 if (ae_txthresh[txthresh].txth_name != NULL) { 944 uint32_t opmode; 945 /* Idle the transmit process. */ 946 opmode = AE_READ(sc, CSR_OPMODE); 947 ae_idle(sc, OPMODE_ST); 948 949 sc->sc_txthresh = txthresh; 950 opmode &= 951 ~(OPMODE_TR|OPMODE_SF); 952 opmode |= 953 ae_txthresh[txthresh].txth_opmode; 954 printf("%s: transmit underrun; new " 955 "threshold: %s\n", 956 sc->sc_dev.dv_xname, 957 ae_txthresh[txthresh].txth_name); 958 959 /* 960 * Set the new threshold and restart 961 * the transmit process. 962 */ 963 AE_WRITE(sc, CSR_OPMODE, opmode); 964 AE_BARRIER(sc); 965 } 966 /* 967 * XXX Log every Nth underrun from 968 * XXX now on? 969 */ 970 } 971 } 972 973 if (status & (STATUS_TPS|STATUS_RPS)) { 974 if (status & STATUS_TPS) 975 printf("%s: transmit process stopped\n", 976 sc->sc_dev.dv_xname); 977 if (status & STATUS_RPS) 978 printf("%s: receive process stopped\n", 979 sc->sc_dev.dv_xname); 980 (void) ae_init(ifp); 981 break; 982 } 983 984 if (status & STATUS_SE) { 985 const char *str; 986 987 if (status & STATUS_TX_ABORT) 988 str = "tx abort"; 989 else if (status & STATUS_RX_ABORT) 990 str = "rx abort"; 991 else 992 str = "unknown error"; 993 994 printf("%s: fatal system error: %s\n", 995 sc->sc_dev.dv_xname, str); 996 (void) ae_init(ifp); 997 break; 998 } 999 1000 /* 1001 * Not handled: 1002 * 1003 * Transmit buffer unavailable -- normal 1004 * condition, nothing to do, really. 1005 * 1006 * General purpose timer experied -- we don't 1007 * use the general purpose timer. 1008 * 1009 * Early receive interrupt -- not available on 1010 * all chips, we just use RI. We also only 1011 * use single-segment receive DMA, so this 1012 * is mostly useless. 1013 */ 1014 } 1015 1016 /* Try to get more packets going. */ 1017 ae_start(ifp); 1018 1019 #if NRND > 0 1020 if (handled) 1021 rnd_add_uint32(&sc->sc_rnd_source, status); 1022 #endif 1023 return (handled); 1024 } 1025 1026 /* 1027 * ae_rxintr: 1028 * 1029 * Helper; handle receive interrupts. 1030 */ 1031 static void 1032 ae_rxintr(struct ae_softc *sc) 1033 { 1034 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1035 struct ether_header *eh; 1036 struct ae_rxsoft *rxs; 1037 struct mbuf *m; 1038 u_int32_t rxstat; 1039 int i, len; 1040 1041 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1042 rxs = &sc->sc_rxsoft[i]; 1043 1044 AE_CDRXSYNC(sc, i, 1045 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1046 1047 rxstat = sc->sc_rxdescs[i].ad_status; 1048 1049 if (rxstat & ADSTAT_OWN) { 1050 /* 1051 * We have processed all of the receive buffers. 1052 */ 1053 break; 1054 } 1055 1056 /* 1057 * If any collisions were seen on the wire, count one. 1058 */ 1059 if (rxstat & ADSTAT_Rx_CS) 1060 ifp->if_collisions++; 1061 1062 /* 1063 * If an error occurred, update stats, clear the status 1064 * word, and leave the packet buffer in place. It will 1065 * simply be reused the next time the ring comes around. 1066 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1067 * error. 1068 */ 1069 if (rxstat & ADSTAT_ES && 1070 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1071 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1072 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1073 #define PRINTERR(bit, str) \ 1074 if (rxstat & (bit)) \ 1075 printf("%s: receive error: %s\n", \ 1076 sc->sc_dev.dv_xname, str) 1077 ifp->if_ierrors++; 1078 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1079 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1080 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1081 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1082 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1083 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1084 #undef PRINTERR 1085 AE_INIT_RXDESC(sc, i); 1086 continue; 1087 } 1088 1089 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1090 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1091 1092 /* 1093 * No errors; receive the packet. Note the chip 1094 * includes the CRC with every packet. 1095 */ 1096 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1097 1098 /* 1099 * XXX: the Atheros part can align on half words. what 1100 * is the performance implication of this? Probably 1101 * minimal, and we should use it... 1102 */ 1103 #ifdef __NO_STRICT_ALIGNMENT 1104 /* 1105 * Allocate a new mbuf cluster. If that fails, we are 1106 * out of memory, and must drop the packet and recycle 1107 * the buffer that's already attached to this descriptor. 1108 */ 1109 m = rxs->rxs_mbuf; 1110 if (ae_add_rxbuf(sc, i) != 0) { 1111 ifp->if_ierrors++; 1112 AE_INIT_RXDESC(sc, i); 1113 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1114 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1115 continue; 1116 } 1117 #else 1118 /* 1119 * The chip's receive buffers must be 4-byte aligned. 1120 * But this means that the data after the Ethernet header 1121 * is misaligned. We must allocate a new buffer and 1122 * copy the data, shifted forward 2 bytes. 1123 */ 1124 MGETHDR(m, M_DONTWAIT, MT_DATA); 1125 if (m == NULL) { 1126 dropit: 1127 ifp->if_ierrors++; 1128 AE_INIT_RXDESC(sc, i); 1129 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1130 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1131 continue; 1132 } 1133 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1134 if (len > (MHLEN - 2)) { 1135 MCLGET(m, M_DONTWAIT); 1136 if ((m->m_flags & M_EXT) == 0) { 1137 m_freem(m); 1138 goto dropit; 1139 } 1140 } 1141 m->m_data += 2; 1142 1143 /* 1144 * Note that we use clusters for incoming frames, so the 1145 * buffer is virtually contiguous. 1146 */ 1147 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 1148 1149 /* Allow the receive descriptor to continue using its mbuf. */ 1150 AE_INIT_RXDESC(sc, i); 1151 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1152 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1153 #endif /* __NO_STRICT_ALIGNMENT */ 1154 1155 ifp->if_ipackets++; 1156 eh = mtod(m, struct ether_header *); 1157 m->m_pkthdr.rcvif = ifp; 1158 m->m_pkthdr.len = m->m_len = len; 1159 1160 #if NBPFILTER > 0 1161 /* 1162 * Pass this up to any BPF listeners, but only 1163 * pass it up the stack if its for us. 1164 */ 1165 if (ifp->if_bpf) 1166 bpf_mtap(ifp->if_bpf, m); 1167 #endif /* NBPFILTER > 0 */ 1168 1169 /* Pass it on. */ 1170 (*ifp->if_input)(ifp, m); 1171 } 1172 1173 /* Update the receive pointer. */ 1174 sc->sc_rxptr = i; 1175 } 1176 1177 /* 1178 * ae_txintr: 1179 * 1180 * Helper; handle transmit interrupts. 1181 */ 1182 static void 1183 ae_txintr(struct ae_softc *sc) 1184 { 1185 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1186 struct ae_txsoft *txs; 1187 u_int32_t txstat; 1188 1189 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1190 sc->sc_dev.dv_xname, sc->sc_flags)); 1191 1192 ifp->if_flags &= ~IFF_OACTIVE; 1193 1194 /* 1195 * Go through our Tx list and free mbufs for those 1196 * frames that have been transmitted. 1197 */ 1198 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1199 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1200 txs->txs_ndescs, 1201 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1202 1203 #ifdef AE_DEBUG 1204 if (ifp->if_flags & IFF_DEBUG) { 1205 int i; 1206 printf(" txsoft %p transmit chain:\n", txs); 1207 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1208 printf(" descriptor %d:\n", i); 1209 printf(" ad_status: 0x%08x\n", 1210 sc->sc_txdescs[i].ad_status); 1211 printf(" ad_ctl: 0x%08x\n", 1212 sc->sc_txdescs[i].ad_ctl); 1213 printf(" ad_bufaddr1: 0x%08x\n", 1214 sc->sc_txdescs[i].ad_bufaddr1); 1215 printf(" ad_bufaddr2: 0x%08x\n", 1216 sc->sc_txdescs[i].ad_bufaddr2); 1217 if (i == txs->txs_lastdesc) 1218 break; 1219 } 1220 } 1221 #endif 1222 1223 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1224 if (txstat & ADSTAT_OWN) 1225 break; 1226 1227 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1228 1229 sc->sc_txfree += txs->txs_ndescs; 1230 1231 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1232 0, txs->txs_dmamap->dm_mapsize, 1233 BUS_DMASYNC_POSTWRITE); 1234 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1235 m_freem(txs->txs_mbuf); 1236 txs->txs_mbuf = NULL; 1237 1238 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1239 1240 /* 1241 * Check for errors and collisions. 1242 */ 1243 #ifdef AE_STATS 1244 if (txstat & ADSTAT_Tx_UF) 1245 sc->sc_stats.ts_tx_uf++; 1246 if (txstat & ADSTAT_Tx_TO) 1247 sc->sc_stats.ts_tx_to++; 1248 if (txstat & ADSTAT_Tx_EC) 1249 sc->sc_stats.ts_tx_ec++; 1250 if (txstat & ADSTAT_Tx_LC) 1251 sc->sc_stats.ts_tx_lc++; 1252 #endif 1253 1254 if (txstat & (ADSTAT_Tx_UF|ADSTAT_Tx_TO)) 1255 ifp->if_oerrors++; 1256 1257 if (txstat & ADSTAT_Tx_EC) 1258 ifp->if_collisions += 16; 1259 else 1260 ifp->if_collisions += ADSTAT_Tx_COLLISIONS(txstat); 1261 if (txstat & ADSTAT_Tx_LC) 1262 ifp->if_collisions++; 1263 1264 ifp->if_opackets++; 1265 } 1266 1267 /* 1268 * If there are no more pending transmissions, cancel the watchdog 1269 * timer. 1270 */ 1271 if (txs == NULL) 1272 ifp->if_timer = 0; 1273 } 1274 1275 #ifdef AE_STATS 1276 void 1277 ae_print_stats(struct ae_softc *sc) 1278 { 1279 1280 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1281 sc->sc_dev.dv_xname, 1282 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1283 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1284 } 1285 #endif 1286 1287 /* 1288 * ae_reset: 1289 * 1290 * Perform a soft reset on the chip. 1291 */ 1292 void 1293 ae_reset(struct ae_softc *sc) 1294 { 1295 int i; 1296 1297 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1298 AE_BARRIER(sc); 1299 1300 /* 1301 * The chip doesn't take itself out of reset automatically. 1302 * We need to do so after 2us. 1303 */ 1304 delay(10); 1305 AE_WRITE(sc, CSR_BUSMODE, 0); 1306 AE_BARRIER(sc); 1307 1308 for (i = 0; i < 1000; i++) { 1309 /* 1310 * Wait a bit for the reset to complete before peeking 1311 * at the chip again. 1312 */ 1313 delay(10); 1314 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1315 break; 1316 } 1317 1318 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1319 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1320 1321 delay(1000); 1322 } 1323 1324 /* 1325 * ae_init: [ ifnet interface function ] 1326 * 1327 * Initialize the interface. Must be called at splnet(). 1328 */ 1329 static int 1330 ae_init(struct ifnet *ifp) 1331 { 1332 struct ae_softc *sc = ifp->if_softc; 1333 struct ae_txsoft *txs; 1334 struct ae_rxsoft *rxs; 1335 const uint8_t *enaddr; 1336 int i, error = 0; 1337 1338 if ((error = ae_enable(sc)) != 0) 1339 goto out; 1340 1341 /* 1342 * Cancel any pending I/O. 1343 */ 1344 ae_stop(ifp, 0); 1345 1346 /* 1347 * Reset the chip to a known state. 1348 */ 1349 ae_reset(sc); 1350 1351 /* 1352 * Initialize the BUSMODE register. 1353 */ 1354 AE_WRITE(sc, CSR_BUSMODE, 1355 /* XXX: not sure if this is a good thing or not... */ 1356 //BUSMODE_ALIGN_16B | 1357 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1358 AE_BARRIER(sc); 1359 1360 /* 1361 * Initialize the transmit descriptor ring. 1362 */ 1363 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1364 for (i = 0; i < AE_NTXDESC; i++) { 1365 sc->sc_txdescs[i].ad_ctl = 0; 1366 sc->sc_txdescs[i].ad_bufaddr2 = 1367 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1368 } 1369 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1370 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1371 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1372 sc->sc_txfree = AE_NTXDESC; 1373 sc->sc_txnext = 0; 1374 1375 /* 1376 * Initialize the transmit job descriptors. 1377 */ 1378 SIMPLEQ_INIT(&sc->sc_txfreeq); 1379 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1380 for (i = 0; i < AE_TXQUEUELEN; i++) { 1381 txs = &sc->sc_txsoft[i]; 1382 txs->txs_mbuf = NULL; 1383 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1384 } 1385 1386 /* 1387 * Initialize the receive descriptor and receive job 1388 * descriptor rings. 1389 */ 1390 for (i = 0; i < AE_NRXDESC; i++) { 1391 rxs = &sc->sc_rxsoft[i]; 1392 if (rxs->rxs_mbuf == NULL) { 1393 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1394 printf("%s: unable to allocate or map rx " 1395 "buffer %d, error = %d\n", 1396 sc->sc_dev.dv_xname, i, error); 1397 /* 1398 * XXX Should attempt to run with fewer receive 1399 * XXX buffers instead of just failing. 1400 */ 1401 ae_rxdrain(sc); 1402 goto out; 1403 } 1404 } else 1405 AE_INIT_RXDESC(sc, i); 1406 } 1407 sc->sc_rxptr = 0; 1408 1409 /* 1410 * Initialize the interrupt mask and enable interrupts. 1411 */ 1412 /* normal interrupts */ 1413 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1414 1415 /* abnormal interrupts */ 1416 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1417 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1418 1419 sc->sc_rxint_mask = STATUS_RI|STATUS_RU; 1420 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT; 1421 1422 sc->sc_rxint_mask &= sc->sc_inten; 1423 sc->sc_txint_mask &= sc->sc_inten; 1424 1425 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1426 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1427 1428 /* 1429 * Give the transmit and receive rings to the chip. 1430 */ 1431 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1432 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1433 AE_BARRIER(sc); 1434 1435 /* 1436 * Set the station address. 1437 */ 1438 enaddr = CLLADDR(ifp->if_sadl); 1439 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1440 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1441 enaddr[1] << 8 | enaddr[0]); 1442 AE_BARRIER(sc); 1443 1444 /* 1445 * Set the receive filter. This will start the transmit and 1446 * receive processes. 1447 */ 1448 ae_filter_setup(sc); 1449 1450 /* 1451 * Set the current media. 1452 */ 1453 if ((error = ether_mediachange(ifp)) != 0) 1454 goto out; 1455 1456 /* 1457 * Start the mac. 1458 */ 1459 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1460 AE_BARRIER(sc); 1461 1462 /* 1463 * Write out the opmode. 1464 */ 1465 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1466 ae_txthresh[sc->sc_txthresh].txth_opmode); 1467 /* 1468 * Start the receive process. 1469 */ 1470 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1471 AE_BARRIER(sc); 1472 1473 if (sc->sc_tick != NULL) { 1474 /* Start the one second clock. */ 1475 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1476 } 1477 1478 /* 1479 * Note that the interface is now running. 1480 */ 1481 ifp->if_flags |= IFF_RUNNING; 1482 ifp->if_flags &= ~IFF_OACTIVE; 1483 sc->sc_if_flags = ifp->if_flags; 1484 1485 out: 1486 if (error) { 1487 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1488 ifp->if_timer = 0; 1489 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1490 } 1491 return (error); 1492 } 1493 1494 /* 1495 * ae_enable: 1496 * 1497 * Enable the chip. 1498 */ 1499 static int 1500 ae_enable(struct ae_softc *sc) 1501 { 1502 1503 if (AE_IS_ENABLED(sc) == 0) { 1504 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1505 ae_intr, sc); 1506 if (sc->sc_ih == NULL) { 1507 printf("%s: unable to establish interrupt\n", 1508 sc->sc_dev.dv_xname); 1509 return (EIO); 1510 } 1511 sc->sc_flags |= AE_ENABLED; 1512 } 1513 return (0); 1514 } 1515 1516 /* 1517 * ae_disable: 1518 * 1519 * Disable the chip. 1520 */ 1521 static void 1522 ae_disable(struct ae_softc *sc) 1523 { 1524 1525 if (AE_IS_ENABLED(sc)) { 1526 arbus_intr_disestablish(sc->sc_ih); 1527 sc->sc_flags &= ~AE_ENABLED; 1528 } 1529 } 1530 1531 /* 1532 * ae_power: 1533 * 1534 * Power management (suspend/resume) hook. 1535 */ 1536 static void 1537 ae_power(int why, void *arg) 1538 { 1539 struct ae_softc *sc = arg; 1540 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1541 int s; 1542 1543 printf("power called: %d, %x\n", why, (uint32_t)arg); 1544 s = splnet(); 1545 switch (why) { 1546 case PWR_STANDBY: 1547 /* do nothing! */ 1548 break; 1549 case PWR_SUSPEND: 1550 ae_stop(ifp, 0); 1551 ae_disable(sc); 1552 break; 1553 case PWR_RESUME: 1554 if (ifp->if_flags & IFF_UP) { 1555 ae_enable(sc); 1556 ae_init(ifp); 1557 } 1558 break; 1559 case PWR_SOFTSUSPEND: 1560 case PWR_SOFTSTANDBY: 1561 case PWR_SOFTRESUME: 1562 break; 1563 } 1564 splx(s); 1565 } 1566 1567 /* 1568 * ae_rxdrain: 1569 * 1570 * Drain the receive queue. 1571 */ 1572 static void 1573 ae_rxdrain(struct ae_softc *sc) 1574 { 1575 struct ae_rxsoft *rxs; 1576 int i; 1577 1578 for (i = 0; i < AE_NRXDESC; i++) { 1579 rxs = &sc->sc_rxsoft[i]; 1580 if (rxs->rxs_mbuf != NULL) { 1581 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1582 m_freem(rxs->rxs_mbuf); 1583 rxs->rxs_mbuf = NULL; 1584 } 1585 } 1586 } 1587 1588 /* 1589 * ae_stop: [ ifnet interface function ] 1590 * 1591 * Stop transmission on the interface. 1592 */ 1593 static void 1594 ae_stop(struct ifnet *ifp, int disable) 1595 { 1596 struct ae_softc *sc = ifp->if_softc; 1597 struct ae_txsoft *txs; 1598 1599 if (sc->sc_tick != NULL) { 1600 /* Stop the one second clock. */ 1601 callout_stop(&sc->sc_tick_callout); 1602 } 1603 1604 /* Down the MII. */ 1605 mii_down(&sc->sc_mii); 1606 1607 /* Disable interrupts. */ 1608 AE_WRITE(sc, CSR_INTEN, 0); 1609 1610 /* Stop the transmit and receive processes. */ 1611 AE_WRITE(sc, CSR_OPMODE, 0); 1612 AE_WRITE(sc, CSR_RXLIST, 0); 1613 AE_WRITE(sc, CSR_TXLIST, 0); 1614 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1615 AE_BARRIER(sc); 1616 1617 /* 1618 * Release any queued transmit buffers. 1619 */ 1620 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1621 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1622 if (txs->txs_mbuf != NULL) { 1623 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1624 m_freem(txs->txs_mbuf); 1625 txs->txs_mbuf = NULL; 1626 } 1627 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1628 } 1629 1630 /* 1631 * Mark the interface down and cancel the watchdog timer. 1632 */ 1633 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1634 sc->sc_if_flags = ifp->if_flags; 1635 ifp->if_timer = 0; 1636 1637 if (disable) { 1638 ae_rxdrain(sc); 1639 ae_disable(sc); 1640 } 1641 1642 /* 1643 * Reset the chip (needed on some flavors to actually disable it). 1644 */ 1645 ae_reset(sc); 1646 } 1647 1648 /* 1649 * ae_add_rxbuf: 1650 * 1651 * Add a receive buffer to the indicated descriptor. 1652 */ 1653 static int 1654 ae_add_rxbuf(struct ae_softc *sc, int idx) 1655 { 1656 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1657 struct mbuf *m; 1658 int error; 1659 1660 MGETHDR(m, M_DONTWAIT, MT_DATA); 1661 if (m == NULL) 1662 return (ENOBUFS); 1663 1664 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1665 MCLGET(m, M_DONTWAIT); 1666 if ((m->m_flags & M_EXT) == 0) { 1667 m_freem(m); 1668 return (ENOBUFS); 1669 } 1670 1671 if (rxs->rxs_mbuf != NULL) 1672 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1673 1674 rxs->rxs_mbuf = m; 1675 1676 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1677 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1678 BUS_DMA_READ|BUS_DMA_NOWAIT); 1679 if (error) { 1680 printf("%s: can't load rx DMA map %d, error = %d\n", 1681 sc->sc_dev.dv_xname, idx, error); 1682 panic("ae_add_rxbuf"); /* XXX */ 1683 } 1684 1685 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1686 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1687 1688 AE_INIT_RXDESC(sc, idx); 1689 1690 return (0); 1691 } 1692 1693 /* 1694 * ae_filter_setup: 1695 * 1696 * Set the chip's receive filter. 1697 */ 1698 static void 1699 ae_filter_setup(struct ae_softc *sc) 1700 { 1701 struct ethercom *ec = &sc->sc_ethercom; 1702 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1703 struct ether_multi *enm; 1704 struct ether_multistep step; 1705 uint32_t hash, mchash[2]; 1706 uint32_t macctl = 0; 1707 1708 /* 1709 * If the chip is running, we need to reset the interface, 1710 * and will revisit here (with IFF_RUNNING) clear. The 1711 * chip seems to really not like to have its multicast 1712 * filter programmed without a reset. 1713 */ 1714 if (ifp->if_flags & IFF_RUNNING) { 1715 (void) ae_init(ifp); 1716 return; 1717 } 1718 1719 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1720 sc->sc_dev.dv_xname, sc->sc_flags)); 1721 1722 macctl = AE_READ(sc, CSR_MACCTL); 1723 macctl &= ~(MACCTL_PR | MACCTL_PM); 1724 macctl |= MACCTL_HASH; 1725 macctl |= MACCTL_HBD; 1726 macctl |= MACCTL_PR; 1727 1728 if (ifp->if_flags & IFF_PROMISC) { 1729 macctl |= MACCTL_PR; 1730 goto allmulti; 1731 } 1732 1733 mchash[0] = mchash[1] = 0; 1734 1735 ETHER_FIRST_MULTI(step, ec, enm); 1736 while (enm != NULL) { 1737 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1738 /* 1739 * We must listen to a range of multicast addresses. 1740 * For now, just accept all multicasts, rather than 1741 * trying to set only those filter bits needed to match 1742 * the range. (At this time, the only use of address 1743 * ranges is for IP multicast routing, for which the 1744 * range is big enough to require all bits set.) 1745 */ 1746 goto allmulti; 1747 } 1748 1749 /* Verify whether we use big or little endian hashes */ 1750 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1751 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1752 ETHER_NEXT_MULTI(step, enm); 1753 } 1754 ifp->if_flags &= ~IFF_ALLMULTI; 1755 goto setit; 1756 1757 allmulti: 1758 ifp->if_flags |= IFF_ALLMULTI; 1759 mchash[0] = mchash[1] = 0xffffffff; 1760 macctl |= MACCTL_PM; 1761 1762 setit: 1763 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1764 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1765 1766 AE_WRITE(sc, CSR_MACCTL, macctl); 1767 AE_BARRIER(sc); 1768 1769 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1770 sc->sc_dev.dv_xname, macctl)); 1771 } 1772 1773 /* 1774 * ae_idle: 1775 * 1776 * Cause the transmit and/or receive processes to go idle. 1777 */ 1778 void 1779 ae_idle(struct ae_softc *sc, u_int32_t bits) 1780 { 1781 static const char * const txstate_names[] = { 1782 "STOPPED", 1783 "RUNNING - FETCH", 1784 "RUNNING - WAIT", 1785 "RUNNING - READING", 1786 "-- RESERVED --", 1787 "RUNNING - SETUP", 1788 "SUSPENDED", 1789 "RUNNING - CLOSE", 1790 }; 1791 static const char * const rxstate_names[] = { 1792 "STOPPED", 1793 "RUNNING - FETCH", 1794 "RUNNING - CHECK", 1795 "RUNNING - WAIT", 1796 "SUSPENDED", 1797 "RUNNING - CLOSE", 1798 "RUNNING - FLUSH", 1799 "RUNNING - QUEUE", 1800 }; 1801 1802 u_int32_t csr, ackmask = 0; 1803 int i; 1804 1805 if (bits & OPMODE_ST) 1806 ackmask |= STATUS_TPS; 1807 1808 if (bits & OPMODE_SR) 1809 ackmask |= STATUS_RPS; 1810 1811 AE_CLR(sc, CSR_OPMODE, bits); 1812 1813 for (i = 0; i < 1000; i++) { 1814 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1815 break; 1816 delay(10); 1817 } 1818 1819 csr = AE_READ(sc, CSR_STATUS); 1820 if ((csr & ackmask) != ackmask) { 1821 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1822 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1823 printf("%s: transmit process failed to idle: " 1824 "state %s\n", sc->sc_dev.dv_xname, 1825 txstate_names[(csr & STATUS_TS) >> 20]); 1826 } 1827 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1828 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1829 printf("%s: receive process failed to idle: " 1830 "state %s\n", sc->sc_dev.dv_xname, 1831 rxstate_names[(csr & STATUS_RS) >> 17]); 1832 } 1833 } 1834 } 1835 1836 /***************************************************************************** 1837 * Support functions for MII-attached media. 1838 *****************************************************************************/ 1839 1840 /* 1841 * ae_mii_tick: 1842 * 1843 * One second timer, used to tick the MII. 1844 */ 1845 static void 1846 ae_mii_tick(void *arg) 1847 { 1848 struct ae_softc *sc = arg; 1849 int s; 1850 1851 if (!device_is_active(&sc->sc_dev)) 1852 return; 1853 1854 s = splnet(); 1855 mii_tick(&sc->sc_mii); 1856 splx(s); 1857 1858 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1859 } 1860 1861 /* 1862 * ae_mii_statchg: [mii interface function] 1863 * 1864 * Callback from PHY when media changes. 1865 */ 1866 static void 1867 ae_mii_statchg(device_t self) 1868 { 1869 struct ae_softc *sc = device_private(self); 1870 uint32_t macctl, flowc; 1871 1872 //opmode = AE_READ(sc, CSR_OPMODE); 1873 macctl = AE_READ(sc, CSR_MACCTL); 1874 1875 /* XXX: do we need to do this? */ 1876 /* Idle the transmit and receive processes. */ 1877 //ae_idle(sc, OPMODE_ST|OPMODE_SR); 1878 1879 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1880 flowc = FLOWC_FCE; 1881 macctl &= ~MACCTL_DRO; 1882 macctl |= MACCTL_FDX; 1883 } else { 1884 flowc = 0; /* cannot do flow control in HDX */ 1885 macctl |= MACCTL_DRO; 1886 macctl &= ~MACCTL_FDX; 1887 } 1888 1889 AE_WRITE(sc, CSR_FLOWC, flowc); 1890 AE_WRITE(sc, CSR_MACCTL, macctl); 1891 1892 /* restore operational mode */ 1893 //AE_WRITE(sc, CSR_OPMODE, opmode); 1894 AE_BARRIER(sc); 1895 } 1896 1897 /* 1898 * ae_mii_readreg: 1899 * 1900 * Read a PHY register. 1901 */ 1902 static int 1903 ae_mii_readreg(device_t self, int phy, int reg) 1904 { 1905 struct ae_softc *sc = device_private(self); 1906 uint32_t addr; 1907 int i; 1908 1909 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1910 AE_WRITE(sc, CSR_MIIADDR, addr); 1911 AE_BARRIER(sc); 1912 for (i = 0; i < 100000000; i++) { 1913 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1914 break; 1915 } 1916 1917 return (AE_READ(sc, CSR_MIIDATA) & 0xffff); 1918 } 1919 1920 /* 1921 * ae_mii_writereg: 1922 * 1923 * Write a PHY register. 1924 */ 1925 static void 1926 ae_mii_writereg(device_t self, int phy, int reg, int val) 1927 { 1928 struct ae_softc *sc = device_private(self); 1929 uint32_t addr; 1930 int i; 1931 1932 /* write the data register */ 1933 AE_WRITE(sc, CSR_MIIDATA, val); 1934 1935 /* write the address to latch it in */ 1936 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1937 MIIADDR_WRITE; 1938 AE_WRITE(sc, CSR_MIIADDR, addr); 1939 AE_BARRIER(sc); 1940 1941 for (i = 0; i < 100000000; i++) { 1942 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1943 break; 1944 } 1945 } 1946
Indexes created Thu Oct 02 14:10:14 GMT 2025