if_ae.c revision 1.16
1 /* $Id: if_ae.c,v 1.16 2009/11/12 19:18:55 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the onboard ethernet MAC found on the AR5312 74 * chip's AHB bus. 75 * 76 * This device is very simliar to the tulip in most regards, and 77 * the code is directly derived from NetBSD's tulip.c. However, it 78 * is different enough that it did not seem to be a good idea to 79 * add further complexity to the tulip driver, so we have our own. 80 * 81 * Also tulip has a lot of complexity in it for various parts/options 82 * that we don't need, and on these little boxes with only ~8MB RAM, we 83 * don't want any extra bloat. 84 */ 85 86 /* 87 * TODO: 88 * 89 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 90 * inbound packets on a half-word boundary, which would make life easier 91 * for TCP/IP. (Aligning IP headers on a word.) 92 * 93 * 2) There is stuff in original tulip to shut down the device when reacting 94 * to a a change in link status. Is that needed. 95 * 96 * 3) Test with variety of 10/100 HDX/FDX scenarios. 97 * 98 */ 99 100 #include <sys/cdefs.h> 101 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.16 2009/11/12 19:18:55 dyoung Exp $"); 102 103 #include "bpfilter.h" 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/callout.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/ioctl.h> 113 #include <sys/errno.h> 114 #include <sys/device.h> 115 116 #include <machine/endian.h> 117 118 #include <uvm/uvm_extern.h> 119 120 #include <net/if.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_ether.h> 124 125 #if NBPFILTER > 0 126 #include <net/bpf.h> 127 #endif 128 129 #include <machine/bus.h> 130 #include <machine/intr.h> 131 132 #include <dev/mii/mii.h> 133 #include <dev/mii/miivar.h> 134 #include <dev/mii/mii_bitbang.h> 135 136 #include <mips/atheros/include/arbusvar.h> 137 #include <mips/atheros/dev/aereg.h> 138 #include <mips/atheros/dev/aevar.h> 139 140 static const struct { 141 u_int32_t txth_opmode; /* OPMODE bits */ 142 const char *txth_name; /* name of mode */ 143 } ae_txthresh[] = { 144 { OPMODE_TR_32, "32 words" }, 145 { OPMODE_TR_64, "64 words" }, 146 { OPMODE_TR_128, "128 words" }, 147 { OPMODE_TR_256, "256 words" }, 148 { OPMODE_SF, "store and forward mode" }, 149 { 0, NULL }, 150 }; 151 152 static int ae_match(device_t, struct cfdata *, void *); 153 static void ae_attach(device_t, device_t, void *); 154 static int ae_detach(device_t, int); 155 static int ae_activate(device_t, enum devact); 156 157 static int ae_ifflags_cb(struct ethercom *); 158 static void ae_reset(struct ae_softc *); 159 static void ae_idle(struct ae_softc *, u_int32_t); 160 161 static void ae_start(struct ifnet *); 162 static void ae_watchdog(struct ifnet *); 163 static int ae_ioctl(struct ifnet *, u_long, void *); 164 static int ae_init(struct ifnet *); 165 static void ae_stop(struct ifnet *, int); 166 167 static void ae_shutdown(void *); 168 169 static void ae_rxdrain(struct ae_softc *); 170 static int ae_add_rxbuf(struct ae_softc *, int); 171 172 static int ae_enable(struct ae_softc *); 173 static void ae_disable(struct ae_softc *); 174 static void ae_power(int, void *); 175 176 static void ae_filter_setup(struct ae_softc *); 177 178 static int ae_intr(void *); 179 static void ae_rxintr(struct ae_softc *); 180 static void ae_txintr(struct ae_softc *); 181 182 static void ae_mii_tick(void *); 183 static void ae_mii_statchg(device_t); 184 185 static int ae_mii_readreg(device_t, int, int); 186 static void ae_mii_writereg(device_t, int, int, int); 187 188 #ifdef AE_DEBUG 189 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 190 printf x 191 #else 192 #define DPRINTF(sc, x) /* nothing */ 193 #endif 194 195 #ifdef AE_STATS 196 static void ae_print_stats(struct ae_softc *); 197 #endif 198 199 CFATTACH_DECL(ae, sizeof(struct ae_softc), 200 ae_match, ae_attach, ae_detach, ae_activate); 201 202 /* 203 * ae_match: 204 * 205 * Check for a device match. 206 */ 207 int 208 ae_match(device_t parent, struct cfdata *cf, void *aux) 209 { 210 struct arbus_attach_args *aa = aux; 211 212 if (strcmp(aa->aa_name, cf->cf_name) == 0) 213 return 1; 214 215 return 0; 216 217 } 218 219 /* 220 * ae_attach: 221 * 222 * Attach an ae interface to the system. 223 */ 224 void 225 ae_attach(device_t parent, device_t self, void *aux) 226 { 227 const uint8_t *enaddr; 228 prop_data_t ea; 229 struct ae_softc *sc = device_private(self); 230 struct arbus_attach_args *aa = aux; 231 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 232 int i, error; 233 234 callout_init(&sc->sc_tick_callout, 0); 235 236 printf(": Atheros AR531X 10/100 Ethernet\n"); 237 238 /* 239 * Try to get MAC address. 240 */ 241 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 242 if (ea == NULL) { 243 printf("%s: unable to get mac-addr property\n", 244 sc->sc_dev.dv_xname); 245 return; 246 } 247 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 248 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 249 enaddr = prop_data_data_nocopy(ea); 250 251 /* Announce ourselves. */ 252 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 253 ether_sprintf(enaddr)); 254 255 sc->sc_cirq = aa->aa_cirq; 256 sc->sc_mirq = aa->aa_mirq; 257 sc->sc_st = aa->aa_bst; 258 sc->sc_dmat = aa->aa_dmat; 259 260 SIMPLEQ_INIT(&sc->sc_txfreeq); 261 SIMPLEQ_INIT(&sc->sc_txdirtyq); 262 263 /* 264 * Map registers. 265 */ 266 sc->sc_size = aa->aa_size; 267 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 268 &sc->sc_sh)) != 0) { 269 printf("%s: unable to map registers, error = %d\n", 270 sc->sc_dev.dv_xname, error); 271 goto fail_0; 272 } 273 274 /* 275 * Allocate the control data structures, and create and load the 276 * DMA map for it. 277 */ 278 if ((error = bus_dmamem_alloc(sc->sc_dmat, 279 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 280 1, &sc->sc_cdnseg, 0)) != 0) { 281 printf("%s: unable to allocate control data, error = %d\n", 282 sc->sc_dev.dv_xname, error); 283 goto fail_1; 284 } 285 286 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 287 sizeof(struct ae_control_data), (void **)&sc->sc_control_data, 288 BUS_DMA_COHERENT)) != 0) { 289 printf("%s: unable to map control data, error = %d\n", 290 sc->sc_dev.dv_xname, error); 291 goto fail_2; 292 } 293 294 if ((error = bus_dmamap_create(sc->sc_dmat, 295 sizeof(struct ae_control_data), 1, 296 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 297 printf("%s: unable to create control data DMA map, " 298 "error = %d\n", sc->sc_dev.dv_xname, error); 299 goto fail_3; 300 } 301 302 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 303 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 304 0)) != 0) { 305 printf("%s: unable to load control data DMA map, error = %d\n", 306 sc->sc_dev.dv_xname, error); 307 goto fail_4; 308 } 309 310 /* 311 * Create the transmit buffer DMA maps. 312 */ 313 for (i = 0; i < AE_TXQUEUELEN; i++) { 314 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 315 AE_NTXSEGS, MCLBYTES, 0, 0, 316 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 317 printf("%s: unable to create tx DMA map %d, " 318 "error = %d\n", sc->sc_dev.dv_xname, i, error); 319 goto fail_5; 320 } 321 } 322 323 /* 324 * Create the receive buffer DMA maps. 325 */ 326 for (i = 0; i < AE_NRXDESC; i++) { 327 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 328 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 329 printf("%s: unable to create rx DMA map %d, " 330 "error = %d\n", sc->sc_dev.dv_xname, i, error); 331 goto fail_6; 332 } 333 sc->sc_rxsoft[i].rxs_mbuf = NULL; 334 } 335 336 /* 337 * Reset the chip to a known state. 338 */ 339 ae_reset(sc); 340 341 /* 342 * From this point forward, the attachment cannot fail. A failure 343 * before this point releases all resources that may have been 344 * allocated. 345 */ 346 sc->sc_flags |= AE_ATTACHED; 347 348 /* 349 * Initialize our media structures. This may probe the MII, if 350 * present. 351 */ 352 sc->sc_mii.mii_ifp = ifp; 353 sc->sc_mii.mii_readreg = ae_mii_readreg; 354 sc->sc_mii.mii_writereg = ae_mii_writereg; 355 sc->sc_mii.mii_statchg = ae_mii_statchg; 356 sc->sc_ethercom.ec_mii = &sc->sc_mii; 357 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 358 ether_mediastatus); 359 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 360 MII_OFFSET_ANY, 0); 361 362 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 363 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 364 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 365 } else 366 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 367 368 sc->sc_tick = ae_mii_tick; 369 370 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 371 ifp->if_softc = sc; 372 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 373 sc->sc_if_flags = ifp->if_flags; 374 ifp->if_ioctl = ae_ioctl; 375 ifp->if_start = ae_start; 376 ifp->if_watchdog = ae_watchdog; 377 ifp->if_init = ae_init; 378 ifp->if_stop = ae_stop; 379 IFQ_SET_READY(&ifp->if_snd); 380 381 /* 382 * We can support 802.1Q VLAN-sized frames. 383 */ 384 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 385 386 /* 387 * Attach the interface. 388 */ 389 if_attach(ifp); 390 ether_ifattach(ifp, enaddr); 391 ether_set_ifflags_cb(&sc->sc_ethercom, ae_ifflags_cb); 392 393 #if NRND > 0 394 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 395 RND_TYPE_NET, 0); 396 #endif 397 398 /* 399 * Make sure the interface is shutdown during reboot. 400 */ 401 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 402 if (sc->sc_sdhook == NULL) 403 printf("%s: WARNING: unable to establish shutdown hook\n", 404 sc->sc_dev.dv_xname); 405 406 /* 407 * Add a suspend hook to make sure we come back up after a 408 * resume. 409 */ 410 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 411 ae_power, sc); 412 if (sc->sc_powerhook == NULL) 413 printf("%s: WARNING: unable to establish power hook\n", 414 sc->sc_dev.dv_xname); 415 return; 416 417 /* 418 * Free any resources we've allocated during the failed attach 419 * attempt. Do this in reverse order and fall through. 420 */ 421 fail_6: 422 for (i = 0; i < AE_NRXDESC; i++) { 423 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 424 bus_dmamap_destroy(sc->sc_dmat, 425 sc->sc_rxsoft[i].rxs_dmamap); 426 } 427 fail_5: 428 for (i = 0; i < AE_TXQUEUELEN; i++) { 429 if (sc->sc_txsoft[i].txs_dmamap != NULL) 430 bus_dmamap_destroy(sc->sc_dmat, 431 sc->sc_txsoft[i].txs_dmamap); 432 } 433 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 434 fail_4: 435 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 436 fail_3: 437 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 438 sizeof(struct ae_control_data)); 439 fail_2: 440 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 441 fail_1: 442 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 443 fail_0: 444 return; 445 } 446 447 /* 448 * ae_activate: 449 * 450 * Handle device activation/deactivation requests. 451 */ 452 int 453 ae_activate(device_t self, enum devact act) 454 { 455 struct ae_softc *sc = device_private(self); 456 457 switch (act) { 458 case DVACT_DEACTIVATE: 459 if_deactivate(&sc->sc_ethercom.ec_if); 460 return 0; 461 default: 462 return EOPNOTSUPP; 463 } 464 } 465 466 /* 467 * ae_detach: 468 * 469 * Detach a device interface. 470 */ 471 int 472 ae_detach(device_t self, int flags) 473 { 474 struct ae_softc *sc = device_private(self); 475 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 476 struct ae_rxsoft *rxs; 477 struct ae_txsoft *txs; 478 int i; 479 480 /* 481 * Succeed now if there isn't any work to do. 482 */ 483 if ((sc->sc_flags & AE_ATTACHED) == 0) 484 return (0); 485 486 /* Unhook our tick handler. */ 487 if (sc->sc_tick) 488 callout_stop(&sc->sc_tick_callout); 489 490 /* Detach all PHYs */ 491 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 492 493 /* Delete all remaining media. */ 494 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 495 496 #if NRND > 0 497 rnd_detach_source(&sc->sc_rnd_source); 498 #endif 499 ether_ifdetach(ifp); 500 if_detach(ifp); 501 502 for (i = 0; i < AE_NRXDESC; i++) { 503 rxs = &sc->sc_rxsoft[i]; 504 if (rxs->rxs_mbuf != NULL) { 505 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 506 m_freem(rxs->rxs_mbuf); 507 rxs->rxs_mbuf = NULL; 508 } 509 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 510 } 511 for (i = 0; i < AE_TXQUEUELEN; i++) { 512 txs = &sc->sc_txsoft[i]; 513 if (txs->txs_mbuf != NULL) { 514 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 515 m_freem(txs->txs_mbuf); 516 txs->txs_mbuf = NULL; 517 } 518 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 519 } 520 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 521 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 522 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 523 sizeof(struct ae_control_data)); 524 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 525 526 shutdownhook_disestablish(sc->sc_sdhook); 527 powerhook_disestablish(sc->sc_powerhook); 528 529 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 530 531 532 return (0); 533 } 534 535 /* 536 * ae_shutdown: 537 * 538 * Make sure the interface is stopped at reboot time. 539 */ 540 static void 541 ae_shutdown(void *arg) 542 { 543 struct ae_softc *sc = arg; 544 545 ae_stop(&sc->sc_ethercom.ec_if, 1); 546 } 547 548 /* 549 * ae_start: [ifnet interface function] 550 * 551 * Start packet transmission on the interface. 552 */ 553 static void 554 ae_start(struct ifnet *ifp) 555 { 556 struct ae_softc *sc = ifp->if_softc; 557 struct mbuf *m0, *m; 558 struct ae_txsoft *txs, *last_txs = NULL; 559 bus_dmamap_t dmamap; 560 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 561 562 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 563 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 564 565 566 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 567 return; 568 569 /* 570 * Remember the previous number of free descriptors and 571 * the first descriptor we'll use. 572 */ 573 ofree = sc->sc_txfree; 574 firsttx = sc->sc_txnext; 575 576 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 577 sc->sc_dev.dv_xname, ofree, firsttx)); 578 579 /* 580 * Loop through the send queue, setting up transmit descriptors 581 * until we drain the queue, or use up all available transmit 582 * descriptors. 583 */ 584 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 585 sc->sc_txfree != 0) { 586 /* 587 * Grab a packet off the queue. 588 */ 589 IFQ_POLL(&ifp->if_snd, m0); 590 if (m0 == NULL) 591 break; 592 m = NULL; 593 594 dmamap = txs->txs_dmamap; 595 596 /* 597 * Load the DMA map. If this fails, the packet either 598 * didn't fit in the alloted number of segments, or we were 599 * short on resources. In this case, we'll copy and try 600 * again. 601 */ 602 if (((mtod(m0, uintptr_t) & 3) != 0) || 603 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 604 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 605 MGETHDR(m, M_DONTWAIT, MT_DATA); 606 if (m == NULL) { 607 printf("%s: unable to allocate Tx mbuf\n", 608 sc->sc_dev.dv_xname); 609 break; 610 } 611 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 612 if (m0->m_pkthdr.len > MHLEN) { 613 MCLGET(m, M_DONTWAIT); 614 if ((m->m_flags & M_EXT) == 0) { 615 printf("%s: unable to allocate Tx " 616 "cluster\n", sc->sc_dev.dv_xname); 617 m_freem(m); 618 break; 619 } 620 } 621 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 622 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 623 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 624 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 625 if (error) { 626 printf("%s: unable to load Tx buffer, " 627 "error = %d\n", sc->sc_dev.dv_xname, 628 error); 629 break; 630 } 631 } 632 633 /* 634 * Ensure we have enough descriptors free to describe 635 * the packet. 636 */ 637 if (dmamap->dm_nsegs > sc->sc_txfree) { 638 /* 639 * Not enough free descriptors to transmit this 640 * packet. We haven't committed to anything yet, 641 * so just unload the DMA map, put the packet 642 * back on the queue, and punt. Notify the upper 643 * layer that there are no more slots left. 644 * 645 * XXX We could allocate an mbuf and copy, but 646 * XXX it is worth it? 647 */ 648 ifp->if_flags |= IFF_OACTIVE; 649 bus_dmamap_unload(sc->sc_dmat, dmamap); 650 if (m != NULL) 651 m_freem(m); 652 break; 653 } 654 655 IFQ_DEQUEUE(&ifp->if_snd, m0); 656 if (m != NULL) { 657 m_freem(m0); 658 m0 = m; 659 } 660 661 /* 662 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 663 */ 664 665 /* Sync the DMA map. */ 666 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 667 BUS_DMASYNC_PREWRITE); 668 669 /* 670 * Initialize the transmit descriptors. 671 */ 672 for (nexttx = sc->sc_txnext, seg = 0; 673 seg < dmamap->dm_nsegs; 674 seg++, nexttx = AE_NEXTTX(nexttx)) { 675 /* 676 * If this is the first descriptor we're 677 * enqueueing, don't set the OWN bit just 678 * yet. That could cause a race condition. 679 * We'll do it below. 680 */ 681 sc->sc_txdescs[nexttx].ad_status = 682 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 683 sc->sc_txdescs[nexttx].ad_bufaddr1 = 684 dmamap->dm_segs[seg].ds_addr; 685 sc->sc_txdescs[nexttx].ad_ctl = 686 (dmamap->dm_segs[seg].ds_len << 687 ADCTL_SIZE1_SHIFT) | 688 (nexttx == (AE_NTXDESC - 1) ? 689 ADCTL_ER : 0); 690 lasttx = nexttx; 691 } 692 693 KASSERT(lasttx != -1); 694 695 /* Set `first segment' and `last segment' appropriately. */ 696 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 697 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 698 699 #ifdef AE_DEBUG 700 if (ifp->if_flags & IFF_DEBUG) { 701 printf(" txsoft %p transmit chain:\n", txs); 702 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 703 printf(" descriptor %d:\n", seg); 704 printf(" ad_status: 0x%08x\n", 705 sc->sc_txdescs[seg].ad_status); 706 printf(" ad_ctl: 0x%08x\n", 707 sc->sc_txdescs[seg].ad_ctl); 708 printf(" ad_bufaddr1: 0x%08x\n", 709 sc->sc_txdescs[seg].ad_bufaddr1); 710 printf(" ad_bufaddr2: 0x%08x\n", 711 sc->sc_txdescs[seg].ad_bufaddr2); 712 if (seg == lasttx) 713 break; 714 } 715 } 716 #endif 717 718 /* Sync the descriptors we're using. */ 719 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 720 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 721 722 /* 723 * Store a pointer to the packet so we can free it later, 724 * and remember what txdirty will be once the packet is 725 * done. 726 */ 727 txs->txs_mbuf = m0; 728 txs->txs_firstdesc = sc->sc_txnext; 729 txs->txs_lastdesc = lasttx; 730 txs->txs_ndescs = dmamap->dm_nsegs; 731 732 /* Advance the tx pointer. */ 733 sc->sc_txfree -= dmamap->dm_nsegs; 734 sc->sc_txnext = nexttx; 735 736 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 737 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 738 739 last_txs = txs; 740 741 #if NBPFILTER > 0 742 /* 743 * Pass the packet to any BPF listeners. 744 */ 745 if (ifp->if_bpf) 746 bpf_mtap(ifp->if_bpf, m0); 747 #endif /* NBPFILTER > 0 */ 748 } 749 750 if (txs == NULL || sc->sc_txfree == 0) { 751 /* No more slots left; notify upper layer. */ 752 ifp->if_flags |= IFF_OACTIVE; 753 } 754 755 if (sc->sc_txfree != ofree) { 756 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 757 sc->sc_dev.dv_xname, lasttx, firsttx)); 758 /* 759 * Cause a transmit interrupt to happen on the 760 * last packet we enqueued. 761 */ 762 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 763 AE_CDTXSYNC(sc, lasttx, 1, 764 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 765 766 /* 767 * The entire packet chain is set up. Give the 768 * first descriptor to the chip now. 769 */ 770 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 771 AE_CDTXSYNC(sc, firsttx, 1, 772 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 773 774 /* Wake up the transmitter. */ 775 /* XXX USE AUTOPOLLING? */ 776 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 777 AE_BARRIER(sc); 778 779 /* Set a watchdog timer in case the chip flakes out. */ 780 ifp->if_timer = 5; 781 } 782 } 783 784 /* 785 * ae_watchdog: [ifnet interface function] 786 * 787 * Watchdog timer handler. 788 */ 789 static void 790 ae_watchdog(struct ifnet *ifp) 791 { 792 struct ae_softc *sc = ifp->if_softc; 793 int doing_transmit; 794 795 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 796 797 if (doing_transmit) { 798 printf("%s: transmit timeout\n", sc->sc_dev.dv_xname); 799 ifp->if_oerrors++; 800 } 801 else 802 printf("%s: spurious watchdog timeout\n", sc->sc_dev.dv_xname); 803 804 (void) ae_init(ifp); 805 806 /* Try to get more packets going. */ 807 ae_start(ifp); 808 } 809 810 /* If the interface is up and running, only modify the receive 811 * filter when changing to/from promiscuous mode. Otherwise return 812 * ENETRESET so that ether_ioctl will reset the chip. 813 */ 814 static int 815 ae_ifflags_cb(struct ethercom *ec) 816 { 817 struct ifnet *ifp = &ec->ec_if; 818 struct ae_softc *sc = ifp->if_softc; 819 int change = ifp->if_flags ^ sc->sc_if_flags; 820 821 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 822 return ENETRESET; 823 else if ((change & IFF_PROMISC) != 0) 824 ae_filter_setup(sc); 825 return 0; 826 } 827 828 /* 829 * ae_ioctl: [ifnet interface function] 830 * 831 * Handle control requests from the operator. 832 */ 833 static int 834 ae_ioctl(struct ifnet *ifp, u_long cmd, void *data) 835 { 836 struct ae_softc *sc = ifp->if_softc; 837 int s, error; 838 839 s = splnet(); 840 841 error = ether_ioctl(ifp, cmd, data); 842 if (error == ENETRESET) { 843 if (ifp->if_flags & IFF_RUNNING) { 844 /* 845 * Multicast list has changed. Set the 846 * hardware filter accordingly. 847 */ 848 ae_filter_setup(sc); 849 } 850 error = 0; 851 } 852 853 /* Try to get more packets going. */ 854 if (AE_IS_ENABLED(sc)) 855 ae_start(ifp); 856 857 sc->sc_if_flags = ifp->if_flags; 858 splx(s); 859 return (error); 860 } 861 862 /* 863 * ae_intr: 864 * 865 * Interrupt service routine. 866 */ 867 int 868 ae_intr(void *arg) 869 { 870 struct ae_softc *sc = arg; 871 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 872 u_int32_t status, rxstatus, txstatus; 873 int handled = 0, txthresh; 874 875 DPRINTF(sc, ("%s: ae_intr\n", sc->sc_dev.dv_xname)); 876 877 #ifdef DEBUG 878 if (AE_IS_ENABLED(sc) == 0) 879 panic("%s: ae_intr: not enabled", sc->sc_dev.dv_xname); 880 #endif 881 882 /* 883 * If the interface isn't running, the interrupt couldn't 884 * possibly have come from us. 885 */ 886 if ((ifp->if_flags & IFF_RUNNING) == 0 || 887 !device_is_active(&sc->sc_dev)) { 888 printf("spurious?!?\n"); 889 return (0); 890 } 891 892 for (;;) { 893 status = AE_READ(sc, CSR_STATUS); 894 if (status) { 895 AE_WRITE(sc, CSR_STATUS, status); 896 AE_BARRIER(sc); 897 } 898 899 if ((status & sc->sc_inten) == 0) 900 break; 901 902 handled = 1; 903 904 rxstatus = status & sc->sc_rxint_mask; 905 txstatus = status & sc->sc_txint_mask; 906 907 if (rxstatus) { 908 /* Grab new any new packets. */ 909 ae_rxintr(sc); 910 911 if (rxstatus & STATUS_RU) { 912 printf("%s: receive ring overrun\n", 913 sc->sc_dev.dv_xname); 914 /* Get the receive process going again. */ 915 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 916 AE_BARRIER(sc); 917 break; 918 } 919 } 920 921 if (txstatus) { 922 /* Sweep up transmit descriptors. */ 923 ae_txintr(sc); 924 925 if (txstatus & STATUS_TJT) 926 printf("%s: transmit jabber timeout\n", 927 sc->sc_dev.dv_xname); 928 929 if (txstatus & STATUS_UNF) { 930 /* 931 * Increase our transmit threshold if 932 * another is available. 933 */ 934 txthresh = sc->sc_txthresh + 1; 935 if (ae_txthresh[txthresh].txth_name != NULL) { 936 uint32_t opmode; 937 /* Idle the transmit process. */ 938 opmode = AE_READ(sc, CSR_OPMODE); 939 ae_idle(sc, OPMODE_ST); 940 941 sc->sc_txthresh = txthresh; 942 opmode &= 943 ~(OPMODE_TR|OPMODE_SF); 944 opmode |= 945 ae_txthresh[txthresh].txth_opmode; 946 printf("%s: transmit underrun; new " 947 "threshold: %s\n", 948 sc->sc_dev.dv_xname, 949 ae_txthresh[txthresh].txth_name); 950 951 /* 952 * Set the new threshold and restart 953 * the transmit process. 954 */ 955 AE_WRITE(sc, CSR_OPMODE, opmode); 956 AE_BARRIER(sc); 957 } 958 /* 959 * XXX Log every Nth underrun from 960 * XXX now on? 961 */ 962 } 963 } 964 965 if (status & (STATUS_TPS|STATUS_RPS)) { 966 if (status & STATUS_TPS) 967 printf("%s: transmit process stopped\n", 968 sc->sc_dev.dv_xname); 969 if (status & STATUS_RPS) 970 printf("%s: receive process stopped\n", 971 sc->sc_dev.dv_xname); 972 (void) ae_init(ifp); 973 break; 974 } 975 976 if (status & STATUS_SE) { 977 const char *str; 978 979 if (status & STATUS_TX_ABORT) 980 str = "tx abort"; 981 else if (status & STATUS_RX_ABORT) 982 str = "rx abort"; 983 else 984 str = "unknown error"; 985 986 printf("%s: fatal system error: %s\n", 987 sc->sc_dev.dv_xname, str); 988 (void) ae_init(ifp); 989 break; 990 } 991 992 /* 993 * Not handled: 994 * 995 * Transmit buffer unavailable -- normal 996 * condition, nothing to do, really. 997 * 998 * General purpose timer experied -- we don't 999 * use the general purpose timer. 1000 * 1001 * Early receive interrupt -- not available on 1002 * all chips, we just use RI. We also only 1003 * use single-segment receive DMA, so this 1004 * is mostly useless. 1005 */ 1006 } 1007 1008 /* Try to get more packets going. */ 1009 ae_start(ifp); 1010 1011 #if NRND > 0 1012 if (handled) 1013 rnd_add_uint32(&sc->sc_rnd_source, status); 1014 #endif 1015 return (handled); 1016 } 1017 1018 /* 1019 * ae_rxintr: 1020 * 1021 * Helper; handle receive interrupts. 1022 */ 1023 static void 1024 ae_rxintr(struct ae_softc *sc) 1025 { 1026 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1027 struct ether_header *eh; 1028 struct ae_rxsoft *rxs; 1029 struct mbuf *m; 1030 u_int32_t rxstat; 1031 int i, len; 1032 1033 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1034 rxs = &sc->sc_rxsoft[i]; 1035 1036 AE_CDRXSYNC(sc, i, 1037 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1038 1039 rxstat = sc->sc_rxdescs[i].ad_status; 1040 1041 if (rxstat & ADSTAT_OWN) { 1042 /* 1043 * We have processed all of the receive buffers. 1044 */ 1045 break; 1046 } 1047 1048 /* 1049 * If any collisions were seen on the wire, count one. 1050 */ 1051 if (rxstat & ADSTAT_Rx_CS) 1052 ifp->if_collisions++; 1053 1054 /* 1055 * If an error occurred, update stats, clear the status 1056 * word, and leave the packet buffer in place. It will 1057 * simply be reused the next time the ring comes around. 1058 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1059 * error. 1060 */ 1061 if (rxstat & ADSTAT_ES && 1062 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1063 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1064 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1065 #define PRINTERR(bit, str) \ 1066 if (rxstat & (bit)) \ 1067 printf("%s: receive error: %s\n", \ 1068 sc->sc_dev.dv_xname, str) 1069 ifp->if_ierrors++; 1070 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1071 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1072 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1073 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1074 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1075 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1076 #undef PRINTERR 1077 AE_INIT_RXDESC(sc, i); 1078 continue; 1079 } 1080 1081 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1082 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1083 1084 /* 1085 * No errors; receive the packet. Note the chip 1086 * includes the CRC with every packet. 1087 */ 1088 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1089 1090 /* 1091 * XXX: the Atheros part can align on half words. what 1092 * is the performance implication of this? Probably 1093 * minimal, and we should use it... 1094 */ 1095 #ifdef __NO_STRICT_ALIGNMENT 1096 /* 1097 * Allocate a new mbuf cluster. If that fails, we are 1098 * out of memory, and must drop the packet and recycle 1099 * the buffer that's already attached to this descriptor. 1100 */ 1101 m = rxs->rxs_mbuf; 1102 if (ae_add_rxbuf(sc, i) != 0) { 1103 ifp->if_ierrors++; 1104 AE_INIT_RXDESC(sc, i); 1105 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1106 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1107 continue; 1108 } 1109 #else 1110 /* 1111 * The chip's receive buffers must be 4-byte aligned. 1112 * But this means that the data after the Ethernet header 1113 * is misaligned. We must allocate a new buffer and 1114 * copy the data, shifted forward 2 bytes. 1115 */ 1116 MGETHDR(m, M_DONTWAIT, MT_DATA); 1117 if (m == NULL) { 1118 dropit: 1119 ifp->if_ierrors++; 1120 AE_INIT_RXDESC(sc, i); 1121 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1122 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1123 continue; 1124 } 1125 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1126 if (len > (MHLEN - 2)) { 1127 MCLGET(m, M_DONTWAIT); 1128 if ((m->m_flags & M_EXT) == 0) { 1129 m_freem(m); 1130 goto dropit; 1131 } 1132 } 1133 m->m_data += 2; 1134 1135 /* 1136 * Note that we use clusters for incoming frames, so the 1137 * buffer is virtually contiguous. 1138 */ 1139 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 1140 1141 /* Allow the receive descriptor to continue using its mbuf. */ 1142 AE_INIT_RXDESC(sc, i); 1143 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1144 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1145 #endif /* __NO_STRICT_ALIGNMENT */ 1146 1147 ifp->if_ipackets++; 1148 eh = mtod(m, struct ether_header *); 1149 m->m_pkthdr.rcvif = ifp; 1150 m->m_pkthdr.len = m->m_len = len; 1151 1152 #if NBPFILTER > 0 1153 /* 1154 * Pass this up to any BPF listeners, but only 1155 * pass it up the stack if its for us. 1156 */ 1157 if (ifp->if_bpf) 1158 bpf_mtap(ifp->if_bpf, m); 1159 #endif /* NBPFILTER > 0 */ 1160 1161 /* Pass it on. */ 1162 (*ifp->if_input)(ifp, m); 1163 } 1164 1165 /* Update the receive pointer. */ 1166 sc->sc_rxptr = i; 1167 } 1168 1169 /* 1170 * ae_txintr: 1171 * 1172 * Helper; handle transmit interrupts. 1173 */ 1174 static void 1175 ae_txintr(struct ae_softc *sc) 1176 { 1177 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1178 struct ae_txsoft *txs; 1179 u_int32_t txstat; 1180 1181 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1182 sc->sc_dev.dv_xname, sc->sc_flags)); 1183 1184 ifp->if_flags &= ~IFF_OACTIVE; 1185 1186 /* 1187 * Go through our Tx list and free mbufs for those 1188 * frames that have been transmitted. 1189 */ 1190 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1191 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1192 txs->txs_ndescs, 1193 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1194 1195 #ifdef AE_DEBUG 1196 if (ifp->if_flags & IFF_DEBUG) { 1197 int i; 1198 printf(" txsoft %p transmit chain:\n", txs); 1199 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1200 printf(" descriptor %d:\n", i); 1201 printf(" ad_status: 0x%08x\n", 1202 sc->sc_txdescs[i].ad_status); 1203 printf(" ad_ctl: 0x%08x\n", 1204 sc->sc_txdescs[i].ad_ctl); 1205 printf(" ad_bufaddr1: 0x%08x\n", 1206 sc->sc_txdescs[i].ad_bufaddr1); 1207 printf(" ad_bufaddr2: 0x%08x\n", 1208 sc->sc_txdescs[i].ad_bufaddr2); 1209 if (i == txs->txs_lastdesc) 1210 break; 1211 } 1212 } 1213 #endif 1214 1215 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1216 if (txstat & ADSTAT_OWN) 1217 break; 1218 1219 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1220 1221 sc->sc_txfree += txs->txs_ndescs; 1222 1223 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1224 0, txs->txs_dmamap->dm_mapsize, 1225 BUS_DMASYNC_POSTWRITE); 1226 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1227 m_freem(txs->txs_mbuf); 1228 txs->txs_mbuf = NULL; 1229 1230 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1231 1232 /* 1233 * Check for errors and collisions. 1234 */ 1235 #ifdef AE_STATS 1236 if (txstat & ADSTAT_Tx_UF) 1237 sc->sc_stats.ts_tx_uf++; 1238 if (txstat & ADSTAT_Tx_TO) 1239 sc->sc_stats.ts_tx_to++; 1240 if (txstat & ADSTAT_Tx_EC) 1241 sc->sc_stats.ts_tx_ec++; 1242 if (txstat & ADSTAT_Tx_LC) 1243 sc->sc_stats.ts_tx_lc++; 1244 #endif 1245 1246 if (txstat & (ADSTAT_Tx_UF|ADSTAT_Tx_TO)) 1247 ifp->if_oerrors++; 1248 1249 if (txstat & ADSTAT_Tx_EC) 1250 ifp->if_collisions += 16; 1251 else 1252 ifp->if_collisions += ADSTAT_Tx_COLLISIONS(txstat); 1253 if (txstat & ADSTAT_Tx_LC) 1254 ifp->if_collisions++; 1255 1256 ifp->if_opackets++; 1257 } 1258 1259 /* 1260 * If there are no more pending transmissions, cancel the watchdog 1261 * timer. 1262 */ 1263 if (txs == NULL) 1264 ifp->if_timer = 0; 1265 } 1266 1267 #ifdef AE_STATS 1268 void 1269 ae_print_stats(struct ae_softc *sc) 1270 { 1271 1272 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1273 sc->sc_dev.dv_xname, 1274 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1275 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1276 } 1277 #endif 1278 1279 /* 1280 * ae_reset: 1281 * 1282 * Perform a soft reset on the chip. 1283 */ 1284 void 1285 ae_reset(struct ae_softc *sc) 1286 { 1287 int i; 1288 1289 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1290 AE_BARRIER(sc); 1291 1292 /* 1293 * The chip doesn't take itself out of reset automatically. 1294 * We need to do so after 2us. 1295 */ 1296 delay(10); 1297 AE_WRITE(sc, CSR_BUSMODE, 0); 1298 AE_BARRIER(sc); 1299 1300 for (i = 0; i < 1000; i++) { 1301 /* 1302 * Wait a bit for the reset to complete before peeking 1303 * at the chip again. 1304 */ 1305 delay(10); 1306 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1307 break; 1308 } 1309 1310 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1311 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1312 1313 delay(1000); 1314 } 1315 1316 /* 1317 * ae_init: [ ifnet interface function ] 1318 * 1319 * Initialize the interface. Must be called at splnet(). 1320 */ 1321 static int 1322 ae_init(struct ifnet *ifp) 1323 { 1324 struct ae_softc *sc = ifp->if_softc; 1325 struct ae_txsoft *txs; 1326 struct ae_rxsoft *rxs; 1327 const uint8_t *enaddr; 1328 int i, error = 0; 1329 1330 if ((error = ae_enable(sc)) != 0) 1331 goto out; 1332 1333 /* 1334 * Cancel any pending I/O. 1335 */ 1336 ae_stop(ifp, 0); 1337 1338 /* 1339 * Reset the chip to a known state. 1340 */ 1341 ae_reset(sc); 1342 1343 /* 1344 * Initialize the BUSMODE register. 1345 */ 1346 AE_WRITE(sc, CSR_BUSMODE, 1347 /* XXX: not sure if this is a good thing or not... */ 1348 //BUSMODE_ALIGN_16B | 1349 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1350 AE_BARRIER(sc); 1351 1352 /* 1353 * Initialize the transmit descriptor ring. 1354 */ 1355 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1356 for (i = 0; i < AE_NTXDESC; i++) { 1357 sc->sc_txdescs[i].ad_ctl = 0; 1358 sc->sc_txdescs[i].ad_bufaddr2 = 1359 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1360 } 1361 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1362 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1363 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1364 sc->sc_txfree = AE_NTXDESC; 1365 sc->sc_txnext = 0; 1366 1367 /* 1368 * Initialize the transmit job descriptors. 1369 */ 1370 SIMPLEQ_INIT(&sc->sc_txfreeq); 1371 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1372 for (i = 0; i < AE_TXQUEUELEN; i++) { 1373 txs = &sc->sc_txsoft[i]; 1374 txs->txs_mbuf = NULL; 1375 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1376 } 1377 1378 /* 1379 * Initialize the receive descriptor and receive job 1380 * descriptor rings. 1381 */ 1382 for (i = 0; i < AE_NRXDESC; i++) { 1383 rxs = &sc->sc_rxsoft[i]; 1384 if (rxs->rxs_mbuf == NULL) { 1385 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1386 printf("%s: unable to allocate or map rx " 1387 "buffer %d, error = %d\n", 1388 sc->sc_dev.dv_xname, i, error); 1389 /* 1390 * XXX Should attempt to run with fewer receive 1391 * XXX buffers instead of just failing. 1392 */ 1393 ae_rxdrain(sc); 1394 goto out; 1395 } 1396 } else 1397 AE_INIT_RXDESC(sc, i); 1398 } 1399 sc->sc_rxptr = 0; 1400 1401 /* 1402 * Initialize the interrupt mask and enable interrupts. 1403 */ 1404 /* normal interrupts */ 1405 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1406 1407 /* abnormal interrupts */ 1408 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1409 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1410 1411 sc->sc_rxint_mask = STATUS_RI|STATUS_RU; 1412 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT; 1413 1414 sc->sc_rxint_mask &= sc->sc_inten; 1415 sc->sc_txint_mask &= sc->sc_inten; 1416 1417 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1418 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1419 1420 /* 1421 * Give the transmit and receive rings to the chip. 1422 */ 1423 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1424 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1425 AE_BARRIER(sc); 1426 1427 /* 1428 * Set the station address. 1429 */ 1430 enaddr = CLLADDR(ifp->if_sadl); 1431 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1432 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1433 enaddr[1] << 8 | enaddr[0]); 1434 AE_BARRIER(sc); 1435 1436 /* 1437 * Set the receive filter. This will start the transmit and 1438 * receive processes. 1439 */ 1440 ae_filter_setup(sc); 1441 1442 /* 1443 * Set the current media. 1444 */ 1445 if ((error = ether_mediachange(ifp)) != 0) 1446 goto out; 1447 1448 /* 1449 * Start the mac. 1450 */ 1451 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1452 AE_BARRIER(sc); 1453 1454 /* 1455 * Write out the opmode. 1456 */ 1457 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1458 ae_txthresh[sc->sc_txthresh].txth_opmode); 1459 /* 1460 * Start the receive process. 1461 */ 1462 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1463 AE_BARRIER(sc); 1464 1465 if (sc->sc_tick != NULL) { 1466 /* Start the one second clock. */ 1467 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1468 } 1469 1470 /* 1471 * Note that the interface is now running. 1472 */ 1473 ifp->if_flags |= IFF_RUNNING; 1474 ifp->if_flags &= ~IFF_OACTIVE; 1475 sc->sc_if_flags = ifp->if_flags; 1476 1477 out: 1478 if (error) { 1479 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1480 ifp->if_timer = 0; 1481 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1482 } 1483 return (error); 1484 } 1485 1486 /* 1487 * ae_enable: 1488 * 1489 * Enable the chip. 1490 */ 1491 static int 1492 ae_enable(struct ae_softc *sc) 1493 { 1494 1495 if (AE_IS_ENABLED(sc) == 0) { 1496 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1497 ae_intr, sc); 1498 if (sc->sc_ih == NULL) { 1499 printf("%s: unable to establish interrupt\n", 1500 sc->sc_dev.dv_xname); 1501 return (EIO); 1502 } 1503 sc->sc_flags |= AE_ENABLED; 1504 } 1505 return (0); 1506 } 1507 1508 /* 1509 * ae_disable: 1510 * 1511 * Disable the chip. 1512 */ 1513 static void 1514 ae_disable(struct ae_softc *sc) 1515 { 1516 1517 if (AE_IS_ENABLED(sc)) { 1518 arbus_intr_disestablish(sc->sc_ih); 1519 sc->sc_flags &= ~AE_ENABLED; 1520 } 1521 } 1522 1523 /* 1524 * ae_power: 1525 * 1526 * Power management (suspend/resume) hook. 1527 */ 1528 static void 1529 ae_power(int why, void *arg) 1530 { 1531 struct ae_softc *sc = arg; 1532 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1533 int s; 1534 1535 printf("power called: %d, %x\n", why, (uint32_t)arg); 1536 s = splnet(); 1537 switch (why) { 1538 case PWR_STANDBY: 1539 /* do nothing! */ 1540 break; 1541 case PWR_SUSPEND: 1542 ae_stop(ifp, 0); 1543 ae_disable(sc); 1544 break; 1545 case PWR_RESUME: 1546 if (ifp->if_flags & IFF_UP) { 1547 ae_enable(sc); 1548 ae_init(ifp); 1549 } 1550 break; 1551 case PWR_SOFTSUSPEND: 1552 case PWR_SOFTSTANDBY: 1553 case PWR_SOFTRESUME: 1554 break; 1555 } 1556 splx(s); 1557 } 1558 1559 /* 1560 * ae_rxdrain: 1561 * 1562 * Drain the receive queue. 1563 */ 1564 static void 1565 ae_rxdrain(struct ae_softc *sc) 1566 { 1567 struct ae_rxsoft *rxs; 1568 int i; 1569 1570 for (i = 0; i < AE_NRXDESC; i++) { 1571 rxs = &sc->sc_rxsoft[i]; 1572 if (rxs->rxs_mbuf != NULL) { 1573 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1574 m_freem(rxs->rxs_mbuf); 1575 rxs->rxs_mbuf = NULL; 1576 } 1577 } 1578 } 1579 1580 /* 1581 * ae_stop: [ ifnet interface function ] 1582 * 1583 * Stop transmission on the interface. 1584 */ 1585 static void 1586 ae_stop(struct ifnet *ifp, int disable) 1587 { 1588 struct ae_softc *sc = ifp->if_softc; 1589 struct ae_txsoft *txs; 1590 1591 if (sc->sc_tick != NULL) { 1592 /* Stop the one second clock. */ 1593 callout_stop(&sc->sc_tick_callout); 1594 } 1595 1596 /* Down the MII. */ 1597 mii_down(&sc->sc_mii); 1598 1599 /* Disable interrupts. */ 1600 AE_WRITE(sc, CSR_INTEN, 0); 1601 1602 /* Stop the transmit and receive processes. */ 1603 AE_WRITE(sc, CSR_OPMODE, 0); 1604 AE_WRITE(sc, CSR_RXLIST, 0); 1605 AE_WRITE(sc, CSR_TXLIST, 0); 1606 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1607 AE_BARRIER(sc); 1608 1609 /* 1610 * Release any queued transmit buffers. 1611 */ 1612 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1613 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1614 if (txs->txs_mbuf != NULL) { 1615 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1616 m_freem(txs->txs_mbuf); 1617 txs->txs_mbuf = NULL; 1618 } 1619 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1620 } 1621 1622 /* 1623 * Mark the interface down and cancel the watchdog timer. 1624 */ 1625 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1626 sc->sc_if_flags = ifp->if_flags; 1627 ifp->if_timer = 0; 1628 1629 if (disable) { 1630 ae_rxdrain(sc); 1631 ae_disable(sc); 1632 } 1633 1634 /* 1635 * Reset the chip (needed on some flavors to actually disable it). 1636 */ 1637 ae_reset(sc); 1638 } 1639 1640 /* 1641 * ae_add_rxbuf: 1642 * 1643 * Add a receive buffer to the indicated descriptor. 1644 */ 1645 static int 1646 ae_add_rxbuf(struct ae_softc *sc, int idx) 1647 { 1648 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1649 struct mbuf *m; 1650 int error; 1651 1652 MGETHDR(m, M_DONTWAIT, MT_DATA); 1653 if (m == NULL) 1654 return (ENOBUFS); 1655 1656 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1657 MCLGET(m, M_DONTWAIT); 1658 if ((m->m_flags & M_EXT) == 0) { 1659 m_freem(m); 1660 return (ENOBUFS); 1661 } 1662 1663 if (rxs->rxs_mbuf != NULL) 1664 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1665 1666 rxs->rxs_mbuf = m; 1667 1668 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1669 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1670 BUS_DMA_READ|BUS_DMA_NOWAIT); 1671 if (error) { 1672 printf("%s: can't load rx DMA map %d, error = %d\n", 1673 sc->sc_dev.dv_xname, idx, error); 1674 panic("ae_add_rxbuf"); /* XXX */ 1675 } 1676 1677 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1678 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1679 1680 AE_INIT_RXDESC(sc, idx); 1681 1682 return (0); 1683 } 1684 1685 /* 1686 * ae_filter_setup: 1687 * 1688 * Set the chip's receive filter. 1689 */ 1690 static void 1691 ae_filter_setup(struct ae_softc *sc) 1692 { 1693 struct ethercom *ec = &sc->sc_ethercom; 1694 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1695 struct ether_multi *enm; 1696 struct ether_multistep step; 1697 uint32_t hash, mchash[2]; 1698 uint32_t macctl = 0; 1699 1700 /* 1701 * If the chip is running, we need to reset the interface, 1702 * and will revisit here (with IFF_RUNNING) clear. The 1703 * chip seems to really not like to have its multicast 1704 * filter programmed without a reset. 1705 */ 1706 if (ifp->if_flags & IFF_RUNNING) { 1707 (void) ae_init(ifp); 1708 return; 1709 } 1710 1711 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1712 sc->sc_dev.dv_xname, sc->sc_flags)); 1713 1714 macctl = AE_READ(sc, CSR_MACCTL); 1715 macctl &= ~(MACCTL_PR | MACCTL_PM); 1716 macctl |= MACCTL_HASH; 1717 macctl |= MACCTL_HBD; 1718 macctl |= MACCTL_PR; 1719 1720 if (ifp->if_flags & IFF_PROMISC) { 1721 macctl |= MACCTL_PR; 1722 goto allmulti; 1723 } 1724 1725 mchash[0] = mchash[1] = 0; 1726 1727 ETHER_FIRST_MULTI(step, ec, enm); 1728 while (enm != NULL) { 1729 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1730 /* 1731 * We must listen to a range of multicast addresses. 1732 * For now, just accept all multicasts, rather than 1733 * trying to set only those filter bits needed to match 1734 * the range. (At this time, the only use of address 1735 * ranges is for IP multicast routing, for which the 1736 * range is big enough to require all bits set.) 1737 */ 1738 goto allmulti; 1739 } 1740 1741 /* Verify whether we use big or little endian hashes */ 1742 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1743 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1744 ETHER_NEXT_MULTI(step, enm); 1745 } 1746 ifp->if_flags &= ~IFF_ALLMULTI; 1747 goto setit; 1748 1749 allmulti: 1750 ifp->if_flags |= IFF_ALLMULTI; 1751 mchash[0] = mchash[1] = 0xffffffff; 1752 macctl |= MACCTL_PM; 1753 1754 setit: 1755 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1756 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1757 1758 AE_WRITE(sc, CSR_MACCTL, macctl); 1759 AE_BARRIER(sc); 1760 1761 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1762 sc->sc_dev.dv_xname, macctl)); 1763 } 1764 1765 /* 1766 * ae_idle: 1767 * 1768 * Cause the transmit and/or receive processes to go idle. 1769 */ 1770 void 1771 ae_idle(struct ae_softc *sc, u_int32_t bits) 1772 { 1773 static const char * const txstate_names[] = { 1774 "STOPPED", 1775 "RUNNING - FETCH", 1776 "RUNNING - WAIT", 1777 "RUNNING - READING", 1778 "-- RESERVED --", 1779 "RUNNING - SETUP", 1780 "SUSPENDED", 1781 "RUNNING - CLOSE", 1782 }; 1783 static const char * const rxstate_names[] = { 1784 "STOPPED", 1785 "RUNNING - FETCH", 1786 "RUNNING - CHECK", 1787 "RUNNING - WAIT", 1788 "SUSPENDED", 1789 "RUNNING - CLOSE", 1790 "RUNNING - FLUSH", 1791 "RUNNING - QUEUE", 1792 }; 1793 1794 u_int32_t csr, ackmask = 0; 1795 int i; 1796 1797 if (bits & OPMODE_ST) 1798 ackmask |= STATUS_TPS; 1799 1800 if (bits & OPMODE_SR) 1801 ackmask |= STATUS_RPS; 1802 1803 AE_CLR(sc, CSR_OPMODE, bits); 1804 1805 for (i = 0; i < 1000; i++) { 1806 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1807 break; 1808 delay(10); 1809 } 1810 1811 csr = AE_READ(sc, CSR_STATUS); 1812 if ((csr & ackmask) != ackmask) { 1813 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1814 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1815 printf("%s: transmit process failed to idle: " 1816 "state %s\n", sc->sc_dev.dv_xname, 1817 txstate_names[(csr & STATUS_TS) >> 20]); 1818 } 1819 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1820 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1821 printf("%s: receive process failed to idle: " 1822 "state %s\n", sc->sc_dev.dv_xname, 1823 rxstate_names[(csr & STATUS_RS) >> 17]); 1824 } 1825 } 1826 } 1827 1828 /***************************************************************************** 1829 * Support functions for MII-attached media. 1830 *****************************************************************************/ 1831 1832 /* 1833 * ae_mii_tick: 1834 * 1835 * One second timer, used to tick the MII. 1836 */ 1837 static void 1838 ae_mii_tick(void *arg) 1839 { 1840 struct ae_softc *sc = arg; 1841 int s; 1842 1843 if (!device_is_active(&sc->sc_dev)) 1844 return; 1845 1846 s = splnet(); 1847 mii_tick(&sc->sc_mii); 1848 splx(s); 1849 1850 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1851 } 1852 1853 /* 1854 * ae_mii_statchg: [mii interface function] 1855 * 1856 * Callback from PHY when media changes. 1857 */ 1858 static void 1859 ae_mii_statchg(device_t self) 1860 { 1861 struct ae_softc *sc = device_private(self); 1862 uint32_t macctl, flowc; 1863 1864 //opmode = AE_READ(sc, CSR_OPMODE); 1865 macctl = AE_READ(sc, CSR_MACCTL); 1866 1867 /* XXX: do we need to do this? */ 1868 /* Idle the transmit and receive processes. */ 1869 //ae_idle(sc, OPMODE_ST|OPMODE_SR); 1870 1871 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1872 flowc = FLOWC_FCE; 1873 macctl &= ~MACCTL_DRO; 1874 macctl |= MACCTL_FDX; 1875 } else { 1876 flowc = 0; /* cannot do flow control in HDX */ 1877 macctl |= MACCTL_DRO; 1878 macctl &= ~MACCTL_FDX; 1879 } 1880 1881 AE_WRITE(sc, CSR_FLOWC, flowc); 1882 AE_WRITE(sc, CSR_MACCTL, macctl); 1883 1884 /* restore operational mode */ 1885 //AE_WRITE(sc, CSR_OPMODE, opmode); 1886 AE_BARRIER(sc); 1887 } 1888 1889 /* 1890 * ae_mii_readreg: 1891 * 1892 * Read a PHY register. 1893 */ 1894 static int 1895 ae_mii_readreg(device_t self, int phy, int reg) 1896 { 1897 struct ae_softc *sc = device_private(self); 1898 uint32_t addr; 1899 int i; 1900 1901 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1902 AE_WRITE(sc, CSR_MIIADDR, addr); 1903 AE_BARRIER(sc); 1904 for (i = 0; i < 100000000; i++) { 1905 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1906 break; 1907 } 1908 1909 return (AE_READ(sc, CSR_MIIDATA) & 0xffff); 1910 } 1911 1912 /* 1913 * ae_mii_writereg: 1914 * 1915 * Write a PHY register. 1916 */ 1917 static void 1918 ae_mii_writereg(device_t self, int phy, int reg, int val) 1919 { 1920 struct ae_softc *sc = device_private(self); 1921 uint32_t addr; 1922 int i; 1923 1924 /* write the data register */ 1925 AE_WRITE(sc, CSR_MIIDATA, val); 1926 1927 /* write the address to latch it in */ 1928 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1929 MIIADDR_WRITE; 1930 AE_WRITE(sc, CSR_MIIADDR, addr); 1931 AE_BARRIER(sc); 1932 1933 for (i = 0; i < 100000000; i++) { 1934 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1935 break; 1936 } 1937 } 1938
Indexes created Fri Sep 26 08:10:20 GMT 2025