if_ae.c revision 1.18.4.1
1 /* $Id: if_ae.c,v 1.18.4.1 2010/05/30 05:16:58 rmind Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the onboard ethernet MAC found on the AR5312 74 * chip's AHB bus. 75 * 76 * This device is very simliar to the tulip in most regards, and 77 * the code is directly derived from NetBSD's tulip.c. However, it 78 * is different enough that it did not seem to be a good idea to 79 * add further complexity to the tulip driver, so we have our own. 80 * 81 * Also tulip has a lot of complexity in it for various parts/options 82 * that we don't need, and on these little boxes with only ~8MB RAM, we 83 * don't want any extra bloat. 84 */ 85 86 /* 87 * TODO: 88 * 89 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 90 * inbound packets on a half-word boundary, which would make life easier 91 * for TCP/IP. (Aligning IP headers on a word.) 92 * 93 * 2) There is stuff in original tulip to shut down the device when reacting 94 * to a a change in link status. Is that needed. 95 * 96 * 3) Test with variety of 10/100 HDX/FDX scenarios. 97 * 98 */ 99 100 #include <sys/cdefs.h> 101 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.18.4.1 2010/05/30 05:16:58 rmind Exp $"); 102 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/callout.h> 107 #include <sys/mbuf.h> 108 #include <sys/malloc.h> 109 #include <sys/kernel.h> 110 #include <sys/socket.h> 111 #include <sys/ioctl.h> 112 #include <sys/errno.h> 113 #include <sys/device.h> 114 115 #include <machine/endian.h> 116 117 #include <uvm/uvm_extern.h> 118 119 #include <net/if.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/if_ether.h> 123 124 #include <net/bpf.h> 125 126 #include <machine/bus.h> 127 #include <machine/intr.h> 128 129 #include <dev/mii/mii.h> 130 #include <dev/mii/miivar.h> 131 #include <dev/mii/mii_bitbang.h> 132 133 #include <mips/atheros/include/arbusvar.h> 134 #include <mips/atheros/dev/aereg.h> 135 #include <mips/atheros/dev/aevar.h> 136 137 static const struct { 138 u_int32_t txth_opmode; /* OPMODE bits */ 139 const char *txth_name; /* name of mode */ 140 } ae_txthresh[] = { 141 { OPMODE_TR_32, "32 words" }, 142 { OPMODE_TR_64, "64 words" }, 143 { OPMODE_TR_128, "128 words" }, 144 { OPMODE_TR_256, "256 words" }, 145 { OPMODE_SF, "store and forward mode" }, 146 { 0, NULL }, 147 }; 148 149 static int ae_match(device_t, struct cfdata *, void *); 150 static void ae_attach(device_t, device_t, void *); 151 static int ae_detach(device_t, int); 152 static int ae_activate(device_t, enum devact); 153 154 static int ae_ifflags_cb(struct ethercom *); 155 static void ae_reset(struct ae_softc *); 156 static void ae_idle(struct ae_softc *, u_int32_t); 157 158 static void ae_start(struct ifnet *); 159 static void ae_watchdog(struct ifnet *); 160 static int ae_ioctl(struct ifnet *, u_long, void *); 161 static int ae_init(struct ifnet *); 162 static void ae_stop(struct ifnet *, int); 163 164 static void ae_shutdown(void *); 165 166 static void ae_rxdrain(struct ae_softc *); 167 static int ae_add_rxbuf(struct ae_softc *, int); 168 169 static int ae_enable(struct ae_softc *); 170 static void ae_disable(struct ae_softc *); 171 static void ae_power(int, void *); 172 173 static void ae_filter_setup(struct ae_softc *); 174 175 static int ae_intr(void *); 176 static void ae_rxintr(struct ae_softc *); 177 static void ae_txintr(struct ae_softc *); 178 179 static void ae_mii_tick(void *); 180 static void ae_mii_statchg(device_t); 181 182 static int ae_mii_readreg(device_t, int, int); 183 static void ae_mii_writereg(device_t, int, int, int); 184 185 #ifdef AE_DEBUG 186 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 187 printf x 188 #else 189 #define DPRINTF(sc, x) /* nothing */ 190 #endif 191 192 #ifdef AE_STATS 193 static void ae_print_stats(struct ae_softc *); 194 #endif 195 196 CFATTACH_DECL(ae, sizeof(struct ae_softc), 197 ae_match, ae_attach, ae_detach, ae_activate); 198 199 /* 200 * ae_match: 201 * 202 * Check for a device match. 203 */ 204 int 205 ae_match(device_t parent, struct cfdata *cf, void *aux) 206 { 207 struct arbus_attach_args *aa = aux; 208 209 if (strcmp(aa->aa_name, cf->cf_name) == 0) 210 return 1; 211 212 return 0; 213 214 } 215 216 /* 217 * ae_attach: 218 * 219 * Attach an ae interface to the system. 220 */ 221 void 222 ae_attach(device_t parent, device_t self, void *aux) 223 { 224 const uint8_t *enaddr; 225 prop_data_t ea; 226 struct ae_softc *sc = device_private(self); 227 struct arbus_attach_args *aa = aux; 228 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 229 int i, error; 230 231 callout_init(&sc->sc_tick_callout, 0); 232 233 printf(": Atheros AR531X 10/100 Ethernet\n"); 234 235 /* 236 * Try to get MAC address. 237 */ 238 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-address"); 239 if (ea == NULL) { 240 printf("%s: unable to get mac-addr property\n", 241 sc->sc_dev.dv_xname); 242 return; 243 } 244 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 245 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 246 enaddr = prop_data_data_nocopy(ea); 247 248 /* Announce ourselves. */ 249 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 250 ether_sprintf(enaddr)); 251 252 sc->sc_cirq = aa->aa_cirq; 253 sc->sc_mirq = aa->aa_mirq; 254 sc->sc_st = aa->aa_bst; 255 sc->sc_dmat = aa->aa_dmat; 256 257 SIMPLEQ_INIT(&sc->sc_txfreeq); 258 SIMPLEQ_INIT(&sc->sc_txdirtyq); 259 260 /* 261 * Map registers. 262 */ 263 sc->sc_size = aa->aa_size; 264 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 265 &sc->sc_sh)) != 0) { 266 printf("%s: unable to map registers, error = %d\n", 267 sc->sc_dev.dv_xname, error); 268 goto fail_0; 269 } 270 271 /* 272 * Allocate the control data structures, and create and load the 273 * DMA map for it. 274 */ 275 if ((error = bus_dmamem_alloc(sc->sc_dmat, 276 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 277 1, &sc->sc_cdnseg, 0)) != 0) { 278 printf("%s: unable to allocate control data, error = %d\n", 279 sc->sc_dev.dv_xname, error); 280 goto fail_1; 281 } 282 283 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 284 sizeof(struct ae_control_data), (void **)&sc->sc_control_data, 285 BUS_DMA_COHERENT)) != 0) { 286 printf("%s: unable to map control data, error = %d\n", 287 sc->sc_dev.dv_xname, error); 288 goto fail_2; 289 } 290 291 if ((error = bus_dmamap_create(sc->sc_dmat, 292 sizeof(struct ae_control_data), 1, 293 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 294 printf("%s: unable to create control data DMA map, " 295 "error = %d\n", sc->sc_dev.dv_xname, error); 296 goto fail_3; 297 } 298 299 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 300 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 301 0)) != 0) { 302 printf("%s: unable to load control data DMA map, error = %d\n", 303 sc->sc_dev.dv_xname, error); 304 goto fail_4; 305 } 306 307 /* 308 * Create the transmit buffer DMA maps. 309 */ 310 for (i = 0; i < AE_TXQUEUELEN; i++) { 311 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 312 AE_NTXSEGS, MCLBYTES, 0, 0, 313 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 314 printf("%s: unable to create tx DMA map %d, " 315 "error = %d\n", sc->sc_dev.dv_xname, i, error); 316 goto fail_5; 317 } 318 } 319 320 /* 321 * Create the receive buffer DMA maps. 322 */ 323 for (i = 0; i < AE_NRXDESC; i++) { 324 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 325 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 326 printf("%s: unable to create rx DMA map %d, " 327 "error = %d\n", sc->sc_dev.dv_xname, i, error); 328 goto fail_6; 329 } 330 sc->sc_rxsoft[i].rxs_mbuf = NULL; 331 } 332 333 /* 334 * Reset the chip to a known state. 335 */ 336 ae_reset(sc); 337 338 /* 339 * From this point forward, the attachment cannot fail. A failure 340 * before this point releases all resources that may have been 341 * allocated. 342 */ 343 sc->sc_flags |= AE_ATTACHED; 344 345 /* 346 * Initialize our media structures. This may probe the MII, if 347 * present. 348 */ 349 sc->sc_mii.mii_ifp = ifp; 350 sc->sc_mii.mii_readreg = ae_mii_readreg; 351 sc->sc_mii.mii_writereg = ae_mii_writereg; 352 sc->sc_mii.mii_statchg = ae_mii_statchg; 353 sc->sc_ethercom.ec_mii = &sc->sc_mii; 354 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 355 ether_mediastatus); 356 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 357 MII_OFFSET_ANY, 0); 358 359 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 360 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 361 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 362 } else 363 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 364 365 sc->sc_tick = ae_mii_tick; 366 367 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 368 ifp->if_softc = sc; 369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 370 sc->sc_if_flags = ifp->if_flags; 371 ifp->if_ioctl = ae_ioctl; 372 ifp->if_start = ae_start; 373 ifp->if_watchdog = ae_watchdog; 374 ifp->if_init = ae_init; 375 ifp->if_stop = ae_stop; 376 IFQ_SET_READY(&ifp->if_snd); 377 378 /* 379 * We can support 802.1Q VLAN-sized frames. 380 */ 381 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 382 383 /* 384 * Attach the interface. 385 */ 386 if_attach(ifp); 387 ether_ifattach(ifp, enaddr); 388 ether_set_ifflags_cb(&sc->sc_ethercom, ae_ifflags_cb); 389 390 #if NRND > 0 391 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 392 RND_TYPE_NET, 0); 393 #endif 394 395 /* 396 * Make sure the interface is shutdown during reboot. 397 */ 398 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 399 if (sc->sc_sdhook == NULL) 400 printf("%s: WARNING: unable to establish shutdown hook\n", 401 sc->sc_dev.dv_xname); 402 403 /* 404 * Add a suspend hook to make sure we come back up after a 405 * resume. 406 */ 407 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 408 ae_power, sc); 409 if (sc->sc_powerhook == NULL) 410 printf("%s: WARNING: unable to establish power hook\n", 411 sc->sc_dev.dv_xname); 412 return; 413 414 /* 415 * Free any resources we've allocated during the failed attach 416 * attempt. Do this in reverse order and fall through. 417 */ 418 fail_6: 419 for (i = 0; i < AE_NRXDESC; i++) { 420 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 421 bus_dmamap_destroy(sc->sc_dmat, 422 sc->sc_rxsoft[i].rxs_dmamap); 423 } 424 fail_5: 425 for (i = 0; i < AE_TXQUEUELEN; i++) { 426 if (sc->sc_txsoft[i].txs_dmamap != NULL) 427 bus_dmamap_destroy(sc->sc_dmat, 428 sc->sc_txsoft[i].txs_dmamap); 429 } 430 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 431 fail_4: 432 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 433 fail_3: 434 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 435 sizeof(struct ae_control_data)); 436 fail_2: 437 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 438 fail_1: 439 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 440 fail_0: 441 return; 442 } 443 444 /* 445 * ae_activate: 446 * 447 * Handle device activation/deactivation requests. 448 */ 449 int 450 ae_activate(device_t self, enum devact act) 451 { 452 struct ae_softc *sc = device_private(self); 453 454 switch (act) { 455 case DVACT_DEACTIVATE: 456 if_deactivate(&sc->sc_ethercom.ec_if); 457 return 0; 458 default: 459 return EOPNOTSUPP; 460 } 461 } 462 463 /* 464 * ae_detach: 465 * 466 * Detach a device interface. 467 */ 468 int 469 ae_detach(device_t self, int flags) 470 { 471 struct ae_softc *sc = device_private(self); 472 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 473 struct ae_rxsoft *rxs; 474 struct ae_txsoft *txs; 475 int i; 476 477 /* 478 * Succeed now if there isn't any work to do. 479 */ 480 if ((sc->sc_flags & AE_ATTACHED) == 0) 481 return (0); 482 483 /* Unhook our tick handler. */ 484 if (sc->sc_tick) 485 callout_stop(&sc->sc_tick_callout); 486 487 /* Detach all PHYs */ 488 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 489 490 /* Delete all remaining media. */ 491 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 492 493 #if NRND > 0 494 rnd_detach_source(&sc->sc_rnd_source); 495 #endif 496 ether_ifdetach(ifp); 497 if_detach(ifp); 498 499 for (i = 0; i < AE_NRXDESC; i++) { 500 rxs = &sc->sc_rxsoft[i]; 501 if (rxs->rxs_mbuf != NULL) { 502 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 503 m_freem(rxs->rxs_mbuf); 504 rxs->rxs_mbuf = NULL; 505 } 506 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 507 } 508 for (i = 0; i < AE_TXQUEUELEN; i++) { 509 txs = &sc->sc_txsoft[i]; 510 if (txs->txs_mbuf != NULL) { 511 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 512 m_freem(txs->txs_mbuf); 513 txs->txs_mbuf = NULL; 514 } 515 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 516 } 517 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 518 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 519 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 520 sizeof(struct ae_control_data)); 521 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 522 523 shutdownhook_disestablish(sc->sc_sdhook); 524 powerhook_disestablish(sc->sc_powerhook); 525 526 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 527 528 529 return (0); 530 } 531 532 /* 533 * ae_shutdown: 534 * 535 * Make sure the interface is stopped at reboot time. 536 */ 537 static void 538 ae_shutdown(void *arg) 539 { 540 struct ae_softc *sc = arg; 541 542 ae_stop(&sc->sc_ethercom.ec_if, 1); 543 } 544 545 /* 546 * ae_start: [ifnet interface function] 547 * 548 * Start packet transmission on the interface. 549 */ 550 static void 551 ae_start(struct ifnet *ifp) 552 { 553 struct ae_softc *sc = ifp->if_softc; 554 struct mbuf *m0, *m; 555 struct ae_txsoft *txs, *last_txs = NULL; 556 bus_dmamap_t dmamap; 557 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 558 559 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 560 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 561 562 563 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 564 return; 565 566 /* 567 * Remember the previous number of free descriptors and 568 * the first descriptor we'll use. 569 */ 570 ofree = sc->sc_txfree; 571 firsttx = sc->sc_txnext; 572 573 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 574 sc->sc_dev.dv_xname, ofree, firsttx)); 575 576 /* 577 * Loop through the send queue, setting up transmit descriptors 578 * until we drain the queue, or use up all available transmit 579 * descriptors. 580 */ 581 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 582 sc->sc_txfree != 0) { 583 /* 584 * Grab a packet off the queue. 585 */ 586 IFQ_POLL(&ifp->if_snd, m0); 587 if (m0 == NULL) 588 break; 589 m = NULL; 590 591 dmamap = txs->txs_dmamap; 592 593 /* 594 * Load the DMA map. If this fails, the packet either 595 * didn't fit in the alloted number of segments, or we were 596 * short on resources. In this case, we'll copy and try 597 * again. 598 */ 599 if (((mtod(m0, uintptr_t) & 3) != 0) || 600 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 601 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 602 MGETHDR(m, M_DONTWAIT, MT_DATA); 603 if (m == NULL) { 604 printf("%s: unable to allocate Tx mbuf\n", 605 sc->sc_dev.dv_xname); 606 break; 607 } 608 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 609 if (m0->m_pkthdr.len > MHLEN) { 610 MCLGET(m, M_DONTWAIT); 611 if ((m->m_flags & M_EXT) == 0) { 612 printf("%s: unable to allocate Tx " 613 "cluster\n", sc->sc_dev.dv_xname); 614 m_freem(m); 615 break; 616 } 617 } 618 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 619 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 620 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 621 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 622 if (error) { 623 printf("%s: unable to load Tx buffer, " 624 "error = %d\n", sc->sc_dev.dv_xname, 625 error); 626 break; 627 } 628 } 629 630 /* 631 * Ensure we have enough descriptors free to describe 632 * the packet. 633 */ 634 if (dmamap->dm_nsegs > sc->sc_txfree) { 635 /* 636 * Not enough free descriptors to transmit this 637 * packet. We haven't committed to anything yet, 638 * so just unload the DMA map, put the packet 639 * back on the queue, and punt. Notify the upper 640 * layer that there are no more slots left. 641 * 642 * XXX We could allocate an mbuf and copy, but 643 * XXX it is worth it? 644 */ 645 ifp->if_flags |= IFF_OACTIVE; 646 bus_dmamap_unload(sc->sc_dmat, dmamap); 647 if (m != NULL) 648 m_freem(m); 649 break; 650 } 651 652 IFQ_DEQUEUE(&ifp->if_snd, m0); 653 if (m != NULL) { 654 m_freem(m0); 655 m0 = m; 656 } 657 658 /* 659 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 660 */ 661 662 /* Sync the DMA map. */ 663 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 664 BUS_DMASYNC_PREWRITE); 665 666 /* 667 * Initialize the transmit descriptors. 668 */ 669 for (nexttx = sc->sc_txnext, seg = 0; 670 seg < dmamap->dm_nsegs; 671 seg++, nexttx = AE_NEXTTX(nexttx)) { 672 /* 673 * If this is the first descriptor we're 674 * enqueueing, don't set the OWN bit just 675 * yet. That could cause a race condition. 676 * We'll do it below. 677 */ 678 sc->sc_txdescs[nexttx].ad_status = 679 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 680 sc->sc_txdescs[nexttx].ad_bufaddr1 = 681 dmamap->dm_segs[seg].ds_addr; 682 sc->sc_txdescs[nexttx].ad_ctl = 683 (dmamap->dm_segs[seg].ds_len << 684 ADCTL_SIZE1_SHIFT) | 685 (nexttx == (AE_NTXDESC - 1) ? 686 ADCTL_ER : 0); 687 lasttx = nexttx; 688 } 689 690 KASSERT(lasttx != -1); 691 692 /* Set `first segment' and `last segment' appropriately. */ 693 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 694 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 695 696 #ifdef AE_DEBUG 697 if (ifp->if_flags & IFF_DEBUG) { 698 printf(" txsoft %p transmit chain:\n", txs); 699 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 700 printf(" descriptor %d:\n", seg); 701 printf(" ad_status: 0x%08x\n", 702 sc->sc_txdescs[seg].ad_status); 703 printf(" ad_ctl: 0x%08x\n", 704 sc->sc_txdescs[seg].ad_ctl); 705 printf(" ad_bufaddr1: 0x%08x\n", 706 sc->sc_txdescs[seg].ad_bufaddr1); 707 printf(" ad_bufaddr2: 0x%08x\n", 708 sc->sc_txdescs[seg].ad_bufaddr2); 709 if (seg == lasttx) 710 break; 711 } 712 } 713 #endif 714 715 /* Sync the descriptors we're using. */ 716 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 717 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 718 719 /* 720 * Store a pointer to the packet so we can free it later, 721 * and remember what txdirty will be once the packet is 722 * done. 723 */ 724 txs->txs_mbuf = m0; 725 txs->txs_firstdesc = sc->sc_txnext; 726 txs->txs_lastdesc = lasttx; 727 txs->txs_ndescs = dmamap->dm_nsegs; 728 729 /* Advance the tx pointer. */ 730 sc->sc_txfree -= dmamap->dm_nsegs; 731 sc->sc_txnext = nexttx; 732 733 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 734 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 735 736 last_txs = txs; 737 738 /* 739 * Pass the packet to any BPF listeners. 740 */ 741 bpf_mtap(ifp, m0); 742 } 743 744 if (txs == NULL || sc->sc_txfree == 0) { 745 /* No more slots left; notify upper layer. */ 746 ifp->if_flags |= IFF_OACTIVE; 747 } 748 749 if (sc->sc_txfree != ofree) { 750 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 751 sc->sc_dev.dv_xname, lasttx, firsttx)); 752 /* 753 * Cause a transmit interrupt to happen on the 754 * last packet we enqueued. 755 */ 756 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 757 AE_CDTXSYNC(sc, lasttx, 1, 758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 759 760 /* 761 * The entire packet chain is set up. Give the 762 * first descriptor to the chip now. 763 */ 764 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 765 AE_CDTXSYNC(sc, firsttx, 1, 766 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 767 768 /* Wake up the transmitter. */ 769 /* XXX USE AUTOPOLLING? */ 770 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 771 AE_BARRIER(sc); 772 773 /* Set a watchdog timer in case the chip flakes out. */ 774 ifp->if_timer = 5; 775 } 776 } 777 778 /* 779 * ae_watchdog: [ifnet interface function] 780 * 781 * Watchdog timer handler. 782 */ 783 static void 784 ae_watchdog(struct ifnet *ifp) 785 { 786 struct ae_softc *sc = ifp->if_softc; 787 int doing_transmit; 788 789 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 790 791 if (doing_transmit) { 792 printf("%s: transmit timeout\n", sc->sc_dev.dv_xname); 793 ifp->if_oerrors++; 794 } 795 else 796 printf("%s: spurious watchdog timeout\n", sc->sc_dev.dv_xname); 797 798 (void) ae_init(ifp); 799 800 /* Try to get more packets going. */ 801 ae_start(ifp); 802 } 803 804 /* If the interface is up and running, only modify the receive 805 * filter when changing to/from promiscuous mode. Otherwise return 806 * ENETRESET so that ether_ioctl will reset the chip. 807 */ 808 static int 809 ae_ifflags_cb(struct ethercom *ec) 810 { 811 struct ifnet *ifp = &ec->ec_if; 812 struct ae_softc *sc = ifp->if_softc; 813 int change = ifp->if_flags ^ sc->sc_if_flags; 814 815 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 816 return ENETRESET; 817 else if ((change & IFF_PROMISC) != 0) 818 ae_filter_setup(sc); 819 return 0; 820 } 821 822 /* 823 * ae_ioctl: [ifnet interface function] 824 * 825 * Handle control requests from the operator. 826 */ 827 static int 828 ae_ioctl(struct ifnet *ifp, u_long cmd, void *data) 829 { 830 struct ae_softc *sc = ifp->if_softc; 831 int s, error; 832 833 s = splnet(); 834 835 error = ether_ioctl(ifp, cmd, data); 836 if (error == ENETRESET) { 837 if (ifp->if_flags & IFF_RUNNING) { 838 /* 839 * Multicast list has changed. Set the 840 * hardware filter accordingly. 841 */ 842 ae_filter_setup(sc); 843 } 844 error = 0; 845 } 846 847 /* Try to get more packets going. */ 848 if (AE_IS_ENABLED(sc)) 849 ae_start(ifp); 850 851 sc->sc_if_flags = ifp->if_flags; 852 splx(s); 853 return (error); 854 } 855 856 /* 857 * ae_intr: 858 * 859 * Interrupt service routine. 860 */ 861 int 862 ae_intr(void *arg) 863 { 864 struct ae_softc *sc = arg; 865 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 866 u_int32_t status, rxstatus, txstatus; 867 int handled = 0, txthresh; 868 869 DPRINTF(sc, ("%s: ae_intr\n", sc->sc_dev.dv_xname)); 870 871 #ifdef DEBUG 872 if (AE_IS_ENABLED(sc) == 0) 873 panic("%s: ae_intr: not enabled", sc->sc_dev.dv_xname); 874 #endif 875 876 /* 877 * If the interface isn't running, the interrupt couldn't 878 * possibly have come from us. 879 */ 880 if ((ifp->if_flags & IFF_RUNNING) == 0 || 881 !device_is_active(&sc->sc_dev)) { 882 printf("spurious?!?\n"); 883 return (0); 884 } 885 886 for (;;) { 887 status = AE_READ(sc, CSR_STATUS); 888 if (status) { 889 AE_WRITE(sc, CSR_STATUS, status); 890 AE_BARRIER(sc); 891 } 892 893 if ((status & sc->sc_inten) == 0) 894 break; 895 896 handled = 1; 897 898 rxstatus = status & sc->sc_rxint_mask; 899 txstatus = status & sc->sc_txint_mask; 900 901 if (rxstatus) { 902 /* Grab new any new packets. */ 903 ae_rxintr(sc); 904 905 if (rxstatus & STATUS_RU) { 906 printf("%s: receive ring overrun\n", 907 sc->sc_dev.dv_xname); 908 /* Get the receive process going again. */ 909 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 910 AE_BARRIER(sc); 911 break; 912 } 913 } 914 915 if (txstatus) { 916 /* Sweep up transmit descriptors. */ 917 ae_txintr(sc); 918 919 if (txstatus & STATUS_TJT) 920 printf("%s: transmit jabber timeout\n", 921 sc->sc_dev.dv_xname); 922 923 if (txstatus & STATUS_UNF) { 924 /* 925 * Increase our transmit threshold if 926 * another is available. 927 */ 928 txthresh = sc->sc_txthresh + 1; 929 if (ae_txthresh[txthresh].txth_name != NULL) { 930 uint32_t opmode; 931 /* Idle the transmit process. */ 932 opmode = AE_READ(sc, CSR_OPMODE); 933 ae_idle(sc, OPMODE_ST); 934 935 sc->sc_txthresh = txthresh; 936 opmode &= 937 ~(OPMODE_TR|OPMODE_SF); 938 opmode |= 939 ae_txthresh[txthresh].txth_opmode; 940 printf("%s: transmit underrun; new " 941 "threshold: %s\n", 942 sc->sc_dev.dv_xname, 943 ae_txthresh[txthresh].txth_name); 944 945 /* 946 * Set the new threshold and restart 947 * the transmit process. 948 */ 949 AE_WRITE(sc, CSR_OPMODE, opmode); 950 AE_BARRIER(sc); 951 } 952 /* 953 * XXX Log every Nth underrun from 954 * XXX now on? 955 */ 956 } 957 } 958 959 if (status & (STATUS_TPS|STATUS_RPS)) { 960 if (status & STATUS_TPS) 961 printf("%s: transmit process stopped\n", 962 sc->sc_dev.dv_xname); 963 if (status & STATUS_RPS) 964 printf("%s: receive process stopped\n", 965 sc->sc_dev.dv_xname); 966 (void) ae_init(ifp); 967 break; 968 } 969 970 if (status & STATUS_SE) { 971 const char *str; 972 973 if (status & STATUS_TX_ABORT) 974 str = "tx abort"; 975 else if (status & STATUS_RX_ABORT) 976 str = "rx abort"; 977 else 978 str = "unknown error"; 979 980 printf("%s: fatal system error: %s\n", 981 sc->sc_dev.dv_xname, str); 982 (void) ae_init(ifp); 983 break; 984 } 985 986 /* 987 * Not handled: 988 * 989 * Transmit buffer unavailable -- normal 990 * condition, nothing to do, really. 991 * 992 * General purpose timer experied -- we don't 993 * use the general purpose timer. 994 * 995 * Early receive interrupt -- not available on 996 * all chips, we just use RI. We also only 997 * use single-segment receive DMA, so this 998 * is mostly useless. 999 */ 1000 } 1001 1002 /* Try to get more packets going. */ 1003 ae_start(ifp); 1004 1005 #if NRND > 0 1006 if (handled) 1007 rnd_add_uint32(&sc->sc_rnd_source, status); 1008 #endif 1009 return (handled); 1010 } 1011 1012 /* 1013 * ae_rxintr: 1014 * 1015 * Helper; handle receive interrupts. 1016 */ 1017 static void 1018 ae_rxintr(struct ae_softc *sc) 1019 { 1020 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1021 struct ether_header *eh; 1022 struct ae_rxsoft *rxs; 1023 struct mbuf *m; 1024 u_int32_t rxstat; 1025 int i, len; 1026 1027 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1028 rxs = &sc->sc_rxsoft[i]; 1029 1030 AE_CDRXSYNC(sc, i, 1031 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1032 1033 rxstat = sc->sc_rxdescs[i].ad_status; 1034 1035 if (rxstat & ADSTAT_OWN) { 1036 /* 1037 * We have processed all of the receive buffers. 1038 */ 1039 break; 1040 } 1041 1042 /* 1043 * If any collisions were seen on the wire, count one. 1044 */ 1045 if (rxstat & ADSTAT_Rx_CS) 1046 ifp->if_collisions++; 1047 1048 /* 1049 * If an error occurred, update stats, clear the status 1050 * word, and leave the packet buffer in place. It will 1051 * simply be reused the next time the ring comes around. 1052 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1053 * error. 1054 */ 1055 if (rxstat & ADSTAT_ES && 1056 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1057 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1058 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1059 #define PRINTERR(bit, str) \ 1060 if (rxstat & (bit)) \ 1061 printf("%s: receive error: %s\n", \ 1062 sc->sc_dev.dv_xname, str) 1063 ifp->if_ierrors++; 1064 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1065 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1066 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1067 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1068 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1069 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1070 #undef PRINTERR 1071 AE_INIT_RXDESC(sc, i); 1072 continue; 1073 } 1074 1075 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1076 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1077 1078 /* 1079 * No errors; receive the packet. Note the chip 1080 * includes the CRC with every packet. 1081 */ 1082 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1083 1084 /* 1085 * XXX: the Atheros part can align on half words. what 1086 * is the performance implication of this? Probably 1087 * minimal, and we should use it... 1088 */ 1089 #ifdef __NO_STRICT_ALIGNMENT 1090 /* 1091 * Allocate a new mbuf cluster. If that fails, we are 1092 * out of memory, and must drop the packet and recycle 1093 * the buffer that's already attached to this descriptor. 1094 */ 1095 m = rxs->rxs_mbuf; 1096 if (ae_add_rxbuf(sc, i) != 0) { 1097 ifp->if_ierrors++; 1098 AE_INIT_RXDESC(sc, i); 1099 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1100 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1101 continue; 1102 } 1103 #else 1104 /* 1105 * The chip's receive buffers must be 4-byte aligned. 1106 * But this means that the data after the Ethernet header 1107 * is misaligned. We must allocate a new buffer and 1108 * copy the data, shifted forward 2 bytes. 1109 */ 1110 MGETHDR(m, M_DONTWAIT, MT_DATA); 1111 if (m == NULL) { 1112 dropit: 1113 ifp->if_ierrors++; 1114 AE_INIT_RXDESC(sc, i); 1115 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1116 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1117 continue; 1118 } 1119 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1120 if (len > (MHLEN - 2)) { 1121 MCLGET(m, M_DONTWAIT); 1122 if ((m->m_flags & M_EXT) == 0) { 1123 m_freem(m); 1124 goto dropit; 1125 } 1126 } 1127 m->m_data += 2; 1128 1129 /* 1130 * Note that we use clusters for incoming frames, so the 1131 * buffer is virtually contiguous. 1132 */ 1133 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 1134 1135 /* Allow the receive descriptor to continue using its mbuf. */ 1136 AE_INIT_RXDESC(sc, i); 1137 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1138 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1139 #endif /* __NO_STRICT_ALIGNMENT */ 1140 1141 ifp->if_ipackets++; 1142 eh = mtod(m, struct ether_header *); 1143 m->m_pkthdr.rcvif = ifp; 1144 m->m_pkthdr.len = m->m_len = len; 1145 1146 /* 1147 * Pass this up to any BPF listeners, but only 1148 * pass it up the stack if its for us. 1149 */ 1150 bpf_mtap(ifp, m); 1151 1152 /* Pass it on. */ 1153 (*ifp->if_input)(ifp, m); 1154 } 1155 1156 /* Update the receive pointer. */ 1157 sc->sc_rxptr = i; 1158 } 1159 1160 /* 1161 * ae_txintr: 1162 * 1163 * Helper; handle transmit interrupts. 1164 */ 1165 static void 1166 ae_txintr(struct ae_softc *sc) 1167 { 1168 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1169 struct ae_txsoft *txs; 1170 u_int32_t txstat; 1171 1172 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1173 sc->sc_dev.dv_xname, sc->sc_flags)); 1174 1175 ifp->if_flags &= ~IFF_OACTIVE; 1176 1177 /* 1178 * Go through our Tx list and free mbufs for those 1179 * frames that have been transmitted. 1180 */ 1181 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1182 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1183 txs->txs_ndescs, 1184 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1185 1186 #ifdef AE_DEBUG 1187 if (ifp->if_flags & IFF_DEBUG) { 1188 int i; 1189 printf(" txsoft %p transmit chain:\n", txs); 1190 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1191 printf(" descriptor %d:\n", i); 1192 printf(" ad_status: 0x%08x\n", 1193 sc->sc_txdescs[i].ad_status); 1194 printf(" ad_ctl: 0x%08x\n", 1195 sc->sc_txdescs[i].ad_ctl); 1196 printf(" ad_bufaddr1: 0x%08x\n", 1197 sc->sc_txdescs[i].ad_bufaddr1); 1198 printf(" ad_bufaddr2: 0x%08x\n", 1199 sc->sc_txdescs[i].ad_bufaddr2); 1200 if (i == txs->txs_lastdesc) 1201 break; 1202 } 1203 } 1204 #endif 1205 1206 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1207 if (txstat & ADSTAT_OWN) 1208 break; 1209 1210 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1211 1212 sc->sc_txfree += txs->txs_ndescs; 1213 1214 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1215 0, txs->txs_dmamap->dm_mapsize, 1216 BUS_DMASYNC_POSTWRITE); 1217 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1218 m_freem(txs->txs_mbuf); 1219 txs->txs_mbuf = NULL; 1220 1221 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1222 1223 /* 1224 * Check for errors and collisions. 1225 */ 1226 #ifdef AE_STATS 1227 if (txstat & ADSTAT_Tx_UF) 1228 sc->sc_stats.ts_tx_uf++; 1229 if (txstat & ADSTAT_Tx_TO) 1230 sc->sc_stats.ts_tx_to++; 1231 if (txstat & ADSTAT_Tx_EC) 1232 sc->sc_stats.ts_tx_ec++; 1233 if (txstat & ADSTAT_Tx_LC) 1234 sc->sc_stats.ts_tx_lc++; 1235 #endif 1236 1237 if (txstat & (ADSTAT_Tx_UF|ADSTAT_Tx_TO)) 1238 ifp->if_oerrors++; 1239 1240 if (txstat & ADSTAT_Tx_EC) 1241 ifp->if_collisions += 16; 1242 else 1243 ifp->if_collisions += ADSTAT_Tx_COLLISIONS(txstat); 1244 if (txstat & ADSTAT_Tx_LC) 1245 ifp->if_collisions++; 1246 1247 ifp->if_opackets++; 1248 } 1249 1250 /* 1251 * If there are no more pending transmissions, cancel the watchdog 1252 * timer. 1253 */ 1254 if (txs == NULL) 1255 ifp->if_timer = 0; 1256 } 1257 1258 #ifdef AE_STATS 1259 void 1260 ae_print_stats(struct ae_softc *sc) 1261 { 1262 1263 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1264 sc->sc_dev.dv_xname, 1265 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1266 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1267 } 1268 #endif 1269 1270 /* 1271 * ae_reset: 1272 * 1273 * Perform a soft reset on the chip. 1274 */ 1275 void 1276 ae_reset(struct ae_softc *sc) 1277 { 1278 int i; 1279 1280 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1281 AE_BARRIER(sc); 1282 1283 /* 1284 * The chip doesn't take itself out of reset automatically. 1285 * We need to do so after 2us. 1286 */ 1287 delay(10); 1288 AE_WRITE(sc, CSR_BUSMODE, 0); 1289 AE_BARRIER(sc); 1290 1291 for (i = 0; i < 1000; i++) { 1292 /* 1293 * Wait a bit for the reset to complete before peeking 1294 * at the chip again. 1295 */ 1296 delay(10); 1297 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1298 break; 1299 } 1300 1301 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1302 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1303 1304 delay(1000); 1305 } 1306 1307 /* 1308 * ae_init: [ ifnet interface function ] 1309 * 1310 * Initialize the interface. Must be called at splnet(). 1311 */ 1312 static int 1313 ae_init(struct ifnet *ifp) 1314 { 1315 struct ae_softc *sc = ifp->if_softc; 1316 struct ae_txsoft *txs; 1317 struct ae_rxsoft *rxs; 1318 const uint8_t *enaddr; 1319 int i, error = 0; 1320 1321 if ((error = ae_enable(sc)) != 0) 1322 goto out; 1323 1324 /* 1325 * Cancel any pending I/O. 1326 */ 1327 ae_stop(ifp, 0); 1328 1329 /* 1330 * Reset the chip to a known state. 1331 */ 1332 ae_reset(sc); 1333 1334 /* 1335 * Initialize the BUSMODE register. 1336 */ 1337 AE_WRITE(sc, CSR_BUSMODE, 1338 /* XXX: not sure if this is a good thing or not... */ 1339 //BUSMODE_ALIGN_16B | 1340 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1341 AE_BARRIER(sc); 1342 1343 /* 1344 * Initialize the transmit descriptor ring. 1345 */ 1346 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1347 for (i = 0; i < AE_NTXDESC; i++) { 1348 sc->sc_txdescs[i].ad_ctl = 0; 1349 sc->sc_txdescs[i].ad_bufaddr2 = 1350 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1351 } 1352 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1353 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1354 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1355 sc->sc_txfree = AE_NTXDESC; 1356 sc->sc_txnext = 0; 1357 1358 /* 1359 * Initialize the transmit job descriptors. 1360 */ 1361 SIMPLEQ_INIT(&sc->sc_txfreeq); 1362 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1363 for (i = 0; i < AE_TXQUEUELEN; i++) { 1364 txs = &sc->sc_txsoft[i]; 1365 txs->txs_mbuf = NULL; 1366 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1367 } 1368 1369 /* 1370 * Initialize the receive descriptor and receive job 1371 * descriptor rings. 1372 */ 1373 for (i = 0; i < AE_NRXDESC; i++) { 1374 rxs = &sc->sc_rxsoft[i]; 1375 if (rxs->rxs_mbuf == NULL) { 1376 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1377 printf("%s: unable to allocate or map rx " 1378 "buffer %d, error = %d\n", 1379 sc->sc_dev.dv_xname, i, error); 1380 /* 1381 * XXX Should attempt to run with fewer receive 1382 * XXX buffers instead of just failing. 1383 */ 1384 ae_rxdrain(sc); 1385 goto out; 1386 } 1387 } else 1388 AE_INIT_RXDESC(sc, i); 1389 } 1390 sc->sc_rxptr = 0; 1391 1392 /* 1393 * Initialize the interrupt mask and enable interrupts. 1394 */ 1395 /* normal interrupts */ 1396 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1397 1398 /* abnormal interrupts */ 1399 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1400 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1401 1402 sc->sc_rxint_mask = STATUS_RI|STATUS_RU; 1403 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT; 1404 1405 sc->sc_rxint_mask &= sc->sc_inten; 1406 sc->sc_txint_mask &= sc->sc_inten; 1407 1408 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1409 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1410 1411 /* 1412 * Give the transmit and receive rings to the chip. 1413 */ 1414 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1415 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1416 AE_BARRIER(sc); 1417 1418 /* 1419 * Set the station address. 1420 */ 1421 enaddr = CLLADDR(ifp->if_sadl); 1422 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1423 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1424 enaddr[1] << 8 | enaddr[0]); 1425 AE_BARRIER(sc); 1426 1427 /* 1428 * Set the receive filter. This will start the transmit and 1429 * receive processes. 1430 */ 1431 ae_filter_setup(sc); 1432 1433 /* 1434 * Set the current media. 1435 */ 1436 if ((error = ether_mediachange(ifp)) != 0) 1437 goto out; 1438 1439 /* 1440 * Start the mac. 1441 */ 1442 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1443 AE_BARRIER(sc); 1444 1445 /* 1446 * Write out the opmode. 1447 */ 1448 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1449 ae_txthresh[sc->sc_txthresh].txth_opmode); 1450 /* 1451 * Start the receive process. 1452 */ 1453 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1454 AE_BARRIER(sc); 1455 1456 if (sc->sc_tick != NULL) { 1457 /* Start the one second clock. */ 1458 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1459 } 1460 1461 /* 1462 * Note that the interface is now running. 1463 */ 1464 ifp->if_flags |= IFF_RUNNING; 1465 ifp->if_flags &= ~IFF_OACTIVE; 1466 sc->sc_if_flags = ifp->if_flags; 1467 1468 out: 1469 if (error) { 1470 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1471 ifp->if_timer = 0; 1472 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1473 } 1474 return (error); 1475 } 1476 1477 /* 1478 * ae_enable: 1479 * 1480 * Enable the chip. 1481 */ 1482 static int 1483 ae_enable(struct ae_softc *sc) 1484 { 1485 1486 if (AE_IS_ENABLED(sc) == 0) { 1487 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1488 ae_intr, sc); 1489 if (sc->sc_ih == NULL) { 1490 printf("%s: unable to establish interrupt\n", 1491 sc->sc_dev.dv_xname); 1492 return (EIO); 1493 } 1494 sc->sc_flags |= AE_ENABLED; 1495 } 1496 return (0); 1497 } 1498 1499 /* 1500 * ae_disable: 1501 * 1502 * Disable the chip. 1503 */ 1504 static void 1505 ae_disable(struct ae_softc *sc) 1506 { 1507 1508 if (AE_IS_ENABLED(sc)) { 1509 arbus_intr_disestablish(sc->sc_ih); 1510 sc->sc_flags &= ~AE_ENABLED; 1511 } 1512 } 1513 1514 /* 1515 * ae_power: 1516 * 1517 * Power management (suspend/resume) hook. 1518 */ 1519 static void 1520 ae_power(int why, void *arg) 1521 { 1522 struct ae_softc *sc = arg; 1523 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1524 int s; 1525 1526 printf("power called: %d, %x\n", why, (uint32_t)arg); 1527 s = splnet(); 1528 switch (why) { 1529 case PWR_STANDBY: 1530 /* do nothing! */ 1531 break; 1532 case PWR_SUSPEND: 1533 ae_stop(ifp, 0); 1534 ae_disable(sc); 1535 break; 1536 case PWR_RESUME: 1537 if (ifp->if_flags & IFF_UP) { 1538 ae_enable(sc); 1539 ae_init(ifp); 1540 } 1541 break; 1542 case PWR_SOFTSUSPEND: 1543 case PWR_SOFTSTANDBY: 1544 case PWR_SOFTRESUME: 1545 break; 1546 } 1547 splx(s); 1548 } 1549 1550 /* 1551 * ae_rxdrain: 1552 * 1553 * Drain the receive queue. 1554 */ 1555 static void 1556 ae_rxdrain(struct ae_softc *sc) 1557 { 1558 struct ae_rxsoft *rxs; 1559 int i; 1560 1561 for (i = 0; i < AE_NRXDESC; i++) { 1562 rxs = &sc->sc_rxsoft[i]; 1563 if (rxs->rxs_mbuf != NULL) { 1564 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1565 m_freem(rxs->rxs_mbuf); 1566 rxs->rxs_mbuf = NULL; 1567 } 1568 } 1569 } 1570 1571 /* 1572 * ae_stop: [ ifnet interface function ] 1573 * 1574 * Stop transmission on the interface. 1575 */ 1576 static void 1577 ae_stop(struct ifnet *ifp, int disable) 1578 { 1579 struct ae_softc *sc = ifp->if_softc; 1580 struct ae_txsoft *txs; 1581 1582 if (sc->sc_tick != NULL) { 1583 /* Stop the one second clock. */ 1584 callout_stop(&sc->sc_tick_callout); 1585 } 1586 1587 /* Down the MII. */ 1588 mii_down(&sc->sc_mii); 1589 1590 /* Disable interrupts. */ 1591 AE_WRITE(sc, CSR_INTEN, 0); 1592 1593 /* Stop the transmit and receive processes. */ 1594 AE_WRITE(sc, CSR_OPMODE, 0); 1595 AE_WRITE(sc, CSR_RXLIST, 0); 1596 AE_WRITE(sc, CSR_TXLIST, 0); 1597 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1598 AE_BARRIER(sc); 1599 1600 /* 1601 * Release any queued transmit buffers. 1602 */ 1603 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1604 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1605 if (txs->txs_mbuf != NULL) { 1606 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1607 m_freem(txs->txs_mbuf); 1608 txs->txs_mbuf = NULL; 1609 } 1610 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1611 } 1612 1613 /* 1614 * Mark the interface down and cancel the watchdog timer. 1615 */ 1616 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1617 sc->sc_if_flags = ifp->if_flags; 1618 ifp->if_timer = 0; 1619 1620 if (disable) { 1621 ae_rxdrain(sc); 1622 ae_disable(sc); 1623 } 1624 1625 /* 1626 * Reset the chip (needed on some flavors to actually disable it). 1627 */ 1628 ae_reset(sc); 1629 } 1630 1631 /* 1632 * ae_add_rxbuf: 1633 * 1634 * Add a receive buffer to the indicated descriptor. 1635 */ 1636 static int 1637 ae_add_rxbuf(struct ae_softc *sc, int idx) 1638 { 1639 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1640 struct mbuf *m; 1641 int error; 1642 1643 MGETHDR(m, M_DONTWAIT, MT_DATA); 1644 if (m == NULL) 1645 return (ENOBUFS); 1646 1647 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1648 MCLGET(m, M_DONTWAIT); 1649 if ((m->m_flags & M_EXT) == 0) { 1650 m_freem(m); 1651 return (ENOBUFS); 1652 } 1653 1654 if (rxs->rxs_mbuf != NULL) 1655 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1656 1657 rxs->rxs_mbuf = m; 1658 1659 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1660 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1661 BUS_DMA_READ|BUS_DMA_NOWAIT); 1662 if (error) { 1663 printf("%s: can't load rx DMA map %d, error = %d\n", 1664 sc->sc_dev.dv_xname, idx, error); 1665 panic("ae_add_rxbuf"); /* XXX */ 1666 } 1667 1668 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1669 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1670 1671 AE_INIT_RXDESC(sc, idx); 1672 1673 return (0); 1674 } 1675 1676 /* 1677 * ae_filter_setup: 1678 * 1679 * Set the chip's receive filter. 1680 */ 1681 static void 1682 ae_filter_setup(struct ae_softc *sc) 1683 { 1684 struct ethercom *ec = &sc->sc_ethercom; 1685 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1686 struct ether_multi *enm; 1687 struct ether_multistep step; 1688 uint32_t hash, mchash[2]; 1689 uint32_t macctl = 0; 1690 1691 /* 1692 * If the chip is running, we need to reset the interface, 1693 * and will revisit here (with IFF_RUNNING) clear. The 1694 * chip seems to really not like to have its multicast 1695 * filter programmed without a reset. 1696 */ 1697 if (ifp->if_flags & IFF_RUNNING) { 1698 (void) ae_init(ifp); 1699 return; 1700 } 1701 1702 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1703 sc->sc_dev.dv_xname, sc->sc_flags)); 1704 1705 macctl = AE_READ(sc, CSR_MACCTL); 1706 macctl &= ~(MACCTL_PR | MACCTL_PM); 1707 macctl |= MACCTL_HASH; 1708 macctl |= MACCTL_HBD; 1709 macctl |= MACCTL_PR; 1710 1711 if (ifp->if_flags & IFF_PROMISC) { 1712 macctl |= MACCTL_PR; 1713 goto allmulti; 1714 } 1715 1716 mchash[0] = mchash[1] = 0; 1717 1718 ETHER_FIRST_MULTI(step, ec, enm); 1719 while (enm != NULL) { 1720 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1721 /* 1722 * We must listen to a range of multicast addresses. 1723 * For now, just accept all multicasts, rather than 1724 * trying to set only those filter bits needed to match 1725 * the range. (At this time, the only use of address 1726 * ranges is for IP multicast routing, for which the 1727 * range is big enough to require all bits set.) 1728 */ 1729 goto allmulti; 1730 } 1731 1732 /* Verify whether we use big or little endian hashes */ 1733 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1734 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1735 ETHER_NEXT_MULTI(step, enm); 1736 } 1737 ifp->if_flags &= ~IFF_ALLMULTI; 1738 goto setit; 1739 1740 allmulti: 1741 ifp->if_flags |= IFF_ALLMULTI; 1742 mchash[0] = mchash[1] = 0xffffffff; 1743 macctl |= MACCTL_PM; 1744 1745 setit: 1746 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1747 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1748 1749 AE_WRITE(sc, CSR_MACCTL, macctl); 1750 AE_BARRIER(sc); 1751 1752 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1753 sc->sc_dev.dv_xname, macctl)); 1754 } 1755 1756 /* 1757 * ae_idle: 1758 * 1759 * Cause the transmit and/or receive processes to go idle. 1760 */ 1761 void 1762 ae_idle(struct ae_softc *sc, u_int32_t bits) 1763 { 1764 static const char * const txstate_names[] = { 1765 "STOPPED", 1766 "RUNNING - FETCH", 1767 "RUNNING - WAIT", 1768 "RUNNING - READING", 1769 "-- RESERVED --", 1770 "RUNNING - SETUP", 1771 "SUSPENDED", 1772 "RUNNING - CLOSE", 1773 }; 1774 static const char * const rxstate_names[] = { 1775 "STOPPED", 1776 "RUNNING - FETCH", 1777 "RUNNING - CHECK", 1778 "RUNNING - WAIT", 1779 "SUSPENDED", 1780 "RUNNING - CLOSE", 1781 "RUNNING - FLUSH", 1782 "RUNNING - QUEUE", 1783 }; 1784 1785 u_int32_t csr, ackmask = 0; 1786 int i; 1787 1788 if (bits & OPMODE_ST) 1789 ackmask |= STATUS_TPS; 1790 1791 if (bits & OPMODE_SR) 1792 ackmask |= STATUS_RPS; 1793 1794 AE_CLR(sc, CSR_OPMODE, bits); 1795 1796 for (i = 0; i < 1000; i++) { 1797 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1798 break; 1799 delay(10); 1800 } 1801 1802 csr = AE_READ(sc, CSR_STATUS); 1803 if ((csr & ackmask) != ackmask) { 1804 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1805 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1806 printf("%s: transmit process failed to idle: " 1807 "state %s\n", sc->sc_dev.dv_xname, 1808 txstate_names[(csr & STATUS_TS) >> 20]); 1809 } 1810 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1811 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1812 printf("%s: receive process failed to idle: " 1813 "state %s\n", sc->sc_dev.dv_xname, 1814 rxstate_names[(csr & STATUS_RS) >> 17]); 1815 } 1816 } 1817 } 1818 1819 /***************************************************************************** 1820 * Support functions for MII-attached media. 1821 *****************************************************************************/ 1822 1823 /* 1824 * ae_mii_tick: 1825 * 1826 * One second timer, used to tick the MII. 1827 */ 1828 static void 1829 ae_mii_tick(void *arg) 1830 { 1831 struct ae_softc *sc = arg; 1832 int s; 1833 1834 if (!device_is_active(&sc->sc_dev)) 1835 return; 1836 1837 s = splnet(); 1838 mii_tick(&sc->sc_mii); 1839 splx(s); 1840 1841 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1842 } 1843 1844 /* 1845 * ae_mii_statchg: [mii interface function] 1846 * 1847 * Callback from PHY when media changes. 1848 */ 1849 static void 1850 ae_mii_statchg(device_t self) 1851 { 1852 struct ae_softc *sc = device_private(self); 1853 uint32_t macctl, flowc; 1854 1855 //opmode = AE_READ(sc, CSR_OPMODE); 1856 macctl = AE_READ(sc, CSR_MACCTL); 1857 1858 /* XXX: do we need to do this? */ 1859 /* Idle the transmit and receive processes. */ 1860 //ae_idle(sc, OPMODE_ST|OPMODE_SR); 1861 1862 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1863 flowc = FLOWC_FCE; 1864 macctl &= ~MACCTL_DRO; 1865 macctl |= MACCTL_FDX; 1866 } else { 1867 flowc = 0; /* cannot do flow control in HDX */ 1868 macctl |= MACCTL_DRO; 1869 macctl &= ~MACCTL_FDX; 1870 } 1871 1872 AE_WRITE(sc, CSR_FLOWC, flowc); 1873 AE_WRITE(sc, CSR_MACCTL, macctl); 1874 1875 /* restore operational mode */ 1876 //AE_WRITE(sc, CSR_OPMODE, opmode); 1877 AE_BARRIER(sc); 1878 } 1879 1880 /* 1881 * ae_mii_readreg: 1882 * 1883 * Read a PHY register. 1884 */ 1885 static int 1886 ae_mii_readreg(device_t self, int phy, int reg) 1887 { 1888 struct ae_softc *sc = device_private(self); 1889 uint32_t addr; 1890 int i; 1891 1892 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1893 AE_WRITE(sc, CSR_MIIADDR, addr); 1894 AE_BARRIER(sc); 1895 for (i = 0; i < 100000000; i++) { 1896 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1897 break; 1898 } 1899 1900 return (AE_READ(sc, CSR_MIIDATA) & 0xffff); 1901 } 1902 1903 /* 1904 * ae_mii_writereg: 1905 * 1906 * Write a PHY register. 1907 */ 1908 static void 1909 ae_mii_writereg(device_t self, int phy, int reg, int val) 1910 { 1911 struct ae_softc *sc = device_private(self); 1912 uint32_t addr; 1913 int i; 1914 1915 /* write the data register */ 1916 AE_WRITE(sc, CSR_MIIDATA, val); 1917 1918 /* write the address to latch it in */ 1919 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1920 MIIADDR_WRITE; 1921 AE_WRITE(sc, CSR_MIIADDR, addr); 1922 AE_BARRIER(sc); 1923 1924 for (i = 0; i < 100000000; i++) { 1925 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1926 break; 1927 } 1928 } 1929
Indexes created Fri Oct 03 02:09:57 GMT 2025