if_ae.c revision 1.27
1 /* $Id: if_ae.c,v 1.27 2016/02/09 08:32:09 ozaki-r Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the onboard ethernet MAC found on the AR5312 74 * chip's AHB bus. 75 * 76 * This device is very simliar to the tulip in most regards, and 77 * the code is directly derived from NetBSD's tulip.c. However, it 78 * is different enough that it did not seem to be a good idea to 79 * add further complexity to the tulip driver, so we have our own. 80 * 81 * Also tulip has a lot of complexity in it for various parts/options 82 * that we don't need, and on these little boxes with only ~8MB RAM, we 83 * don't want any extra bloat. 84 */ 85 86 /* 87 * TODO: 88 * 89 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 90 * inbound packets on a half-word boundary, which would make life easier 91 * for TCP/IP. (Aligning IP headers on a word.) 92 * 93 * 2) There is stuff in original tulip to shut down the device when reacting 94 * to a a change in link status. Is that needed. 95 * 96 * 3) Test with variety of 10/100 HDX/FDX scenarios. 97 * 98 */ 99 100 #include <sys/cdefs.h> 101 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.27 2016/02/09 08:32:09 ozaki-r Exp $"); 102 103 104 #include <sys/param.h> 105 #include <sys/bus.h> 106 #include <sys/callout.h> 107 #include <sys/device.h> 108 #include <sys/endian.h> 109 #include <sys/errno.h> 110 #include <sys/intr.h> 111 #include <sys/ioctl.h> 112 #include <sys/kernel.h> 113 #include <sys/malloc.h> 114 #include <sys/mbuf.h> 115 #include <sys/socket.h> 116 117 #include <uvm/uvm_extern.h> 118 119 #include <net/if.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/if_ether.h> 123 124 #include <net/bpf.h> 125 126 #include <dev/mii/mii.h> 127 #include <dev/mii/miivar.h> 128 #include <dev/mii/mii_bitbang.h> 129 130 #include <mips/atheros/include/arbusvar.h> 131 #include <mips/atheros/dev/aereg.h> 132 #include <mips/atheros/dev/aevar.h> 133 134 static const struct { 135 u_int32_t txth_opmode; /* OPMODE bits */ 136 const char *txth_name; /* name of mode */ 137 } ae_txthresh[] = { 138 { OPMODE_TR_32, "32 words" }, 139 { OPMODE_TR_64, "64 words" }, 140 { OPMODE_TR_128, "128 words" }, 141 { OPMODE_TR_256, "256 words" }, 142 { OPMODE_SF, "store and forward mode" }, 143 { 0, NULL }, 144 }; 145 146 static int ae_match(device_t, struct cfdata *, void *); 147 static void ae_attach(device_t, device_t, void *); 148 static int ae_detach(device_t, int); 149 static int ae_activate(device_t, enum devact); 150 151 static int ae_ifflags_cb(struct ethercom *); 152 static void ae_reset(struct ae_softc *); 153 static void ae_idle(struct ae_softc *, u_int32_t); 154 155 static void ae_start(struct ifnet *); 156 static void ae_watchdog(struct ifnet *); 157 static int ae_ioctl(struct ifnet *, u_long, void *); 158 static int ae_init(struct ifnet *); 159 static void ae_stop(struct ifnet *, int); 160 161 static void ae_shutdown(void *); 162 163 static void ae_rxdrain(struct ae_softc *); 164 static int ae_add_rxbuf(struct ae_softc *, int); 165 166 static int ae_enable(struct ae_softc *); 167 static void ae_disable(struct ae_softc *); 168 static void ae_power(int, void *); 169 170 static void ae_filter_setup(struct ae_softc *); 171 172 static int ae_intr(void *); 173 static void ae_rxintr(struct ae_softc *); 174 static void ae_txintr(struct ae_softc *); 175 176 static void ae_mii_tick(void *); 177 static void ae_mii_statchg(struct ifnet *); 178 179 static int ae_mii_readreg(device_t, int, int); 180 static void ae_mii_writereg(device_t, int, int, int); 181 182 #ifdef AE_DEBUG 183 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 184 printf x 185 #else 186 #define DPRINTF(sc, x) /* nothing */ 187 #endif 188 189 #ifdef AE_STATS 190 static void ae_print_stats(struct ae_softc *); 191 #endif 192 193 CFATTACH_DECL_NEW(ae, sizeof(struct ae_softc), 194 ae_match, ae_attach, ae_detach, ae_activate); 195 196 /* 197 * ae_match: 198 * 199 * Check for a device match. 200 */ 201 int 202 ae_match(device_t parent, struct cfdata *cf, void *aux) 203 { 204 struct arbus_attach_args *aa = aux; 205 206 if (strcmp(aa->aa_name, cf->cf_name) == 0) 207 return 1; 208 209 return 0; 210 211 } 212 213 /* 214 * ae_attach: 215 * 216 * Attach an ae interface to the system. 217 */ 218 void 219 ae_attach(device_t parent, device_t self, void *aux) 220 { 221 const uint8_t *enaddr; 222 prop_data_t ea; 223 struct ae_softc *sc = device_private(self); 224 struct arbus_attach_args *aa = aux; 225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 226 int i, error; 227 228 sc->sc_dev = self; 229 230 callout_init(&sc->sc_tick_callout, 0); 231 232 printf(": Atheros AR531X 10/100 Ethernet\n"); 233 234 /* 235 * Try to get MAC address. 236 */ 237 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-address"); 238 if (ea == NULL) { 239 printf("%s: unable to get mac-addr property\n", 240 device_xname(sc->sc_dev)); 241 return; 242 } 243 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 244 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 245 enaddr = prop_data_data_nocopy(ea); 246 247 /* Announce ourselves. */ 248 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 249 ether_sprintf(enaddr)); 250 251 sc->sc_cirq = aa->aa_cirq; 252 sc->sc_mirq = aa->aa_mirq; 253 sc->sc_st = aa->aa_bst; 254 sc->sc_dmat = aa->aa_dmat; 255 256 SIMPLEQ_INIT(&sc->sc_txfreeq); 257 SIMPLEQ_INIT(&sc->sc_txdirtyq); 258 259 /* 260 * Map registers. 261 */ 262 sc->sc_size = aa->aa_size; 263 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 264 &sc->sc_sh)) != 0) { 265 printf("%s: unable to map registers, error = %d\n", 266 device_xname(sc->sc_dev), error); 267 goto fail_0; 268 } 269 270 /* 271 * Allocate the control data structures, and create and load the 272 * DMA map for it. 273 */ 274 if ((error = bus_dmamem_alloc(sc->sc_dmat, 275 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 276 1, &sc->sc_cdnseg, 0)) != 0) { 277 printf("%s: unable to allocate control data, error = %d\n", 278 device_xname(sc->sc_dev), error); 279 goto fail_1; 280 } 281 282 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 283 sizeof(struct ae_control_data), (void **)&sc->sc_control_data, 284 BUS_DMA_COHERENT)) != 0) { 285 printf("%s: unable to map control data, error = %d\n", 286 device_xname(sc->sc_dev), error); 287 goto fail_2; 288 } 289 290 if ((error = bus_dmamap_create(sc->sc_dmat, 291 sizeof(struct ae_control_data), 1, 292 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 293 printf("%s: unable to create control data DMA map, " 294 "error = %d\n", device_xname(sc->sc_dev), error); 295 goto fail_3; 296 } 297 298 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 299 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 300 0)) != 0) { 301 printf("%s: unable to load control data DMA map, error = %d\n", 302 device_xname(sc->sc_dev), error); 303 goto fail_4; 304 } 305 306 /* 307 * Create the transmit buffer DMA maps. 308 */ 309 for (i = 0; i < AE_TXQUEUELEN; i++) { 310 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 311 AE_NTXSEGS, MCLBYTES, 0, 0, 312 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 313 printf("%s: unable to create tx DMA map %d, " 314 "error = %d\n", device_xname(sc->sc_dev), i, error); 315 goto fail_5; 316 } 317 } 318 319 /* 320 * Create the receive buffer DMA maps. 321 */ 322 for (i = 0; i < AE_NRXDESC; i++) { 323 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 324 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 325 printf("%s: unable to create rx DMA map %d, " 326 "error = %d\n", device_xname(sc->sc_dev), i, error); 327 goto fail_6; 328 } 329 sc->sc_rxsoft[i].rxs_mbuf = NULL; 330 } 331 332 /* 333 * Reset the chip to a known state. 334 */ 335 ae_reset(sc); 336 337 /* 338 * From this point forward, the attachment cannot fail. A failure 339 * before this point releases all resources that may have been 340 * allocated. 341 */ 342 sc->sc_flags |= AE_ATTACHED; 343 344 /* 345 * Initialize our media structures. This may probe the MII, if 346 * present. 347 */ 348 sc->sc_mii.mii_ifp = ifp; 349 sc->sc_mii.mii_readreg = ae_mii_readreg; 350 sc->sc_mii.mii_writereg = ae_mii_writereg; 351 sc->sc_mii.mii_statchg = ae_mii_statchg; 352 sc->sc_ethercom.ec_mii = &sc->sc_mii; 353 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 354 ether_mediastatus); 355 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 356 MII_OFFSET_ANY, 0); 357 358 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 359 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 360 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 361 } else 362 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 363 364 sc->sc_tick = ae_mii_tick; 365 366 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 sc->sc_if_flags = ifp->if_flags; 370 ifp->if_ioctl = ae_ioctl; 371 ifp->if_start = ae_start; 372 ifp->if_watchdog = ae_watchdog; 373 ifp->if_init = ae_init; 374 ifp->if_stop = ae_stop; 375 IFQ_SET_READY(&ifp->if_snd); 376 377 /* 378 * We can support 802.1Q VLAN-sized frames. 379 */ 380 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 381 382 /* 383 * Attach the interface. 384 */ 385 if_attach(ifp); 386 ether_ifattach(ifp, enaddr); 387 ether_set_ifflags_cb(&sc->sc_ethercom, ae_ifflags_cb); 388 389 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 390 RND_TYPE_NET, RND_FLAG_DEFAULT); 391 392 /* 393 * Make sure the interface is shutdown during reboot. 394 */ 395 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 396 if (sc->sc_sdhook == NULL) 397 printf("%s: WARNING: unable to establish shutdown hook\n", 398 device_xname(sc->sc_dev)); 399 400 /* 401 * Add a suspend hook to make sure we come back up after a 402 * resume. 403 */ 404 sc->sc_powerhook = powerhook_establish(device_xname(sc->sc_dev), 405 ae_power, sc); 406 if (sc->sc_powerhook == NULL) 407 printf("%s: WARNING: unable to establish power hook\n", 408 device_xname(sc->sc_dev)); 409 return; 410 411 /* 412 * Free any resources we've allocated during the failed attach 413 * attempt. Do this in reverse order and fall through. 414 */ 415 fail_6: 416 for (i = 0; i < AE_NRXDESC; i++) { 417 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 418 bus_dmamap_destroy(sc->sc_dmat, 419 sc->sc_rxsoft[i].rxs_dmamap); 420 } 421 fail_5: 422 for (i = 0; i < AE_TXQUEUELEN; i++) { 423 if (sc->sc_txsoft[i].txs_dmamap != NULL) 424 bus_dmamap_destroy(sc->sc_dmat, 425 sc->sc_txsoft[i].txs_dmamap); 426 } 427 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 428 fail_4: 429 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 430 fail_3: 431 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 432 sizeof(struct ae_control_data)); 433 fail_2: 434 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 435 fail_1: 436 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 437 fail_0: 438 return; 439 } 440 441 /* 442 * ae_activate: 443 * 444 * Handle device activation/deactivation requests. 445 */ 446 int 447 ae_activate(device_t self, enum devact act) 448 { 449 struct ae_softc *sc = device_private(self); 450 451 switch (act) { 452 case DVACT_DEACTIVATE: 453 if_deactivate(&sc->sc_ethercom.ec_if); 454 return 0; 455 default: 456 return EOPNOTSUPP; 457 } 458 } 459 460 /* 461 * ae_detach: 462 * 463 * Detach a device interface. 464 */ 465 int 466 ae_detach(device_t self, int flags) 467 { 468 struct ae_softc *sc = device_private(self); 469 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 470 struct ae_rxsoft *rxs; 471 struct ae_txsoft *txs; 472 int i; 473 474 /* 475 * Succeed now if there isn't any work to do. 476 */ 477 if ((sc->sc_flags & AE_ATTACHED) == 0) 478 return (0); 479 480 /* Unhook our tick handler. */ 481 if (sc->sc_tick) 482 callout_stop(&sc->sc_tick_callout); 483 484 /* Detach all PHYs */ 485 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 486 487 /* Delete all remaining media. */ 488 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 489 490 rnd_detach_source(&sc->sc_rnd_source); 491 ether_ifdetach(ifp); 492 if_detach(ifp); 493 494 for (i = 0; i < AE_NRXDESC; i++) { 495 rxs = &sc->sc_rxsoft[i]; 496 if (rxs->rxs_mbuf != NULL) { 497 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 498 m_freem(rxs->rxs_mbuf); 499 rxs->rxs_mbuf = NULL; 500 } 501 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 502 } 503 for (i = 0; i < AE_TXQUEUELEN; i++) { 504 txs = &sc->sc_txsoft[i]; 505 if (txs->txs_mbuf != NULL) { 506 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 507 m_freem(txs->txs_mbuf); 508 txs->txs_mbuf = NULL; 509 } 510 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 511 } 512 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 513 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 514 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 515 sizeof(struct ae_control_data)); 516 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 517 518 shutdownhook_disestablish(sc->sc_sdhook); 519 powerhook_disestablish(sc->sc_powerhook); 520 521 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 522 523 524 return (0); 525 } 526 527 /* 528 * ae_shutdown: 529 * 530 * Make sure the interface is stopped at reboot time. 531 */ 532 static void 533 ae_shutdown(void *arg) 534 { 535 struct ae_softc *sc = arg; 536 537 ae_stop(&sc->sc_ethercom.ec_if, 1); 538 } 539 540 /* 541 * ae_start: [ifnet interface function] 542 * 543 * Start packet transmission on the interface. 544 */ 545 static void 546 ae_start(struct ifnet *ifp) 547 { 548 struct ae_softc *sc = ifp->if_softc; 549 struct mbuf *m0, *m; 550 struct ae_txsoft *txs; 551 bus_dmamap_t dmamap; 552 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 553 554 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 555 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 556 557 558 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 559 return; 560 561 /* 562 * Remember the previous number of free descriptors and 563 * the first descriptor we'll use. 564 */ 565 ofree = sc->sc_txfree; 566 firsttx = sc->sc_txnext; 567 568 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 569 device_xname(sc->sc_dev), ofree, firsttx)); 570 571 /* 572 * Loop through the send queue, setting up transmit descriptors 573 * until we drain the queue, or use up all available transmit 574 * descriptors. 575 */ 576 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 577 sc->sc_txfree != 0) { 578 /* 579 * Grab a packet off the queue. 580 */ 581 IFQ_POLL(&ifp->if_snd, m0); 582 if (m0 == NULL) 583 break; 584 m = NULL; 585 586 dmamap = txs->txs_dmamap; 587 588 /* 589 * Load the DMA map. If this fails, the packet either 590 * didn't fit in the alloted number of segments, or we were 591 * short on resources. In this case, we'll copy and try 592 * again. 593 */ 594 if (((mtod(m0, uintptr_t) & 3) != 0) || 595 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 596 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 597 MGETHDR(m, M_DONTWAIT, MT_DATA); 598 if (m == NULL) { 599 printf("%s: unable to allocate Tx mbuf\n", 600 device_xname(sc->sc_dev)); 601 break; 602 } 603 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 604 if (m0->m_pkthdr.len > MHLEN) { 605 MCLGET(m, M_DONTWAIT); 606 if ((m->m_flags & M_EXT) == 0) { 607 printf("%s: unable to allocate Tx " 608 "cluster\n", device_xname(sc->sc_dev)); 609 m_freem(m); 610 break; 611 } 612 } 613 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 614 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 615 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 616 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 617 if (error) { 618 printf("%s: unable to load Tx buffer, " 619 "error = %d\n", device_xname(sc->sc_dev), 620 error); 621 break; 622 } 623 } 624 625 /* 626 * Ensure we have enough descriptors free to describe 627 * the packet. 628 */ 629 if (dmamap->dm_nsegs > sc->sc_txfree) { 630 /* 631 * Not enough free descriptors to transmit this 632 * packet. We haven't committed to anything yet, 633 * so just unload the DMA map, put the packet 634 * back on the queue, and punt. Notify the upper 635 * layer that there are no more slots left. 636 * 637 * XXX We could allocate an mbuf and copy, but 638 * XXX it is worth it? 639 */ 640 ifp->if_flags |= IFF_OACTIVE; 641 bus_dmamap_unload(sc->sc_dmat, dmamap); 642 if (m != NULL) 643 m_freem(m); 644 break; 645 } 646 647 IFQ_DEQUEUE(&ifp->if_snd, m0); 648 if (m != NULL) { 649 m_freem(m0); 650 m0 = m; 651 } 652 653 /* 654 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 655 */ 656 657 /* Sync the DMA map. */ 658 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 659 BUS_DMASYNC_PREWRITE); 660 661 /* 662 * Initialize the transmit descriptors. 663 */ 664 for (nexttx = sc->sc_txnext, seg = 0; 665 seg < dmamap->dm_nsegs; 666 seg++, nexttx = AE_NEXTTX(nexttx)) { 667 /* 668 * If this is the first descriptor we're 669 * enqueueing, don't set the OWN bit just 670 * yet. That could cause a race condition. 671 * We'll do it below. 672 */ 673 sc->sc_txdescs[nexttx].ad_status = 674 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 675 sc->sc_txdescs[nexttx].ad_bufaddr1 = 676 dmamap->dm_segs[seg].ds_addr; 677 sc->sc_txdescs[nexttx].ad_ctl = 678 (dmamap->dm_segs[seg].ds_len << 679 ADCTL_SIZE1_SHIFT) | 680 (nexttx == (AE_NTXDESC - 1) ? 681 ADCTL_ER : 0); 682 lasttx = nexttx; 683 } 684 685 KASSERT(lasttx != -1); 686 687 /* Set `first segment' and `last segment' appropriately. */ 688 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 689 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 690 691 #ifdef AE_DEBUG 692 if (ifp->if_flags & IFF_DEBUG) { 693 printf(" txsoft %p transmit chain:\n", txs); 694 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 695 printf(" descriptor %d:\n", seg); 696 printf(" ad_status: 0x%08x\n", 697 sc->sc_txdescs[seg].ad_status); 698 printf(" ad_ctl: 0x%08x\n", 699 sc->sc_txdescs[seg].ad_ctl); 700 printf(" ad_bufaddr1: 0x%08x\n", 701 sc->sc_txdescs[seg].ad_bufaddr1); 702 printf(" ad_bufaddr2: 0x%08x\n", 703 sc->sc_txdescs[seg].ad_bufaddr2); 704 if (seg == lasttx) 705 break; 706 } 707 } 708 #endif 709 710 /* Sync the descriptors we're using. */ 711 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 712 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 713 714 /* 715 * Store a pointer to the packet so we can free it later, 716 * and remember what txdirty will be once the packet is 717 * done. 718 */ 719 txs->txs_mbuf = m0; 720 txs->txs_firstdesc = sc->sc_txnext; 721 txs->txs_lastdesc = lasttx; 722 txs->txs_ndescs = dmamap->dm_nsegs; 723 724 /* Advance the tx pointer. */ 725 sc->sc_txfree -= dmamap->dm_nsegs; 726 sc->sc_txnext = nexttx; 727 728 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 729 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 730 731 /* 732 * Pass the packet to any BPF listeners. 733 */ 734 bpf_mtap(ifp, m0); 735 } 736 737 if (txs == NULL || sc->sc_txfree == 0) { 738 /* No more slots left; notify upper layer. */ 739 ifp->if_flags |= IFF_OACTIVE; 740 } 741 742 if (sc->sc_txfree != ofree) { 743 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 744 device_xname(sc->sc_dev), lasttx, firsttx)); 745 /* 746 * Cause a transmit interrupt to happen on the 747 * last packet we enqueued. 748 */ 749 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 750 AE_CDTXSYNC(sc, lasttx, 1, 751 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 752 753 /* 754 * The entire packet chain is set up. Give the 755 * first descriptor to the chip now. 756 */ 757 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 758 AE_CDTXSYNC(sc, firsttx, 1, 759 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 760 761 /* Wake up the transmitter. */ 762 /* XXX USE AUTOPOLLING? */ 763 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 764 AE_BARRIER(sc); 765 766 /* Set a watchdog timer in case the chip flakes out. */ 767 ifp->if_timer = 5; 768 } 769 } 770 771 /* 772 * ae_watchdog: [ifnet interface function] 773 * 774 * Watchdog timer handler. 775 */ 776 static void 777 ae_watchdog(struct ifnet *ifp) 778 { 779 struct ae_softc *sc = ifp->if_softc; 780 int doing_transmit; 781 782 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 783 784 if (doing_transmit) { 785 printf("%s: transmit timeout\n", device_xname(sc->sc_dev)); 786 ifp->if_oerrors++; 787 } 788 else 789 printf("%s: spurious watchdog timeout\n", device_xname(sc->sc_dev)); 790 791 (void) ae_init(ifp); 792 793 /* Try to get more packets going. */ 794 ae_start(ifp); 795 } 796 797 /* If the interface is up and running, only modify the receive 798 * filter when changing to/from promiscuous mode. Otherwise return 799 * ENETRESET so that ether_ioctl will reset the chip. 800 */ 801 static int 802 ae_ifflags_cb(struct ethercom *ec) 803 { 804 struct ifnet *ifp = &ec->ec_if; 805 struct ae_softc *sc = ifp->if_softc; 806 int change = ifp->if_flags ^ sc->sc_if_flags; 807 808 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 809 return ENETRESET; 810 else if ((change & IFF_PROMISC) != 0) 811 ae_filter_setup(sc); 812 return 0; 813 } 814 815 /* 816 * ae_ioctl: [ifnet interface function] 817 * 818 * Handle control requests from the operator. 819 */ 820 static int 821 ae_ioctl(struct ifnet *ifp, u_long cmd, void *data) 822 { 823 struct ae_softc *sc = ifp->if_softc; 824 int s, error; 825 826 s = splnet(); 827 828 error = ether_ioctl(ifp, cmd, data); 829 if (error == ENETRESET) { 830 if (ifp->if_flags & IFF_RUNNING) { 831 /* 832 * Multicast list has changed. Set the 833 * hardware filter accordingly. 834 */ 835 ae_filter_setup(sc); 836 } 837 error = 0; 838 } 839 840 /* Try to get more packets going. */ 841 if (AE_IS_ENABLED(sc)) 842 ae_start(ifp); 843 844 sc->sc_if_flags = ifp->if_flags; 845 splx(s); 846 return (error); 847 } 848 849 /* 850 * ae_intr: 851 * 852 * Interrupt service routine. 853 */ 854 int 855 ae_intr(void *arg) 856 { 857 struct ae_softc *sc = arg; 858 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 859 u_int32_t status, rxstatus, txstatus; 860 int handled = 0, txthresh; 861 862 DPRINTF(sc, ("%s: ae_intr\n", device_xname(sc->sc_dev))); 863 864 #ifdef DEBUG 865 if (AE_IS_ENABLED(sc) == 0) 866 panic("%s: ae_intr: not enabled", device_xname(sc->sc_dev)); 867 #endif 868 869 /* 870 * If the interface isn't running, the interrupt couldn't 871 * possibly have come from us. 872 */ 873 if ((ifp->if_flags & IFF_RUNNING) == 0 || 874 !device_is_active(sc->sc_dev)) { 875 printf("spurious?!?\n"); 876 return (0); 877 } 878 879 for (;;) { 880 status = AE_READ(sc, CSR_STATUS); 881 if (status) { 882 AE_WRITE(sc, CSR_STATUS, status); 883 AE_BARRIER(sc); 884 } 885 886 if ((status & sc->sc_inten) == 0) 887 break; 888 889 handled = 1; 890 891 rxstatus = status & sc->sc_rxint_mask; 892 txstatus = status & sc->sc_txint_mask; 893 894 if (rxstatus) { 895 /* Grab new any new packets. */ 896 ae_rxintr(sc); 897 898 if (rxstatus & STATUS_RU) { 899 printf("%s: receive ring overrun\n", 900 device_xname(sc->sc_dev)); 901 /* Get the receive process going again. */ 902 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 903 AE_BARRIER(sc); 904 break; 905 } 906 } 907 908 if (txstatus) { 909 /* Sweep up transmit descriptors. */ 910 ae_txintr(sc); 911 912 if (txstatus & STATUS_TJT) 913 printf("%s: transmit jabber timeout\n", 914 device_xname(sc->sc_dev)); 915 916 if (txstatus & STATUS_UNF) { 917 /* 918 * Increase our transmit threshold if 919 * another is available. 920 */ 921 txthresh = sc->sc_txthresh + 1; 922 if (ae_txthresh[txthresh].txth_name != NULL) { 923 uint32_t opmode; 924 /* Idle the transmit process. */ 925 opmode = AE_READ(sc, CSR_OPMODE); 926 ae_idle(sc, OPMODE_ST); 927 928 sc->sc_txthresh = txthresh; 929 opmode &= 930 ~(OPMODE_TR|OPMODE_SF); 931 opmode |= 932 ae_txthresh[txthresh].txth_opmode; 933 printf("%s: transmit underrun; new " 934 "threshold: %s\n", 935 device_xname(sc->sc_dev), 936 ae_txthresh[txthresh].txth_name); 937 938 /* 939 * Set the new threshold and restart 940 * the transmit process. 941 */ 942 AE_WRITE(sc, CSR_OPMODE, opmode); 943 AE_BARRIER(sc); 944 } 945 /* 946 * XXX Log every Nth underrun from 947 * XXX now on? 948 */ 949 } 950 } 951 952 if (status & (STATUS_TPS|STATUS_RPS)) { 953 if (status & STATUS_TPS) 954 printf("%s: transmit process stopped\n", 955 device_xname(sc->sc_dev)); 956 if (status & STATUS_RPS) 957 printf("%s: receive process stopped\n", 958 device_xname(sc->sc_dev)); 959 (void) ae_init(ifp); 960 break; 961 } 962 963 if (status & STATUS_SE) { 964 const char *str; 965 966 if (status & STATUS_TX_ABORT) 967 str = "tx abort"; 968 else if (status & STATUS_RX_ABORT) 969 str = "rx abort"; 970 else 971 str = "unknown error"; 972 973 printf("%s: fatal system error: %s\n", 974 device_xname(sc->sc_dev), str); 975 (void) ae_init(ifp); 976 break; 977 } 978 979 /* 980 * Not handled: 981 * 982 * Transmit buffer unavailable -- normal 983 * condition, nothing to do, really. 984 * 985 * General purpose timer experied -- we don't 986 * use the general purpose timer. 987 * 988 * Early receive interrupt -- not available on 989 * all chips, we just use RI. We also only 990 * use single-segment receive DMA, so this 991 * is mostly useless. 992 */ 993 } 994 995 /* Try to get more packets going. */ 996 ae_start(ifp); 997 998 if (handled) 999 rnd_add_uint32(&sc->sc_rnd_source, status); 1000 return (handled); 1001 } 1002 1003 /* 1004 * ae_rxintr: 1005 * 1006 * Helper; handle receive interrupts. 1007 */ 1008 static void 1009 ae_rxintr(struct ae_softc *sc) 1010 { 1011 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1012 struct ae_rxsoft *rxs; 1013 struct mbuf *m; 1014 u_int32_t rxstat; 1015 int i, len; 1016 1017 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1018 rxs = &sc->sc_rxsoft[i]; 1019 1020 AE_CDRXSYNC(sc, i, 1021 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1022 1023 rxstat = sc->sc_rxdescs[i].ad_status; 1024 1025 if (rxstat & ADSTAT_OWN) { 1026 /* 1027 * We have processed all of the receive buffers. 1028 */ 1029 break; 1030 } 1031 1032 /* 1033 * If any collisions were seen on the wire, count one. 1034 */ 1035 if (rxstat & ADSTAT_Rx_CS) 1036 ifp->if_collisions++; 1037 1038 /* 1039 * If an error occurred, update stats, clear the status 1040 * word, and leave the packet buffer in place. It will 1041 * simply be reused the next time the ring comes around. 1042 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1043 * error. 1044 */ 1045 if (rxstat & ADSTAT_ES && 1046 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1047 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1048 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1049 #define PRINTERR(bit, str) \ 1050 if (rxstat & (bit)) \ 1051 printf("%s: receive error: %s\n", \ 1052 device_xname(sc->sc_dev), str) 1053 ifp->if_ierrors++; 1054 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1055 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1056 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1057 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1058 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1059 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1060 #undef PRINTERR 1061 AE_INIT_RXDESC(sc, i); 1062 continue; 1063 } 1064 1065 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1066 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1067 1068 /* 1069 * No errors; receive the packet. Note the chip 1070 * includes the CRC with every packet. 1071 */ 1072 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1073 1074 /* 1075 * XXX: the Atheros part can align on half words. what 1076 * is the performance implication of this? Probably 1077 * minimal, and we should use it... 1078 */ 1079 #ifdef __NO_STRICT_ALIGNMENT 1080 /* 1081 * Allocate a new mbuf cluster. If that fails, we are 1082 * out of memory, and must drop the packet and recycle 1083 * the buffer that's already attached to this descriptor. 1084 */ 1085 m = rxs->rxs_mbuf; 1086 if (ae_add_rxbuf(sc, i) != 0) { 1087 ifp->if_ierrors++; 1088 AE_INIT_RXDESC(sc, i); 1089 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1090 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1091 continue; 1092 } 1093 #else 1094 /* 1095 * The chip's receive buffers must be 4-byte aligned. 1096 * But this means that the data after the Ethernet header 1097 * is misaligned. We must allocate a new buffer and 1098 * copy the data, shifted forward 2 bytes. 1099 */ 1100 MGETHDR(m, M_DONTWAIT, MT_DATA); 1101 if (m == NULL) { 1102 dropit: 1103 ifp->if_ierrors++; 1104 AE_INIT_RXDESC(sc, i); 1105 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1106 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1107 continue; 1108 } 1109 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1110 if (len > (MHLEN - 2)) { 1111 MCLGET(m, M_DONTWAIT); 1112 if ((m->m_flags & M_EXT) == 0) { 1113 m_freem(m); 1114 goto dropit; 1115 } 1116 } 1117 m->m_data += 2; 1118 1119 /* 1120 * Note that we use clusters for incoming frames, so the 1121 * buffer is virtually contiguous. 1122 */ 1123 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 1124 1125 /* Allow the receive descriptor to continue using its mbuf. */ 1126 AE_INIT_RXDESC(sc, i); 1127 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1128 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1129 #endif /* __NO_STRICT_ALIGNMENT */ 1130 1131 ifp->if_ipackets++; 1132 m->m_pkthdr.rcvif = ifp; 1133 m->m_pkthdr.len = m->m_len = len; 1134 1135 /* 1136 * Pass this up to any BPF listeners, but only 1137 * pass it up the stack if its for us. 1138 */ 1139 bpf_mtap(ifp, m); 1140 1141 /* Pass it on. */ 1142 if_percpuq_enqueue(ifp->if_percpuq, m); 1143 } 1144 1145 /* Update the receive pointer. */ 1146 sc->sc_rxptr = i; 1147 } 1148 1149 /* 1150 * ae_txintr: 1151 * 1152 * Helper; handle transmit interrupts. 1153 */ 1154 static void 1155 ae_txintr(struct ae_softc *sc) 1156 { 1157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1158 struct ae_txsoft *txs; 1159 u_int32_t txstat; 1160 1161 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1162 device_xname(sc->sc_dev), sc->sc_flags)); 1163 1164 ifp->if_flags &= ~IFF_OACTIVE; 1165 1166 /* 1167 * Go through our Tx list and free mbufs for those 1168 * frames that have been transmitted. 1169 */ 1170 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1171 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1172 txs->txs_ndescs, 1173 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1174 1175 #ifdef AE_DEBUG 1176 if (ifp->if_flags & IFF_DEBUG) { 1177 int i; 1178 printf(" txsoft %p transmit chain:\n", txs); 1179 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1180 printf(" descriptor %d:\n", i); 1181 printf(" ad_status: 0x%08x\n", 1182 sc->sc_txdescs[i].ad_status); 1183 printf(" ad_ctl: 0x%08x\n", 1184 sc->sc_txdescs[i].ad_ctl); 1185 printf(" ad_bufaddr1: 0x%08x\n", 1186 sc->sc_txdescs[i].ad_bufaddr1); 1187 printf(" ad_bufaddr2: 0x%08x\n", 1188 sc->sc_txdescs[i].ad_bufaddr2); 1189 if (i == txs->txs_lastdesc) 1190 break; 1191 } 1192 } 1193 #endif 1194 1195 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1196 if (txstat & ADSTAT_OWN) 1197 break; 1198 1199 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1200 1201 sc->sc_txfree += txs->txs_ndescs; 1202 1203 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1204 0, txs->txs_dmamap->dm_mapsize, 1205 BUS_DMASYNC_POSTWRITE); 1206 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1207 m_freem(txs->txs_mbuf); 1208 txs->txs_mbuf = NULL; 1209 1210 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1211 1212 /* 1213 * Check for errors and collisions. 1214 */ 1215 #ifdef AE_STATS 1216 if (txstat & ADSTAT_Tx_UF) 1217 sc->sc_stats.ts_tx_uf++; 1218 if (txstat & ADSTAT_Tx_TO) 1219 sc->sc_stats.ts_tx_to++; 1220 if (txstat & ADSTAT_Tx_EC) 1221 sc->sc_stats.ts_tx_ec++; 1222 if (txstat & ADSTAT_Tx_LC) 1223 sc->sc_stats.ts_tx_lc++; 1224 #endif 1225 1226 if (txstat & (ADSTAT_Tx_UF|ADSTAT_Tx_TO)) 1227 ifp->if_oerrors++; 1228 1229 if (txstat & ADSTAT_Tx_EC) 1230 ifp->if_collisions += 16; 1231 else 1232 ifp->if_collisions += ADSTAT_Tx_COLLISIONS(txstat); 1233 if (txstat & ADSTAT_Tx_LC) 1234 ifp->if_collisions++; 1235 1236 ifp->if_opackets++; 1237 } 1238 1239 /* 1240 * If there are no more pending transmissions, cancel the watchdog 1241 * timer. 1242 */ 1243 if (txs == NULL) 1244 ifp->if_timer = 0; 1245 } 1246 1247 #ifdef AE_STATS 1248 void 1249 ae_print_stats(struct ae_softc *sc) 1250 { 1251 1252 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1253 device_xname(sc->sc_dev), 1254 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1255 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1256 } 1257 #endif 1258 1259 /* 1260 * ae_reset: 1261 * 1262 * Perform a soft reset on the chip. 1263 */ 1264 void 1265 ae_reset(struct ae_softc *sc) 1266 { 1267 int i; 1268 1269 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1270 AE_BARRIER(sc); 1271 1272 /* 1273 * The chip doesn't take itself out of reset automatically. 1274 * We need to do so after 2us. 1275 */ 1276 delay(10); 1277 AE_WRITE(sc, CSR_BUSMODE, 0); 1278 AE_BARRIER(sc); 1279 1280 for (i = 0; i < 1000; i++) { 1281 /* 1282 * Wait a bit for the reset to complete before peeking 1283 * at the chip again. 1284 */ 1285 delay(10); 1286 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1287 break; 1288 } 1289 1290 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1291 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 1292 1293 delay(1000); 1294 } 1295 1296 /* 1297 * ae_init: [ ifnet interface function ] 1298 * 1299 * Initialize the interface. Must be called at splnet(). 1300 */ 1301 static int 1302 ae_init(struct ifnet *ifp) 1303 { 1304 struct ae_softc *sc = ifp->if_softc; 1305 struct ae_txsoft *txs; 1306 struct ae_rxsoft *rxs; 1307 const uint8_t *enaddr; 1308 int i, error = 0; 1309 1310 if ((error = ae_enable(sc)) != 0) 1311 goto out; 1312 1313 /* 1314 * Cancel any pending I/O. 1315 */ 1316 ae_stop(ifp, 0); 1317 1318 /* 1319 * Reset the chip to a known state. 1320 */ 1321 ae_reset(sc); 1322 1323 /* 1324 * Initialize the BUSMODE register. 1325 */ 1326 AE_WRITE(sc, CSR_BUSMODE, 1327 /* XXX: not sure if this is a good thing or not... */ 1328 //BUSMODE_ALIGN_16B | 1329 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1330 AE_BARRIER(sc); 1331 1332 /* 1333 * Initialize the transmit descriptor ring. 1334 */ 1335 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1336 for (i = 0; i < AE_NTXDESC; i++) { 1337 sc->sc_txdescs[i].ad_ctl = 0; 1338 sc->sc_txdescs[i].ad_bufaddr2 = 1339 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1340 } 1341 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1342 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1343 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1344 sc->sc_txfree = AE_NTXDESC; 1345 sc->sc_txnext = 0; 1346 1347 /* 1348 * Initialize the transmit job descriptors. 1349 */ 1350 SIMPLEQ_INIT(&sc->sc_txfreeq); 1351 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1352 for (i = 0; i < AE_TXQUEUELEN; i++) { 1353 txs = &sc->sc_txsoft[i]; 1354 txs->txs_mbuf = NULL; 1355 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1356 } 1357 1358 /* 1359 * Initialize the receive descriptor and receive job 1360 * descriptor rings. 1361 */ 1362 for (i = 0; i < AE_NRXDESC; i++) { 1363 rxs = &sc->sc_rxsoft[i]; 1364 if (rxs->rxs_mbuf == NULL) { 1365 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1366 printf("%s: unable to allocate or map rx " 1367 "buffer %d, error = %d\n", 1368 device_xname(sc->sc_dev), i, error); 1369 /* 1370 * XXX Should attempt to run with fewer receive 1371 * XXX buffers instead of just failing. 1372 */ 1373 ae_rxdrain(sc); 1374 goto out; 1375 } 1376 } else 1377 AE_INIT_RXDESC(sc, i); 1378 } 1379 sc->sc_rxptr = 0; 1380 1381 /* 1382 * Initialize the interrupt mask and enable interrupts. 1383 */ 1384 /* normal interrupts */ 1385 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1386 1387 /* abnormal interrupts */ 1388 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1389 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1390 1391 sc->sc_rxint_mask = STATUS_RI|STATUS_RU; 1392 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT; 1393 1394 sc->sc_rxint_mask &= sc->sc_inten; 1395 sc->sc_txint_mask &= sc->sc_inten; 1396 1397 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1398 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1399 1400 /* 1401 * Give the transmit and receive rings to the chip. 1402 */ 1403 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1404 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1405 AE_BARRIER(sc); 1406 1407 /* 1408 * Set the station address. 1409 */ 1410 enaddr = CLLADDR(ifp->if_sadl); 1411 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1412 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1413 enaddr[1] << 8 | enaddr[0]); 1414 AE_BARRIER(sc); 1415 1416 /* 1417 * Set the receive filter. This will start the transmit and 1418 * receive processes. 1419 */ 1420 ae_filter_setup(sc); 1421 1422 /* 1423 * Set the current media. 1424 */ 1425 if ((error = ether_mediachange(ifp)) != 0) 1426 goto out; 1427 1428 /* 1429 * Start the mac. 1430 */ 1431 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1432 AE_BARRIER(sc); 1433 1434 /* 1435 * Write out the opmode. 1436 */ 1437 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1438 ae_txthresh[sc->sc_txthresh].txth_opmode); 1439 /* 1440 * Start the receive process. 1441 */ 1442 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1443 AE_BARRIER(sc); 1444 1445 if (sc->sc_tick != NULL) { 1446 /* Start the one second clock. */ 1447 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1448 } 1449 1450 /* 1451 * Note that the interface is now running. 1452 */ 1453 ifp->if_flags |= IFF_RUNNING; 1454 ifp->if_flags &= ~IFF_OACTIVE; 1455 sc->sc_if_flags = ifp->if_flags; 1456 1457 out: 1458 if (error) { 1459 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1460 ifp->if_timer = 0; 1461 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1462 } 1463 return (error); 1464 } 1465 1466 /* 1467 * ae_enable: 1468 * 1469 * Enable the chip. 1470 */ 1471 static int 1472 ae_enable(struct ae_softc *sc) 1473 { 1474 1475 if (AE_IS_ENABLED(sc) == 0) { 1476 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1477 ae_intr, sc); 1478 if (sc->sc_ih == NULL) { 1479 printf("%s: unable to establish interrupt\n", 1480 device_xname(sc->sc_dev)); 1481 return (EIO); 1482 } 1483 sc->sc_flags |= AE_ENABLED; 1484 } 1485 return (0); 1486 } 1487 1488 /* 1489 * ae_disable: 1490 * 1491 * Disable the chip. 1492 */ 1493 static void 1494 ae_disable(struct ae_softc *sc) 1495 { 1496 1497 if (AE_IS_ENABLED(sc)) { 1498 arbus_intr_disestablish(sc->sc_ih); 1499 sc->sc_flags &= ~AE_ENABLED; 1500 } 1501 } 1502 1503 /* 1504 * ae_power: 1505 * 1506 * Power management (suspend/resume) hook. 1507 */ 1508 static void 1509 ae_power(int why, void *arg) 1510 { 1511 struct ae_softc *sc = arg; 1512 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1513 int s; 1514 1515 printf("power called: %d, %x\n", why, (uint32_t)arg); 1516 s = splnet(); 1517 switch (why) { 1518 case PWR_STANDBY: 1519 /* do nothing! */ 1520 break; 1521 case PWR_SUSPEND: 1522 ae_stop(ifp, 0); 1523 ae_disable(sc); 1524 break; 1525 case PWR_RESUME: 1526 if (ifp->if_flags & IFF_UP) { 1527 ae_enable(sc); 1528 ae_init(ifp); 1529 } 1530 break; 1531 case PWR_SOFTSUSPEND: 1532 case PWR_SOFTSTANDBY: 1533 case PWR_SOFTRESUME: 1534 break; 1535 } 1536 splx(s); 1537 } 1538 1539 /* 1540 * ae_rxdrain: 1541 * 1542 * Drain the receive queue. 1543 */ 1544 static void 1545 ae_rxdrain(struct ae_softc *sc) 1546 { 1547 struct ae_rxsoft *rxs; 1548 int i; 1549 1550 for (i = 0; i < AE_NRXDESC; i++) { 1551 rxs = &sc->sc_rxsoft[i]; 1552 if (rxs->rxs_mbuf != NULL) { 1553 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1554 m_freem(rxs->rxs_mbuf); 1555 rxs->rxs_mbuf = NULL; 1556 } 1557 } 1558 } 1559 1560 /* 1561 * ae_stop: [ ifnet interface function ] 1562 * 1563 * Stop transmission on the interface. 1564 */ 1565 static void 1566 ae_stop(struct ifnet *ifp, int disable) 1567 { 1568 struct ae_softc *sc = ifp->if_softc; 1569 struct ae_txsoft *txs; 1570 1571 if (sc->sc_tick != NULL) { 1572 /* Stop the one second clock. */ 1573 callout_stop(&sc->sc_tick_callout); 1574 } 1575 1576 /* Down the MII. */ 1577 mii_down(&sc->sc_mii); 1578 1579 /* Disable interrupts. */ 1580 AE_WRITE(sc, CSR_INTEN, 0); 1581 1582 /* Stop the transmit and receive processes. */ 1583 AE_WRITE(sc, CSR_OPMODE, 0); 1584 AE_WRITE(sc, CSR_RXLIST, 0); 1585 AE_WRITE(sc, CSR_TXLIST, 0); 1586 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1587 AE_BARRIER(sc); 1588 1589 /* 1590 * Release any queued transmit buffers. 1591 */ 1592 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1593 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1594 if (txs->txs_mbuf != NULL) { 1595 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1596 m_freem(txs->txs_mbuf); 1597 txs->txs_mbuf = NULL; 1598 } 1599 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1600 } 1601 1602 /* 1603 * Mark the interface down and cancel the watchdog timer. 1604 */ 1605 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1606 sc->sc_if_flags = ifp->if_flags; 1607 ifp->if_timer = 0; 1608 1609 if (disable) { 1610 ae_rxdrain(sc); 1611 ae_disable(sc); 1612 } 1613 1614 /* 1615 * Reset the chip (needed on some flavors to actually disable it). 1616 */ 1617 ae_reset(sc); 1618 } 1619 1620 /* 1621 * ae_add_rxbuf: 1622 * 1623 * Add a receive buffer to the indicated descriptor. 1624 */ 1625 static int 1626 ae_add_rxbuf(struct ae_softc *sc, int idx) 1627 { 1628 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1629 struct mbuf *m; 1630 int error; 1631 1632 MGETHDR(m, M_DONTWAIT, MT_DATA); 1633 if (m == NULL) 1634 return (ENOBUFS); 1635 1636 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1637 MCLGET(m, M_DONTWAIT); 1638 if ((m->m_flags & M_EXT) == 0) { 1639 m_freem(m); 1640 return (ENOBUFS); 1641 } 1642 1643 if (rxs->rxs_mbuf != NULL) 1644 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1645 1646 rxs->rxs_mbuf = m; 1647 1648 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1649 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1650 BUS_DMA_READ|BUS_DMA_NOWAIT); 1651 if (error) { 1652 printf("%s: can't load rx DMA map %d, error = %d\n", 1653 device_xname(sc->sc_dev), idx, error); 1654 panic("ae_add_rxbuf"); /* XXX */ 1655 } 1656 1657 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1658 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1659 1660 AE_INIT_RXDESC(sc, idx); 1661 1662 return (0); 1663 } 1664 1665 /* 1666 * ae_filter_setup: 1667 * 1668 * Set the chip's receive filter. 1669 */ 1670 static void 1671 ae_filter_setup(struct ae_softc *sc) 1672 { 1673 struct ethercom *ec = &sc->sc_ethercom; 1674 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1675 struct ether_multi *enm; 1676 struct ether_multistep step; 1677 uint32_t hash, mchash[2]; 1678 uint32_t macctl = 0; 1679 1680 /* 1681 * If the chip is running, we need to reset the interface, 1682 * and will revisit here (with IFF_RUNNING) clear. The 1683 * chip seems to really not like to have its multicast 1684 * filter programmed without a reset. 1685 */ 1686 if (ifp->if_flags & IFF_RUNNING) { 1687 (void) ae_init(ifp); 1688 return; 1689 } 1690 1691 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1692 device_xname(sc->sc_dev), sc->sc_flags)); 1693 1694 macctl = AE_READ(sc, CSR_MACCTL); 1695 macctl &= ~(MACCTL_PR | MACCTL_PM); 1696 macctl |= MACCTL_HASH; 1697 macctl |= MACCTL_HBD; 1698 macctl |= MACCTL_PR; 1699 1700 if (ifp->if_flags & IFF_PROMISC) { 1701 macctl |= MACCTL_PR; 1702 goto allmulti; 1703 } 1704 1705 mchash[0] = mchash[1] = 0; 1706 1707 ETHER_FIRST_MULTI(step, ec, enm); 1708 while (enm != NULL) { 1709 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1710 /* 1711 * We must listen to a range of multicast addresses. 1712 * For now, just accept all multicasts, rather than 1713 * trying to set only those filter bits needed to match 1714 * the range. (At this time, the only use of address 1715 * ranges is for IP multicast routing, for which the 1716 * range is big enough to require all bits set.) 1717 */ 1718 goto allmulti; 1719 } 1720 1721 /* Verify whether we use big or little endian hashes */ 1722 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1723 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1724 ETHER_NEXT_MULTI(step, enm); 1725 } 1726 ifp->if_flags &= ~IFF_ALLMULTI; 1727 goto setit; 1728 1729 allmulti: 1730 ifp->if_flags |= IFF_ALLMULTI; 1731 mchash[0] = mchash[1] = 0xffffffff; 1732 macctl |= MACCTL_PM; 1733 1734 setit: 1735 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1736 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1737 1738 AE_WRITE(sc, CSR_MACCTL, macctl); 1739 AE_BARRIER(sc); 1740 1741 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1742 device_xname(sc->sc_dev), macctl)); 1743 } 1744 1745 /* 1746 * ae_idle: 1747 * 1748 * Cause the transmit and/or receive processes to go idle. 1749 */ 1750 void 1751 ae_idle(struct ae_softc *sc, u_int32_t bits) 1752 { 1753 static const char * const txstate_names[] = { 1754 "STOPPED", 1755 "RUNNING - FETCH", 1756 "RUNNING - WAIT", 1757 "RUNNING - READING", 1758 "-- RESERVED --", 1759 "RUNNING - SETUP", 1760 "SUSPENDED", 1761 "RUNNING - CLOSE", 1762 }; 1763 static const char * const rxstate_names[] = { 1764 "STOPPED", 1765 "RUNNING - FETCH", 1766 "RUNNING - CHECK", 1767 "RUNNING - WAIT", 1768 "SUSPENDED", 1769 "RUNNING - CLOSE", 1770 "RUNNING - FLUSH", 1771 "RUNNING - QUEUE", 1772 }; 1773 1774 u_int32_t csr, ackmask = 0; 1775 int i; 1776 1777 if (bits & OPMODE_ST) 1778 ackmask |= STATUS_TPS; 1779 1780 if (bits & OPMODE_SR) 1781 ackmask |= STATUS_RPS; 1782 1783 AE_CLR(sc, CSR_OPMODE, bits); 1784 1785 for (i = 0; i < 1000; i++) { 1786 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1787 break; 1788 delay(10); 1789 } 1790 1791 csr = AE_READ(sc, CSR_STATUS); 1792 if ((csr & ackmask) != ackmask) { 1793 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1794 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1795 printf("%s: transmit process failed to idle: " 1796 "state %s\n", device_xname(sc->sc_dev), 1797 txstate_names[(csr & STATUS_TS) >> 20]); 1798 } 1799 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1800 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1801 printf("%s: receive process failed to idle: " 1802 "state %s\n", device_xname(sc->sc_dev), 1803 rxstate_names[(csr & STATUS_RS) >> 17]); 1804 } 1805 } 1806 } 1807 1808 /***************************************************************************** 1809 * Support functions for MII-attached media. 1810 *****************************************************************************/ 1811 1812 /* 1813 * ae_mii_tick: 1814 * 1815 * One second timer, used to tick the MII. 1816 */ 1817 static void 1818 ae_mii_tick(void *arg) 1819 { 1820 struct ae_softc *sc = arg; 1821 int s; 1822 1823 if (!device_is_active(sc->sc_dev)) 1824 return; 1825 1826 s = splnet(); 1827 mii_tick(&sc->sc_mii); 1828 splx(s); 1829 1830 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1831 } 1832 1833 /* 1834 * ae_mii_statchg: [mii interface function] 1835 * 1836 * Callback from PHY when media changes. 1837 */ 1838 static void 1839 ae_mii_statchg(struct ifnet *ifp) 1840 { 1841 struct ae_softc *sc = ifp->if_softc; 1842 uint32_t macctl, flowc; 1843 1844 //opmode = AE_READ(sc, CSR_OPMODE); 1845 macctl = AE_READ(sc, CSR_MACCTL); 1846 1847 /* XXX: do we need to do this? */ 1848 /* Idle the transmit and receive processes. */ 1849 //ae_idle(sc, OPMODE_ST|OPMODE_SR); 1850 1851 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1852 flowc = FLOWC_FCE; 1853 macctl &= ~MACCTL_DRO; 1854 macctl |= MACCTL_FDX; 1855 } else { 1856 flowc = 0; /* cannot do flow control in HDX */ 1857 macctl |= MACCTL_DRO; 1858 macctl &= ~MACCTL_FDX; 1859 } 1860 1861 AE_WRITE(sc, CSR_FLOWC, flowc); 1862 AE_WRITE(sc, CSR_MACCTL, macctl); 1863 1864 /* restore operational mode */ 1865 //AE_WRITE(sc, CSR_OPMODE, opmode); 1866 AE_BARRIER(sc); 1867 } 1868 1869 /* 1870 * ae_mii_readreg: 1871 * 1872 * Read a PHY register. 1873 */ 1874 static int 1875 ae_mii_readreg(device_t self, int phy, int reg) 1876 { 1877 struct ae_softc *sc = device_private(self); 1878 uint32_t addr; 1879 int i; 1880 1881 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1882 AE_WRITE(sc, CSR_MIIADDR, addr); 1883 AE_BARRIER(sc); 1884 for (i = 0; i < 100000000; i++) { 1885 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1886 break; 1887 } 1888 1889 return (AE_READ(sc, CSR_MIIDATA) & 0xffff); 1890 } 1891 1892 /* 1893 * ae_mii_writereg: 1894 * 1895 * Write a PHY register. 1896 */ 1897 static void 1898 ae_mii_writereg(device_t self, int phy, int reg, int val) 1899 { 1900 struct ae_softc *sc = device_private(self); 1901 uint32_t addr; 1902 int i; 1903 1904 /* write the data register */ 1905 AE_WRITE(sc, CSR_MIIDATA, val); 1906 1907 /* write the address to latch it in */ 1908 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1909 MIIADDR_WRITE; 1910 AE_WRITE(sc, CSR_MIIADDR, addr); 1911 AE_BARRIER(sc); 1912 1913 for (i = 0; i < 100000000; i++) { 1914 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1915 break; 1916 } 1917 } 1918
Indexes created Fri Sep 26 20:09:58 GMT 2025