if_ae.c revision 1.29
1 /* $Id: if_ae.c,v 1.29 2016/12/08 01:12:00 ozaki-r Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the onboard ethernet MAC found on the AR5312 74 * chip's AHB bus. 75 * 76 * This device is very simliar to the tulip in most regards, and 77 * the code is directly derived from NetBSD's tulip.c. However, it 78 * is different enough that it did not seem to be a good idea to 79 * add further complexity to the tulip driver, so we have our own. 80 * 81 * Also tulip has a lot of complexity in it for various parts/options 82 * that we don't need, and on these little boxes with only ~8MB RAM, we 83 * don't want any extra bloat. 84 */ 85 86 /* 87 * TODO: 88 * 89 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 90 * inbound packets on a half-word boundary, which would make life easier 91 * for TCP/IP. (Aligning IP headers on a word.) 92 * 93 * 2) There is stuff in original tulip to shut down the device when reacting 94 * to a a change in link status. Is that needed. 95 * 96 * 3) Test with variety of 10/100 HDX/FDX scenarios. 97 * 98 */ 99 100 #include <sys/cdefs.h> 101 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.29 2016/12/08 01:12:00 ozaki-r Exp $"); 102 103 104 #include <sys/param.h> 105 #include <sys/bus.h> 106 #include <sys/callout.h> 107 #include <sys/device.h> 108 #include <sys/endian.h> 109 #include <sys/errno.h> 110 #include <sys/intr.h> 111 #include <sys/ioctl.h> 112 #include <sys/kernel.h> 113 #include <sys/malloc.h> 114 #include <sys/mbuf.h> 115 #include <sys/socket.h> 116 117 #include <uvm/uvm_extern.h> 118 119 #include <net/if.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/if_ether.h> 123 124 #include <net/bpf.h> 125 126 #include <dev/mii/mii.h> 127 #include <dev/mii/miivar.h> 128 #include <dev/mii/mii_bitbang.h> 129 130 #include <mips/atheros/include/arbusvar.h> 131 #include <mips/atheros/dev/aereg.h> 132 #include <mips/atheros/dev/aevar.h> 133 134 static const struct { 135 u_int32_t txth_opmode; /* OPMODE bits */ 136 const char *txth_name; /* name of mode */ 137 } ae_txthresh[] = { 138 { OPMODE_TR_32, "32 words" }, 139 { OPMODE_TR_64, "64 words" }, 140 { OPMODE_TR_128, "128 words" }, 141 { OPMODE_TR_256, "256 words" }, 142 { OPMODE_SF, "store and forward mode" }, 143 { 0, NULL }, 144 }; 145 146 static int ae_match(device_t, struct cfdata *, void *); 147 static void ae_attach(device_t, device_t, void *); 148 static int ae_detach(device_t, int); 149 static int ae_activate(device_t, enum devact); 150 151 static int ae_ifflags_cb(struct ethercom *); 152 static void ae_reset(struct ae_softc *); 153 static void ae_idle(struct ae_softc *, u_int32_t); 154 155 static void ae_start(struct ifnet *); 156 static void ae_watchdog(struct ifnet *); 157 static int ae_ioctl(struct ifnet *, u_long, void *); 158 static int ae_init(struct ifnet *); 159 static void ae_stop(struct ifnet *, int); 160 161 static void ae_shutdown(void *); 162 163 static void ae_rxdrain(struct ae_softc *); 164 static int ae_add_rxbuf(struct ae_softc *, int); 165 166 static int ae_enable(struct ae_softc *); 167 static void ae_disable(struct ae_softc *); 168 static void ae_power(int, void *); 169 170 static void ae_filter_setup(struct ae_softc *); 171 172 static int ae_intr(void *); 173 static void ae_rxintr(struct ae_softc *); 174 static void ae_txintr(struct ae_softc *); 175 176 static void ae_mii_tick(void *); 177 static void ae_mii_statchg(struct ifnet *); 178 179 static int ae_mii_readreg(device_t, int, int); 180 static void ae_mii_writereg(device_t, int, int, int); 181 182 #ifdef AE_DEBUG 183 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 184 printf x 185 #else 186 #define DPRINTF(sc, x) /* nothing */ 187 #endif 188 189 #ifdef AE_STATS 190 static void ae_print_stats(struct ae_softc *); 191 #endif 192 193 CFATTACH_DECL_NEW(ae, sizeof(struct ae_softc), 194 ae_match, ae_attach, ae_detach, ae_activate); 195 196 /* 197 * ae_match: 198 * 199 * Check for a device match. 200 */ 201 int 202 ae_match(device_t parent, struct cfdata *cf, void *aux) 203 { 204 struct arbus_attach_args *aa = aux; 205 206 if (strcmp(aa->aa_name, cf->cf_name) == 0) 207 return 1; 208 209 return 0; 210 211 } 212 213 /* 214 * ae_attach: 215 * 216 * Attach an ae interface to the system. 217 */ 218 void 219 ae_attach(device_t parent, device_t self, void *aux) 220 { 221 const uint8_t *enaddr; 222 prop_data_t ea; 223 struct ae_softc *sc = device_private(self); 224 struct arbus_attach_args *aa = aux; 225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 226 int i, error; 227 228 sc->sc_dev = self; 229 230 callout_init(&sc->sc_tick_callout, 0); 231 232 printf(": Atheros AR531X 10/100 Ethernet\n"); 233 234 /* 235 * Try to get MAC address. 236 */ 237 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-address"); 238 if (ea == NULL) { 239 printf("%s: unable to get mac-addr property\n", 240 device_xname(sc->sc_dev)); 241 return; 242 } 243 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 244 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 245 enaddr = prop_data_data_nocopy(ea); 246 247 /* Announce ourselves. */ 248 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 249 ether_sprintf(enaddr)); 250 251 sc->sc_cirq = aa->aa_cirq; 252 sc->sc_mirq = aa->aa_mirq; 253 sc->sc_st = aa->aa_bst; 254 sc->sc_dmat = aa->aa_dmat; 255 256 SIMPLEQ_INIT(&sc->sc_txfreeq); 257 SIMPLEQ_INIT(&sc->sc_txdirtyq); 258 259 /* 260 * Map registers. 261 */ 262 sc->sc_size = aa->aa_size; 263 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 264 &sc->sc_sh)) != 0) { 265 printf("%s: unable to map registers, error = %d\n", 266 device_xname(sc->sc_dev), error); 267 goto fail_0; 268 } 269 270 /* 271 * Allocate the control data structures, and create and load the 272 * DMA map for it. 273 */ 274 if ((error = bus_dmamem_alloc(sc->sc_dmat, 275 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 276 1, &sc->sc_cdnseg, 0)) != 0) { 277 printf("%s: unable to allocate control data, error = %d\n", 278 device_xname(sc->sc_dev), error); 279 goto fail_1; 280 } 281 282 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 283 sizeof(struct ae_control_data), (void **)&sc->sc_control_data, 284 BUS_DMA_COHERENT)) != 0) { 285 printf("%s: unable to map control data, error = %d\n", 286 device_xname(sc->sc_dev), error); 287 goto fail_2; 288 } 289 290 if ((error = bus_dmamap_create(sc->sc_dmat, 291 sizeof(struct ae_control_data), 1, 292 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 293 printf("%s: unable to create control data DMA map, " 294 "error = %d\n", device_xname(sc->sc_dev), error); 295 goto fail_3; 296 } 297 298 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 299 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 300 0)) != 0) { 301 printf("%s: unable to load control data DMA map, error = %d\n", 302 device_xname(sc->sc_dev), error); 303 goto fail_4; 304 } 305 306 /* 307 * Create the transmit buffer DMA maps. 308 */ 309 for (i = 0; i < AE_TXQUEUELEN; i++) { 310 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 311 AE_NTXSEGS, MCLBYTES, 0, 0, 312 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 313 printf("%s: unable to create tx DMA map %d, " 314 "error = %d\n", device_xname(sc->sc_dev), i, error); 315 goto fail_5; 316 } 317 } 318 319 /* 320 * Create the receive buffer DMA maps. 321 */ 322 for (i = 0; i < AE_NRXDESC; i++) { 323 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 324 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 325 printf("%s: unable to create rx DMA map %d, " 326 "error = %d\n", device_xname(sc->sc_dev), i, error); 327 goto fail_6; 328 } 329 sc->sc_rxsoft[i].rxs_mbuf = NULL; 330 } 331 332 /* 333 * Reset the chip to a known state. 334 */ 335 ae_reset(sc); 336 337 /* 338 * From this point forward, the attachment cannot fail. A failure 339 * before this point releases all resources that may have been 340 * allocated. 341 */ 342 sc->sc_flags |= AE_ATTACHED; 343 344 /* 345 * Initialize our media structures. This may probe the MII, if 346 * present. 347 */ 348 sc->sc_mii.mii_ifp = ifp; 349 sc->sc_mii.mii_readreg = ae_mii_readreg; 350 sc->sc_mii.mii_writereg = ae_mii_writereg; 351 sc->sc_mii.mii_statchg = ae_mii_statchg; 352 sc->sc_ethercom.ec_mii = &sc->sc_mii; 353 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 354 ether_mediastatus); 355 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 356 MII_OFFSET_ANY, 0); 357 358 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 359 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 360 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 361 } else 362 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 363 364 sc->sc_tick = ae_mii_tick; 365 366 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 sc->sc_if_flags = ifp->if_flags; 370 ifp->if_ioctl = ae_ioctl; 371 ifp->if_start = ae_start; 372 ifp->if_watchdog = ae_watchdog; 373 ifp->if_init = ae_init; 374 ifp->if_stop = ae_stop; 375 IFQ_SET_READY(&ifp->if_snd); 376 377 /* 378 * We can support 802.1Q VLAN-sized frames. 379 */ 380 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 381 382 /* 383 * Attach the interface. 384 */ 385 if_attach(ifp); 386 if_deferred_start_init(ifp, NULL); 387 ether_ifattach(ifp, enaddr); 388 ether_set_ifflags_cb(&sc->sc_ethercom, ae_ifflags_cb); 389 390 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 391 RND_TYPE_NET, RND_FLAG_DEFAULT); 392 393 /* 394 * Make sure the interface is shutdown during reboot. 395 */ 396 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 397 if (sc->sc_sdhook == NULL) 398 printf("%s: WARNING: unable to establish shutdown hook\n", 399 device_xname(sc->sc_dev)); 400 401 /* 402 * Add a suspend hook to make sure we come back up after a 403 * resume. 404 */ 405 sc->sc_powerhook = powerhook_establish(device_xname(sc->sc_dev), 406 ae_power, sc); 407 if (sc->sc_powerhook == NULL) 408 printf("%s: WARNING: unable to establish power hook\n", 409 device_xname(sc->sc_dev)); 410 return; 411 412 /* 413 * Free any resources we've allocated during the failed attach 414 * attempt. Do this in reverse order and fall through. 415 */ 416 fail_6: 417 for (i = 0; i < AE_NRXDESC; i++) { 418 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 419 bus_dmamap_destroy(sc->sc_dmat, 420 sc->sc_rxsoft[i].rxs_dmamap); 421 } 422 fail_5: 423 for (i = 0; i < AE_TXQUEUELEN; i++) { 424 if (sc->sc_txsoft[i].txs_dmamap != NULL) 425 bus_dmamap_destroy(sc->sc_dmat, 426 sc->sc_txsoft[i].txs_dmamap); 427 } 428 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 429 fail_4: 430 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 431 fail_3: 432 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 433 sizeof(struct ae_control_data)); 434 fail_2: 435 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 436 fail_1: 437 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 438 fail_0: 439 return; 440 } 441 442 /* 443 * ae_activate: 444 * 445 * Handle device activation/deactivation requests. 446 */ 447 int 448 ae_activate(device_t self, enum devact act) 449 { 450 struct ae_softc *sc = device_private(self); 451 452 switch (act) { 453 case DVACT_DEACTIVATE: 454 if_deactivate(&sc->sc_ethercom.ec_if); 455 return 0; 456 default: 457 return EOPNOTSUPP; 458 } 459 } 460 461 /* 462 * ae_detach: 463 * 464 * Detach a device interface. 465 */ 466 int 467 ae_detach(device_t self, int flags) 468 { 469 struct ae_softc *sc = device_private(self); 470 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 471 struct ae_rxsoft *rxs; 472 struct ae_txsoft *txs; 473 int i; 474 475 /* 476 * Succeed now if there isn't any work to do. 477 */ 478 if ((sc->sc_flags & AE_ATTACHED) == 0) 479 return (0); 480 481 /* Unhook our tick handler. */ 482 if (sc->sc_tick) 483 callout_stop(&sc->sc_tick_callout); 484 485 /* Detach all PHYs */ 486 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 487 488 /* Delete all remaining media. */ 489 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 490 491 rnd_detach_source(&sc->sc_rnd_source); 492 ether_ifdetach(ifp); 493 if_detach(ifp); 494 495 for (i = 0; i < AE_NRXDESC; i++) { 496 rxs = &sc->sc_rxsoft[i]; 497 if (rxs->rxs_mbuf != NULL) { 498 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 499 m_freem(rxs->rxs_mbuf); 500 rxs->rxs_mbuf = NULL; 501 } 502 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 503 } 504 for (i = 0; i < AE_TXQUEUELEN; i++) { 505 txs = &sc->sc_txsoft[i]; 506 if (txs->txs_mbuf != NULL) { 507 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 508 m_freem(txs->txs_mbuf); 509 txs->txs_mbuf = NULL; 510 } 511 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 512 } 513 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 514 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 515 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 516 sizeof(struct ae_control_data)); 517 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 518 519 shutdownhook_disestablish(sc->sc_sdhook); 520 powerhook_disestablish(sc->sc_powerhook); 521 522 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 523 524 525 return (0); 526 } 527 528 /* 529 * ae_shutdown: 530 * 531 * Make sure the interface is stopped at reboot time. 532 */ 533 static void 534 ae_shutdown(void *arg) 535 { 536 struct ae_softc *sc = arg; 537 538 ae_stop(&sc->sc_ethercom.ec_if, 1); 539 } 540 541 /* 542 * ae_start: [ifnet interface function] 543 * 544 * Start packet transmission on the interface. 545 */ 546 static void 547 ae_start(struct ifnet *ifp) 548 { 549 struct ae_softc *sc = ifp->if_softc; 550 struct mbuf *m0, *m; 551 struct ae_txsoft *txs; 552 bus_dmamap_t dmamap; 553 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 554 555 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 556 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 557 558 559 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 560 return; 561 562 /* 563 * Remember the previous number of free descriptors and 564 * the first descriptor we'll use. 565 */ 566 ofree = sc->sc_txfree; 567 firsttx = sc->sc_txnext; 568 569 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 570 device_xname(sc->sc_dev), ofree, firsttx)); 571 572 /* 573 * Loop through the send queue, setting up transmit descriptors 574 * until we drain the queue, or use up all available transmit 575 * descriptors. 576 */ 577 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 578 sc->sc_txfree != 0) { 579 /* 580 * Grab a packet off the queue. 581 */ 582 IFQ_POLL(&ifp->if_snd, m0); 583 if (m0 == NULL) 584 break; 585 m = NULL; 586 587 dmamap = txs->txs_dmamap; 588 589 /* 590 * Load the DMA map. If this fails, the packet either 591 * didn't fit in the alloted number of segments, or we were 592 * short on resources. In this case, we'll copy and try 593 * again. 594 */ 595 if (((mtod(m0, uintptr_t) & 3) != 0) || 596 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 597 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 598 MGETHDR(m, M_DONTWAIT, MT_DATA); 599 if (m == NULL) { 600 printf("%s: unable to allocate Tx mbuf\n", 601 device_xname(sc->sc_dev)); 602 break; 603 } 604 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 605 if (m0->m_pkthdr.len > MHLEN) { 606 MCLGET(m, M_DONTWAIT); 607 if ((m->m_flags & M_EXT) == 0) { 608 printf("%s: unable to allocate Tx " 609 "cluster\n", device_xname(sc->sc_dev)); 610 m_freem(m); 611 break; 612 } 613 } 614 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 615 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 616 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 617 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 618 if (error) { 619 printf("%s: unable to load Tx buffer, " 620 "error = %d\n", device_xname(sc->sc_dev), 621 error); 622 break; 623 } 624 } 625 626 /* 627 * Ensure we have enough descriptors free to describe 628 * the packet. 629 */ 630 if (dmamap->dm_nsegs > sc->sc_txfree) { 631 /* 632 * Not enough free descriptors to transmit this 633 * packet. We haven't committed to anything yet, 634 * so just unload the DMA map, put the packet 635 * back on the queue, and punt. Notify the upper 636 * layer that there are no more slots left. 637 * 638 * XXX We could allocate an mbuf and copy, but 639 * XXX it is worth it? 640 */ 641 ifp->if_flags |= IFF_OACTIVE; 642 bus_dmamap_unload(sc->sc_dmat, dmamap); 643 if (m != NULL) 644 m_freem(m); 645 break; 646 } 647 648 IFQ_DEQUEUE(&ifp->if_snd, m0); 649 if (m != NULL) { 650 m_freem(m0); 651 m0 = m; 652 } 653 654 /* 655 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 656 */ 657 658 /* Sync the DMA map. */ 659 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 660 BUS_DMASYNC_PREWRITE); 661 662 /* 663 * Initialize the transmit descriptors. 664 */ 665 for (nexttx = sc->sc_txnext, seg = 0; 666 seg < dmamap->dm_nsegs; 667 seg++, nexttx = AE_NEXTTX(nexttx)) { 668 /* 669 * If this is the first descriptor we're 670 * enqueueing, don't set the OWN bit just 671 * yet. That could cause a race condition. 672 * We'll do it below. 673 */ 674 sc->sc_txdescs[nexttx].ad_status = 675 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 676 sc->sc_txdescs[nexttx].ad_bufaddr1 = 677 dmamap->dm_segs[seg].ds_addr; 678 sc->sc_txdescs[nexttx].ad_ctl = 679 (dmamap->dm_segs[seg].ds_len << 680 ADCTL_SIZE1_SHIFT) | 681 (nexttx == (AE_NTXDESC - 1) ? 682 ADCTL_ER : 0); 683 lasttx = nexttx; 684 } 685 686 KASSERT(lasttx != -1); 687 688 /* Set `first segment' and `last segment' appropriately. */ 689 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 690 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 691 692 #ifdef AE_DEBUG 693 if (ifp->if_flags & IFF_DEBUG) { 694 printf(" txsoft %p transmit chain:\n", txs); 695 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 696 printf(" descriptor %d:\n", seg); 697 printf(" ad_status: 0x%08x\n", 698 sc->sc_txdescs[seg].ad_status); 699 printf(" ad_ctl: 0x%08x\n", 700 sc->sc_txdescs[seg].ad_ctl); 701 printf(" ad_bufaddr1: 0x%08x\n", 702 sc->sc_txdescs[seg].ad_bufaddr1); 703 printf(" ad_bufaddr2: 0x%08x\n", 704 sc->sc_txdescs[seg].ad_bufaddr2); 705 if (seg == lasttx) 706 break; 707 } 708 } 709 #endif 710 711 /* Sync the descriptors we're using. */ 712 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 713 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 714 715 /* 716 * Store a pointer to the packet so we can free it later, 717 * and remember what txdirty will be once the packet is 718 * done. 719 */ 720 txs->txs_mbuf = m0; 721 txs->txs_firstdesc = sc->sc_txnext; 722 txs->txs_lastdesc = lasttx; 723 txs->txs_ndescs = dmamap->dm_nsegs; 724 725 /* Advance the tx pointer. */ 726 sc->sc_txfree -= dmamap->dm_nsegs; 727 sc->sc_txnext = nexttx; 728 729 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 730 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 731 732 /* 733 * Pass the packet to any BPF listeners. 734 */ 735 bpf_mtap(ifp, m0); 736 } 737 738 if (txs == NULL || sc->sc_txfree == 0) { 739 /* No more slots left; notify upper layer. */ 740 ifp->if_flags |= IFF_OACTIVE; 741 } 742 743 if (sc->sc_txfree != ofree) { 744 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 745 device_xname(sc->sc_dev), lasttx, firsttx)); 746 /* 747 * Cause a transmit interrupt to happen on the 748 * last packet we enqueued. 749 */ 750 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 751 AE_CDTXSYNC(sc, lasttx, 1, 752 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 753 754 /* 755 * The entire packet chain is set up. Give the 756 * first descriptor to the chip now. 757 */ 758 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 759 AE_CDTXSYNC(sc, firsttx, 1, 760 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 761 762 /* Wake up the transmitter. */ 763 /* XXX USE AUTOPOLLING? */ 764 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 765 AE_BARRIER(sc); 766 767 /* Set a watchdog timer in case the chip flakes out. */ 768 ifp->if_timer = 5; 769 } 770 } 771 772 /* 773 * ae_watchdog: [ifnet interface function] 774 * 775 * Watchdog timer handler. 776 */ 777 static void 778 ae_watchdog(struct ifnet *ifp) 779 { 780 struct ae_softc *sc = ifp->if_softc; 781 int doing_transmit; 782 783 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 784 785 if (doing_transmit) { 786 printf("%s: transmit timeout\n", device_xname(sc->sc_dev)); 787 ifp->if_oerrors++; 788 } 789 else 790 printf("%s: spurious watchdog timeout\n", device_xname(sc->sc_dev)); 791 792 (void) ae_init(ifp); 793 794 /* Try to get more packets going. */ 795 ae_start(ifp); 796 } 797 798 /* If the interface is up and running, only modify the receive 799 * filter when changing to/from promiscuous mode. Otherwise return 800 * ENETRESET so that ether_ioctl will reset the chip. 801 */ 802 static int 803 ae_ifflags_cb(struct ethercom *ec) 804 { 805 struct ifnet *ifp = &ec->ec_if; 806 struct ae_softc *sc = ifp->if_softc; 807 int change = ifp->if_flags ^ sc->sc_if_flags; 808 809 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 810 return ENETRESET; 811 else if ((change & IFF_PROMISC) != 0) 812 ae_filter_setup(sc); 813 return 0; 814 } 815 816 /* 817 * ae_ioctl: [ifnet interface function] 818 * 819 * Handle control requests from the operator. 820 */ 821 static int 822 ae_ioctl(struct ifnet *ifp, u_long cmd, void *data) 823 { 824 struct ae_softc *sc = ifp->if_softc; 825 int s, error; 826 827 s = splnet(); 828 829 error = ether_ioctl(ifp, cmd, data); 830 if (error == ENETRESET) { 831 if (ifp->if_flags & IFF_RUNNING) { 832 /* 833 * Multicast list has changed. Set the 834 * hardware filter accordingly. 835 */ 836 ae_filter_setup(sc); 837 } 838 error = 0; 839 } 840 841 /* Try to get more packets going. */ 842 if (AE_IS_ENABLED(sc)) 843 ae_start(ifp); 844 845 sc->sc_if_flags = ifp->if_flags; 846 splx(s); 847 return (error); 848 } 849 850 /* 851 * ae_intr: 852 * 853 * Interrupt service routine. 854 */ 855 int 856 ae_intr(void *arg) 857 { 858 struct ae_softc *sc = arg; 859 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 860 u_int32_t status, rxstatus, txstatus; 861 int handled = 0, txthresh; 862 863 DPRINTF(sc, ("%s: ae_intr\n", device_xname(sc->sc_dev))); 864 865 #ifdef DEBUG 866 if (AE_IS_ENABLED(sc) == 0) 867 panic("%s: ae_intr: not enabled", device_xname(sc->sc_dev)); 868 #endif 869 870 /* 871 * If the interface isn't running, the interrupt couldn't 872 * possibly have come from us. 873 */ 874 if ((ifp->if_flags & IFF_RUNNING) == 0 || 875 !device_is_active(sc->sc_dev)) { 876 printf("spurious?!?\n"); 877 return (0); 878 } 879 880 for (;;) { 881 status = AE_READ(sc, CSR_STATUS); 882 if (status) { 883 AE_WRITE(sc, CSR_STATUS, status); 884 AE_BARRIER(sc); 885 } 886 887 if ((status & sc->sc_inten) == 0) 888 break; 889 890 handled = 1; 891 892 rxstatus = status & sc->sc_rxint_mask; 893 txstatus = status & sc->sc_txint_mask; 894 895 if (rxstatus) { 896 /* Grab new any new packets. */ 897 ae_rxintr(sc); 898 899 if (rxstatus & STATUS_RU) { 900 printf("%s: receive ring overrun\n", 901 device_xname(sc->sc_dev)); 902 /* Get the receive process going again. */ 903 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 904 AE_BARRIER(sc); 905 break; 906 } 907 } 908 909 if (txstatus) { 910 /* Sweep up transmit descriptors. */ 911 ae_txintr(sc); 912 913 if (txstatus & STATUS_TJT) 914 printf("%s: transmit jabber timeout\n", 915 device_xname(sc->sc_dev)); 916 917 if (txstatus & STATUS_UNF) { 918 /* 919 * Increase our transmit threshold if 920 * another is available. 921 */ 922 txthresh = sc->sc_txthresh + 1; 923 if (ae_txthresh[txthresh].txth_name != NULL) { 924 uint32_t opmode; 925 /* Idle the transmit process. */ 926 opmode = AE_READ(sc, CSR_OPMODE); 927 ae_idle(sc, OPMODE_ST); 928 929 sc->sc_txthresh = txthresh; 930 opmode &= 931 ~(OPMODE_TR|OPMODE_SF); 932 opmode |= 933 ae_txthresh[txthresh].txth_opmode; 934 printf("%s: transmit underrun; new " 935 "threshold: %s\n", 936 device_xname(sc->sc_dev), 937 ae_txthresh[txthresh].txth_name); 938 939 /* 940 * Set the new threshold and restart 941 * the transmit process. 942 */ 943 AE_WRITE(sc, CSR_OPMODE, opmode); 944 AE_BARRIER(sc); 945 } 946 /* 947 * XXX Log every Nth underrun from 948 * XXX now on? 949 */ 950 } 951 } 952 953 if (status & (STATUS_TPS|STATUS_RPS)) { 954 if (status & STATUS_TPS) 955 printf("%s: transmit process stopped\n", 956 device_xname(sc->sc_dev)); 957 if (status & STATUS_RPS) 958 printf("%s: receive process stopped\n", 959 device_xname(sc->sc_dev)); 960 (void) ae_init(ifp); 961 break; 962 } 963 964 if (status & STATUS_SE) { 965 const char *str; 966 967 if (status & STATUS_TX_ABORT) 968 str = "tx abort"; 969 else if (status & STATUS_RX_ABORT) 970 str = "rx abort"; 971 else 972 str = "unknown error"; 973 974 printf("%s: fatal system error: %s\n", 975 device_xname(sc->sc_dev), str); 976 (void) ae_init(ifp); 977 break; 978 } 979 980 /* 981 * Not handled: 982 * 983 * Transmit buffer unavailable -- normal 984 * condition, nothing to do, really. 985 * 986 * General purpose timer experied -- we don't 987 * use the general purpose timer. 988 * 989 * Early receive interrupt -- not available on 990 * all chips, we just use RI. We also only 991 * use single-segment receive DMA, so this 992 * is mostly useless. 993 */ 994 } 995 996 /* Try to get more packets going. */ 997 if_schedule_deferred_start(ifp); 998 999 if (handled) 1000 rnd_add_uint32(&sc->sc_rnd_source, status); 1001 return (handled); 1002 } 1003 1004 /* 1005 * ae_rxintr: 1006 * 1007 * Helper; handle receive interrupts. 1008 */ 1009 static void 1010 ae_rxintr(struct ae_softc *sc) 1011 { 1012 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1013 struct ae_rxsoft *rxs; 1014 struct mbuf *m; 1015 u_int32_t rxstat; 1016 int i, len; 1017 1018 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1019 rxs = &sc->sc_rxsoft[i]; 1020 1021 AE_CDRXSYNC(sc, i, 1022 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1023 1024 rxstat = sc->sc_rxdescs[i].ad_status; 1025 1026 if (rxstat & ADSTAT_OWN) { 1027 /* 1028 * We have processed all of the receive buffers. 1029 */ 1030 break; 1031 } 1032 1033 /* 1034 * If any collisions were seen on the wire, count one. 1035 */ 1036 if (rxstat & ADSTAT_Rx_CS) 1037 ifp->if_collisions++; 1038 1039 /* 1040 * If an error occurred, update stats, clear the status 1041 * word, and leave the packet buffer in place. It will 1042 * simply be reused the next time the ring comes around. 1043 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1044 * error. 1045 */ 1046 if (rxstat & ADSTAT_ES && 1047 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1048 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1049 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1050 #define PRINTERR(bit, str) \ 1051 if (rxstat & (bit)) \ 1052 printf("%s: receive error: %s\n", \ 1053 device_xname(sc->sc_dev), str) 1054 ifp->if_ierrors++; 1055 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1056 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1057 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1058 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1059 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1060 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1061 #undef PRINTERR 1062 AE_INIT_RXDESC(sc, i); 1063 continue; 1064 } 1065 1066 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1067 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1068 1069 /* 1070 * No errors; receive the packet. Note the chip 1071 * includes the CRC with every packet. 1072 */ 1073 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1074 1075 /* 1076 * XXX: the Atheros part can align on half words. what 1077 * is the performance implication of this? Probably 1078 * minimal, and we should use it... 1079 */ 1080 #ifdef __NO_STRICT_ALIGNMENT 1081 /* 1082 * Allocate a new mbuf cluster. If that fails, we are 1083 * out of memory, and must drop the packet and recycle 1084 * the buffer that's already attached to this descriptor. 1085 */ 1086 m = rxs->rxs_mbuf; 1087 if (ae_add_rxbuf(sc, i) != 0) { 1088 ifp->if_ierrors++; 1089 AE_INIT_RXDESC(sc, i); 1090 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1091 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1092 continue; 1093 } 1094 #else 1095 /* 1096 * The chip's receive buffers must be 4-byte aligned. 1097 * But this means that the data after the Ethernet header 1098 * is misaligned. We must allocate a new buffer and 1099 * copy the data, shifted forward 2 bytes. 1100 */ 1101 MGETHDR(m, M_DONTWAIT, MT_DATA); 1102 if (m == NULL) { 1103 dropit: 1104 ifp->if_ierrors++; 1105 AE_INIT_RXDESC(sc, i); 1106 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1107 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1108 continue; 1109 } 1110 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1111 if (len > (MHLEN - 2)) { 1112 MCLGET(m, M_DONTWAIT); 1113 if ((m->m_flags & M_EXT) == 0) { 1114 m_freem(m); 1115 goto dropit; 1116 } 1117 } 1118 m->m_data += 2; 1119 1120 /* 1121 * Note that we use clusters for incoming frames, so the 1122 * buffer is virtually contiguous. 1123 */ 1124 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 1125 1126 /* Allow the receive descriptor to continue using its mbuf. */ 1127 AE_INIT_RXDESC(sc, i); 1128 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1129 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1130 #endif /* __NO_STRICT_ALIGNMENT */ 1131 1132 ifp->if_ipackets++; 1133 m_set_rcvif(m, ifp); 1134 m->m_pkthdr.len = m->m_len = len; 1135 1136 /* 1137 * Pass this up to any BPF listeners, but only 1138 * pass it up the stack if its for us. 1139 */ 1140 bpf_mtap(ifp, m); 1141 1142 /* Pass it on. */ 1143 if_percpuq_enqueue(ifp->if_percpuq, m); 1144 } 1145 1146 /* Update the receive pointer. */ 1147 sc->sc_rxptr = i; 1148 } 1149 1150 /* 1151 * ae_txintr: 1152 * 1153 * Helper; handle transmit interrupts. 1154 */ 1155 static void 1156 ae_txintr(struct ae_softc *sc) 1157 { 1158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1159 struct ae_txsoft *txs; 1160 u_int32_t txstat; 1161 1162 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1163 device_xname(sc->sc_dev), sc->sc_flags)); 1164 1165 ifp->if_flags &= ~IFF_OACTIVE; 1166 1167 /* 1168 * Go through our Tx list and free mbufs for those 1169 * frames that have been transmitted. 1170 */ 1171 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1172 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1173 txs->txs_ndescs, 1174 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1175 1176 #ifdef AE_DEBUG 1177 if (ifp->if_flags & IFF_DEBUG) { 1178 int i; 1179 printf(" txsoft %p transmit chain:\n", txs); 1180 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1181 printf(" descriptor %d:\n", i); 1182 printf(" ad_status: 0x%08x\n", 1183 sc->sc_txdescs[i].ad_status); 1184 printf(" ad_ctl: 0x%08x\n", 1185 sc->sc_txdescs[i].ad_ctl); 1186 printf(" ad_bufaddr1: 0x%08x\n", 1187 sc->sc_txdescs[i].ad_bufaddr1); 1188 printf(" ad_bufaddr2: 0x%08x\n", 1189 sc->sc_txdescs[i].ad_bufaddr2); 1190 if (i == txs->txs_lastdesc) 1191 break; 1192 } 1193 } 1194 #endif 1195 1196 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1197 if (txstat & ADSTAT_OWN) 1198 break; 1199 1200 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1201 1202 sc->sc_txfree += txs->txs_ndescs; 1203 1204 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1205 0, txs->txs_dmamap->dm_mapsize, 1206 BUS_DMASYNC_POSTWRITE); 1207 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1208 m_freem(txs->txs_mbuf); 1209 txs->txs_mbuf = NULL; 1210 1211 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1212 1213 /* 1214 * Check for errors and collisions. 1215 */ 1216 #ifdef AE_STATS 1217 if (txstat & ADSTAT_Tx_UF) 1218 sc->sc_stats.ts_tx_uf++; 1219 if (txstat & ADSTAT_Tx_TO) 1220 sc->sc_stats.ts_tx_to++; 1221 if (txstat & ADSTAT_Tx_EC) 1222 sc->sc_stats.ts_tx_ec++; 1223 if (txstat & ADSTAT_Tx_LC) 1224 sc->sc_stats.ts_tx_lc++; 1225 #endif 1226 1227 if (txstat & (ADSTAT_Tx_UF|ADSTAT_Tx_TO)) 1228 ifp->if_oerrors++; 1229 1230 if (txstat & ADSTAT_Tx_EC) 1231 ifp->if_collisions += 16; 1232 else 1233 ifp->if_collisions += ADSTAT_Tx_COLLISIONS(txstat); 1234 if (txstat & ADSTAT_Tx_LC) 1235 ifp->if_collisions++; 1236 1237 ifp->if_opackets++; 1238 } 1239 1240 /* 1241 * If there are no more pending transmissions, cancel the watchdog 1242 * timer. 1243 */ 1244 if (txs == NULL) 1245 ifp->if_timer = 0; 1246 } 1247 1248 #ifdef AE_STATS 1249 void 1250 ae_print_stats(struct ae_softc *sc) 1251 { 1252 1253 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1254 device_xname(sc->sc_dev), 1255 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1256 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1257 } 1258 #endif 1259 1260 /* 1261 * ae_reset: 1262 * 1263 * Perform a soft reset on the chip. 1264 */ 1265 void 1266 ae_reset(struct ae_softc *sc) 1267 { 1268 int i; 1269 1270 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1271 AE_BARRIER(sc); 1272 1273 /* 1274 * The chip doesn't take itself out of reset automatically. 1275 * We need to do so after 2us. 1276 */ 1277 delay(10); 1278 AE_WRITE(sc, CSR_BUSMODE, 0); 1279 AE_BARRIER(sc); 1280 1281 for (i = 0; i < 1000; i++) { 1282 /* 1283 * Wait a bit for the reset to complete before peeking 1284 * at the chip again. 1285 */ 1286 delay(10); 1287 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1288 break; 1289 } 1290 1291 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1292 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 1293 1294 delay(1000); 1295 } 1296 1297 /* 1298 * ae_init: [ ifnet interface function ] 1299 * 1300 * Initialize the interface. Must be called at splnet(). 1301 */ 1302 static int 1303 ae_init(struct ifnet *ifp) 1304 { 1305 struct ae_softc *sc = ifp->if_softc; 1306 struct ae_txsoft *txs; 1307 struct ae_rxsoft *rxs; 1308 const uint8_t *enaddr; 1309 int i, error = 0; 1310 1311 if ((error = ae_enable(sc)) != 0) 1312 goto out; 1313 1314 /* 1315 * Cancel any pending I/O. 1316 */ 1317 ae_stop(ifp, 0); 1318 1319 /* 1320 * Reset the chip to a known state. 1321 */ 1322 ae_reset(sc); 1323 1324 /* 1325 * Initialize the BUSMODE register. 1326 */ 1327 AE_WRITE(sc, CSR_BUSMODE, 1328 /* XXX: not sure if this is a good thing or not... */ 1329 //BUSMODE_ALIGN_16B | 1330 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1331 AE_BARRIER(sc); 1332 1333 /* 1334 * Initialize the transmit descriptor ring. 1335 */ 1336 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1337 for (i = 0; i < AE_NTXDESC; i++) { 1338 sc->sc_txdescs[i].ad_ctl = 0; 1339 sc->sc_txdescs[i].ad_bufaddr2 = 1340 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1341 } 1342 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1343 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1344 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1345 sc->sc_txfree = AE_NTXDESC; 1346 sc->sc_txnext = 0; 1347 1348 /* 1349 * Initialize the transmit job descriptors. 1350 */ 1351 SIMPLEQ_INIT(&sc->sc_txfreeq); 1352 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1353 for (i = 0; i < AE_TXQUEUELEN; i++) { 1354 txs = &sc->sc_txsoft[i]; 1355 txs->txs_mbuf = NULL; 1356 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1357 } 1358 1359 /* 1360 * Initialize the receive descriptor and receive job 1361 * descriptor rings. 1362 */ 1363 for (i = 0; i < AE_NRXDESC; i++) { 1364 rxs = &sc->sc_rxsoft[i]; 1365 if (rxs->rxs_mbuf == NULL) { 1366 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1367 printf("%s: unable to allocate or map rx " 1368 "buffer %d, error = %d\n", 1369 device_xname(sc->sc_dev), i, error); 1370 /* 1371 * XXX Should attempt to run with fewer receive 1372 * XXX buffers instead of just failing. 1373 */ 1374 ae_rxdrain(sc); 1375 goto out; 1376 } 1377 } else 1378 AE_INIT_RXDESC(sc, i); 1379 } 1380 sc->sc_rxptr = 0; 1381 1382 /* 1383 * Initialize the interrupt mask and enable interrupts. 1384 */ 1385 /* normal interrupts */ 1386 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1387 1388 /* abnormal interrupts */ 1389 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1390 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1391 1392 sc->sc_rxint_mask = STATUS_RI|STATUS_RU; 1393 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT; 1394 1395 sc->sc_rxint_mask &= sc->sc_inten; 1396 sc->sc_txint_mask &= sc->sc_inten; 1397 1398 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1399 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1400 1401 /* 1402 * Give the transmit and receive rings to the chip. 1403 */ 1404 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1405 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1406 AE_BARRIER(sc); 1407 1408 /* 1409 * Set the station address. 1410 */ 1411 enaddr = CLLADDR(ifp->if_sadl); 1412 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1413 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1414 enaddr[1] << 8 | enaddr[0]); 1415 AE_BARRIER(sc); 1416 1417 /* 1418 * Set the receive filter. This will start the transmit and 1419 * receive processes. 1420 */ 1421 ae_filter_setup(sc); 1422 1423 /* 1424 * Set the current media. 1425 */ 1426 if ((error = ether_mediachange(ifp)) != 0) 1427 goto out; 1428 1429 /* 1430 * Start the mac. 1431 */ 1432 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1433 AE_BARRIER(sc); 1434 1435 /* 1436 * Write out the opmode. 1437 */ 1438 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1439 ae_txthresh[sc->sc_txthresh].txth_opmode); 1440 /* 1441 * Start the receive process. 1442 */ 1443 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1444 AE_BARRIER(sc); 1445 1446 if (sc->sc_tick != NULL) { 1447 /* Start the one second clock. */ 1448 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1449 } 1450 1451 /* 1452 * Note that the interface is now running. 1453 */ 1454 ifp->if_flags |= IFF_RUNNING; 1455 ifp->if_flags &= ~IFF_OACTIVE; 1456 sc->sc_if_flags = ifp->if_flags; 1457 1458 out: 1459 if (error) { 1460 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1461 ifp->if_timer = 0; 1462 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1463 } 1464 return (error); 1465 } 1466 1467 /* 1468 * ae_enable: 1469 * 1470 * Enable the chip. 1471 */ 1472 static int 1473 ae_enable(struct ae_softc *sc) 1474 { 1475 1476 if (AE_IS_ENABLED(sc) == 0) { 1477 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1478 ae_intr, sc); 1479 if (sc->sc_ih == NULL) { 1480 printf("%s: unable to establish interrupt\n", 1481 device_xname(sc->sc_dev)); 1482 return (EIO); 1483 } 1484 sc->sc_flags |= AE_ENABLED; 1485 } 1486 return (0); 1487 } 1488 1489 /* 1490 * ae_disable: 1491 * 1492 * Disable the chip. 1493 */ 1494 static void 1495 ae_disable(struct ae_softc *sc) 1496 { 1497 1498 if (AE_IS_ENABLED(sc)) { 1499 arbus_intr_disestablish(sc->sc_ih); 1500 sc->sc_flags &= ~AE_ENABLED; 1501 } 1502 } 1503 1504 /* 1505 * ae_power: 1506 * 1507 * Power management (suspend/resume) hook. 1508 */ 1509 static void 1510 ae_power(int why, void *arg) 1511 { 1512 struct ae_softc *sc = arg; 1513 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1514 int s; 1515 1516 printf("power called: %d, %x\n", why, (uint32_t)arg); 1517 s = splnet(); 1518 switch (why) { 1519 case PWR_STANDBY: 1520 /* do nothing! */ 1521 break; 1522 case PWR_SUSPEND: 1523 ae_stop(ifp, 0); 1524 ae_disable(sc); 1525 break; 1526 case PWR_RESUME: 1527 if (ifp->if_flags & IFF_UP) { 1528 ae_enable(sc); 1529 ae_init(ifp); 1530 } 1531 break; 1532 case PWR_SOFTSUSPEND: 1533 case PWR_SOFTSTANDBY: 1534 case PWR_SOFTRESUME: 1535 break; 1536 } 1537 splx(s); 1538 } 1539 1540 /* 1541 * ae_rxdrain: 1542 * 1543 * Drain the receive queue. 1544 */ 1545 static void 1546 ae_rxdrain(struct ae_softc *sc) 1547 { 1548 struct ae_rxsoft *rxs; 1549 int i; 1550 1551 for (i = 0; i < AE_NRXDESC; i++) { 1552 rxs = &sc->sc_rxsoft[i]; 1553 if (rxs->rxs_mbuf != NULL) { 1554 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1555 m_freem(rxs->rxs_mbuf); 1556 rxs->rxs_mbuf = NULL; 1557 } 1558 } 1559 } 1560 1561 /* 1562 * ae_stop: [ ifnet interface function ] 1563 * 1564 * Stop transmission on the interface. 1565 */ 1566 static void 1567 ae_stop(struct ifnet *ifp, int disable) 1568 { 1569 struct ae_softc *sc = ifp->if_softc; 1570 struct ae_txsoft *txs; 1571 1572 if (sc->sc_tick != NULL) { 1573 /* Stop the one second clock. */ 1574 callout_stop(&sc->sc_tick_callout); 1575 } 1576 1577 /* Down the MII. */ 1578 mii_down(&sc->sc_mii); 1579 1580 /* Disable interrupts. */ 1581 AE_WRITE(sc, CSR_INTEN, 0); 1582 1583 /* Stop the transmit and receive processes. */ 1584 AE_WRITE(sc, CSR_OPMODE, 0); 1585 AE_WRITE(sc, CSR_RXLIST, 0); 1586 AE_WRITE(sc, CSR_TXLIST, 0); 1587 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1588 AE_BARRIER(sc); 1589 1590 /* 1591 * Release any queued transmit buffers. 1592 */ 1593 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1594 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1595 if (txs->txs_mbuf != NULL) { 1596 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1597 m_freem(txs->txs_mbuf); 1598 txs->txs_mbuf = NULL; 1599 } 1600 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1601 } 1602 1603 /* 1604 * Mark the interface down and cancel the watchdog timer. 1605 */ 1606 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1607 sc->sc_if_flags = ifp->if_flags; 1608 ifp->if_timer = 0; 1609 1610 if (disable) { 1611 ae_rxdrain(sc); 1612 ae_disable(sc); 1613 } 1614 1615 /* 1616 * Reset the chip (needed on some flavors to actually disable it). 1617 */ 1618 ae_reset(sc); 1619 } 1620 1621 /* 1622 * ae_add_rxbuf: 1623 * 1624 * Add a receive buffer to the indicated descriptor. 1625 */ 1626 static int 1627 ae_add_rxbuf(struct ae_softc *sc, int idx) 1628 { 1629 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1630 struct mbuf *m; 1631 int error; 1632 1633 MGETHDR(m, M_DONTWAIT, MT_DATA); 1634 if (m == NULL) 1635 return (ENOBUFS); 1636 1637 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1638 MCLGET(m, M_DONTWAIT); 1639 if ((m->m_flags & M_EXT) == 0) { 1640 m_freem(m); 1641 return (ENOBUFS); 1642 } 1643 1644 if (rxs->rxs_mbuf != NULL) 1645 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1646 1647 rxs->rxs_mbuf = m; 1648 1649 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1650 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1651 BUS_DMA_READ|BUS_DMA_NOWAIT); 1652 if (error) { 1653 printf("%s: can't load rx DMA map %d, error = %d\n", 1654 device_xname(sc->sc_dev), idx, error); 1655 panic("ae_add_rxbuf"); /* XXX */ 1656 } 1657 1658 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1659 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1660 1661 AE_INIT_RXDESC(sc, idx); 1662 1663 return (0); 1664 } 1665 1666 /* 1667 * ae_filter_setup: 1668 * 1669 * Set the chip's receive filter. 1670 */ 1671 static void 1672 ae_filter_setup(struct ae_softc *sc) 1673 { 1674 struct ethercom *ec = &sc->sc_ethercom; 1675 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1676 struct ether_multi *enm; 1677 struct ether_multistep step; 1678 uint32_t hash, mchash[2]; 1679 uint32_t macctl = 0; 1680 1681 /* 1682 * If the chip is running, we need to reset the interface, 1683 * and will revisit here (with IFF_RUNNING) clear. The 1684 * chip seems to really not like to have its multicast 1685 * filter programmed without a reset. 1686 */ 1687 if (ifp->if_flags & IFF_RUNNING) { 1688 (void) ae_init(ifp); 1689 return; 1690 } 1691 1692 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1693 device_xname(sc->sc_dev), sc->sc_flags)); 1694 1695 macctl = AE_READ(sc, CSR_MACCTL); 1696 macctl &= ~(MACCTL_PR | MACCTL_PM); 1697 macctl |= MACCTL_HASH; 1698 macctl |= MACCTL_HBD; 1699 macctl |= MACCTL_PR; 1700 1701 if (ifp->if_flags & IFF_PROMISC) { 1702 macctl |= MACCTL_PR; 1703 goto allmulti; 1704 } 1705 1706 mchash[0] = mchash[1] = 0; 1707 1708 ETHER_FIRST_MULTI(step, ec, enm); 1709 while (enm != NULL) { 1710 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1711 /* 1712 * We must listen to a range of multicast addresses. 1713 * For now, just accept all multicasts, rather than 1714 * trying to set only those filter bits needed to match 1715 * the range. (At this time, the only use of address 1716 * ranges is for IP multicast routing, for which the 1717 * range is big enough to require all bits set.) 1718 */ 1719 goto allmulti; 1720 } 1721 1722 /* Verify whether we use big or little endian hashes */ 1723 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1724 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1725 ETHER_NEXT_MULTI(step, enm); 1726 } 1727 ifp->if_flags &= ~IFF_ALLMULTI; 1728 goto setit; 1729 1730 allmulti: 1731 ifp->if_flags |= IFF_ALLMULTI; 1732 mchash[0] = mchash[1] = 0xffffffff; 1733 macctl |= MACCTL_PM; 1734 1735 setit: 1736 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1737 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1738 1739 AE_WRITE(sc, CSR_MACCTL, macctl); 1740 AE_BARRIER(sc); 1741 1742 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1743 device_xname(sc->sc_dev), macctl)); 1744 } 1745 1746 /* 1747 * ae_idle: 1748 * 1749 * Cause the transmit and/or receive processes to go idle. 1750 */ 1751 void 1752 ae_idle(struct ae_softc *sc, u_int32_t bits) 1753 { 1754 static const char * const txstate_names[] = { 1755 "STOPPED", 1756 "RUNNING - FETCH", 1757 "RUNNING - WAIT", 1758 "RUNNING - READING", 1759 "-- RESERVED --", 1760 "RUNNING - SETUP", 1761 "SUSPENDED", 1762 "RUNNING - CLOSE", 1763 }; 1764 static const char * const rxstate_names[] = { 1765 "STOPPED", 1766 "RUNNING - FETCH", 1767 "RUNNING - CHECK", 1768 "RUNNING - WAIT", 1769 "SUSPENDED", 1770 "RUNNING - CLOSE", 1771 "RUNNING - FLUSH", 1772 "RUNNING - QUEUE", 1773 }; 1774 1775 u_int32_t csr, ackmask = 0; 1776 int i; 1777 1778 if (bits & OPMODE_ST) 1779 ackmask |= STATUS_TPS; 1780 1781 if (bits & OPMODE_SR) 1782 ackmask |= STATUS_RPS; 1783 1784 AE_CLR(sc, CSR_OPMODE, bits); 1785 1786 for (i = 0; i < 1000; i++) { 1787 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1788 break; 1789 delay(10); 1790 } 1791 1792 csr = AE_READ(sc, CSR_STATUS); 1793 if ((csr & ackmask) != ackmask) { 1794 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1795 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1796 printf("%s: transmit process failed to idle: " 1797 "state %s\n", device_xname(sc->sc_dev), 1798 txstate_names[(csr & STATUS_TS) >> 20]); 1799 } 1800 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1801 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1802 printf("%s: receive process failed to idle: " 1803 "state %s\n", device_xname(sc->sc_dev), 1804 rxstate_names[(csr & STATUS_RS) >> 17]); 1805 } 1806 } 1807 } 1808 1809 /***************************************************************************** 1810 * Support functions for MII-attached media. 1811 *****************************************************************************/ 1812 1813 /* 1814 * ae_mii_tick: 1815 * 1816 * One second timer, used to tick the MII. 1817 */ 1818 static void 1819 ae_mii_tick(void *arg) 1820 { 1821 struct ae_softc *sc = arg; 1822 int s; 1823 1824 if (!device_is_active(sc->sc_dev)) 1825 return; 1826 1827 s = splnet(); 1828 mii_tick(&sc->sc_mii); 1829 splx(s); 1830 1831 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1832 } 1833 1834 /* 1835 * ae_mii_statchg: [mii interface function] 1836 * 1837 * Callback from PHY when media changes. 1838 */ 1839 static void 1840 ae_mii_statchg(struct ifnet *ifp) 1841 { 1842 struct ae_softc *sc = ifp->if_softc; 1843 uint32_t macctl, flowc; 1844 1845 //opmode = AE_READ(sc, CSR_OPMODE); 1846 macctl = AE_READ(sc, CSR_MACCTL); 1847 1848 /* XXX: do we need to do this? */ 1849 /* Idle the transmit and receive processes. */ 1850 //ae_idle(sc, OPMODE_ST|OPMODE_SR); 1851 1852 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1853 flowc = FLOWC_FCE; 1854 macctl &= ~MACCTL_DRO; 1855 macctl |= MACCTL_FDX; 1856 } else { 1857 flowc = 0; /* cannot do flow control in HDX */ 1858 macctl |= MACCTL_DRO; 1859 macctl &= ~MACCTL_FDX; 1860 } 1861 1862 AE_WRITE(sc, CSR_FLOWC, flowc); 1863 AE_WRITE(sc, CSR_MACCTL, macctl); 1864 1865 /* restore operational mode */ 1866 //AE_WRITE(sc, CSR_OPMODE, opmode); 1867 AE_BARRIER(sc); 1868 } 1869 1870 /* 1871 * ae_mii_readreg: 1872 * 1873 * Read a PHY register. 1874 */ 1875 static int 1876 ae_mii_readreg(device_t self, int phy, int reg) 1877 { 1878 struct ae_softc *sc = device_private(self); 1879 uint32_t addr; 1880 int i; 1881 1882 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1883 AE_WRITE(sc, CSR_MIIADDR, addr); 1884 AE_BARRIER(sc); 1885 for (i = 0; i < 100000000; i++) { 1886 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1887 break; 1888 } 1889 1890 return (AE_READ(sc, CSR_MIIDATA) & 0xffff); 1891 } 1892 1893 /* 1894 * ae_mii_writereg: 1895 * 1896 * Write a PHY register. 1897 */ 1898 static void 1899 ae_mii_writereg(device_t self, int phy, int reg, int val) 1900 { 1901 struct ae_softc *sc = device_private(self); 1902 uint32_t addr; 1903 int i; 1904 1905 /* write the data register */ 1906 AE_WRITE(sc, CSR_MIIDATA, val); 1907 1908 /* write the address to latch it in */ 1909 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1910 MIIADDR_WRITE; 1911 AE_WRITE(sc, CSR_MIIADDR, addr); 1912 AE_BARRIER(sc); 1913 1914 for (i = 0; i < 100000000; i++) { 1915 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1916 break; 1917 } 1918 } 1919
Indexes created Wed Sep 24 05:09:52 GMT 2025