if_ae.c revision 1.3
1 /* $Id: if_ae.c,v 1.3 2006/09/04 05:17:26 gdamore Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 3. All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the NetBSD 61 * Foundation, Inc. and its contributors. 62 * 4. Neither the name of The NetBSD Foundation nor the names of its 63 * contributors may be used to endorse or promote products derived 64 * from this software without specific prior written permission. 65 * 66 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 67 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 68 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 69 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 70 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 71 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 72 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 73 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 74 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 75 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 76 * POSSIBILITY OF SUCH DAMAGE. 77 */ 78 79 /* 80 * Device driver for the onboard ethernet MAC found on the AR5312 81 * chip's AHB bus. 82 * 83 * This device is very simliar to the tulip in most regards, and 84 * the code is directly derived from NetBSD's tulip.c. However, it 85 * is different enough that it did not seem to be a good idea to 86 * add further complexity to the tulip driver, so we have our own. 87 * 88 * Also tulip has a lot of complexity in it for various parts/options 89 * that we don't need, and on these little boxes with only ~8MB RAM, we 90 * don't want any extra bloat. 91 */ 92 93 /* 94 * TODO: 95 * 96 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 97 * inbound packets on a half-word boundary, which would make life easier 98 * for TCP/IP. (Aligning IP headers on a word.) 99 * 100 * 2) There is stuff in original tulip to shut down the device when reacting 101 * to a a change in link status. Is that needed. 102 * 103 * 3) Test with variety of 10/100 HDX/FDX scenarios. 104 * 105 */ 106 107 #include <sys/cdefs.h> 108 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.3 2006/09/04 05:17:26 gdamore Exp $"); 109 110 #include "bpfilter.h" 111 112 #include <sys/param.h> 113 #include <sys/systm.h> 114 #include <sys/callout.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/kernel.h> 118 #include <sys/socket.h> 119 #include <sys/ioctl.h> 120 #include <sys/errno.h> 121 #include <sys/device.h> 122 123 #include <machine/endian.h> 124 125 #include <uvm/uvm_extern.h> 126 127 #include <net/if.h> 128 #include <net/if_dl.h> 129 #include <net/if_media.h> 130 #include <net/if_ether.h> 131 132 #if NBPFILTER > 0 133 #include <net/bpf.h> 134 #endif 135 136 #include <machine/bus.h> 137 #include <machine/intr.h> 138 139 #include <dev/mii/mii.h> 140 #include <dev/mii/miivar.h> 141 #include <dev/mii/mii_bitbang.h> 142 143 #include <mips/atheros/include/arbusvar.h> 144 #include <mips/atheros/dev/aereg.h> 145 #include <mips/atheros/dev/aevar.h> 146 147 static const struct { 148 u_int32_t txth_opmode; /* OPMODE bits */ 149 const char *txth_name; /* name of mode */ 150 } ae_txthresh[] = { 151 { OPMODE_TR_32, "32 words" }, 152 { OPMODE_TR_64, "64 words" }, 153 { OPMODE_TR_128, "128 words" }, 154 { OPMODE_TR_256, "256 words" }, 155 { OPMODE_SF, "store and forward mode" }, 156 { 0, NULL }, 157 }; 158 159 static int ae_match(struct device *, struct cfdata *, void *); 160 static void ae_attach(struct device *, struct device *, void *); 161 static int ae_detach(struct device *, int); 162 static int ae_activate(struct device *, enum devact); 163 164 static void ae_reset(struct ae_softc *); 165 static void ae_idle(struct ae_softc *, u_int32_t); 166 167 static int ae_mediachange(struct ifnet *); 168 static void ae_mediastatus(struct ifnet *, struct ifmediareq *); 169 170 static void ae_start(struct ifnet *); 171 static void ae_watchdog(struct ifnet *); 172 static int ae_ioctl(struct ifnet *, u_long, caddr_t); 173 static int ae_init(struct ifnet *); 174 static void ae_stop(struct ifnet *, int); 175 176 static void ae_shutdown(void *); 177 178 static void ae_rxdrain(struct ae_softc *); 179 static int ae_add_rxbuf(struct ae_softc *, int); 180 181 static int ae_enable(struct ae_softc *); 182 static void ae_disable(struct ae_softc *); 183 static void ae_power(int, void *); 184 185 static void ae_filter_setup(struct ae_softc *); 186 187 static int ae_intr(void *); 188 static void ae_rxintr(struct ae_softc *); 189 static void ae_txintr(struct ae_softc *); 190 191 static void ae_mii_tick(void *); 192 static void ae_mii_statchg(struct device *); 193 194 static int ae_mii_readreg(struct device *, int, int); 195 static void ae_mii_writereg(struct device *, int, int, int); 196 197 #ifdef AE_DEBUG 198 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 199 printf x 200 #else 201 #define DPRINTF(sc, x) /* nothing */ 202 #endif 203 204 #ifdef AE_STATS 205 static void ae_print_stats(struct ae_softc *); 206 #endif 207 208 CFATTACH_DECL(ae, sizeof(struct ae_softc), 209 ae_match, ae_attach, ae_detach, ae_activate); 210 211 /* 212 * ae_match: 213 * 214 * Check for a device match. 215 */ 216 int 217 ae_match(struct device *parent, struct cfdata *cf, void *aux) 218 { 219 struct arbus_attach_args *aa = aux; 220 221 if (strcmp(aa->aa_name, cf->cf_name) == 0) 222 return 1; 223 224 return 0; 225 226 } 227 228 /* 229 * ae_attach: 230 * 231 * Attach an ae interface to the system. 232 */ 233 void 234 ae_attach(struct device *parent, struct device *self, void *aux) 235 { 236 const uint8_t *enaddr; 237 prop_data_t ea; 238 struct ae_softc *sc = (void *)self; 239 struct arbus_attach_args *aa = aux; 240 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 241 int i, error; 242 243 callout_init(&sc->sc_tick_callout); 244 245 printf(": Atheros AR531X 10/100 Ethernet\n"); 246 247 /* 248 * Try to get MAC address. 249 */ 250 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 251 if (ea == NULL) { 252 printf("%s: unable to get mac-addr property\n", 253 sc->sc_dev.dv_xname); 254 return; 255 } 256 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 257 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 258 enaddr = prop_data_data_nocopy(ea); 259 260 /* Announce ourselves. */ 261 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 262 ether_sprintf(enaddr)); 263 264 sc->sc_cirq = aa->aa_cirq; 265 sc->sc_mirq = aa->aa_mirq; 266 sc->sc_st = aa->aa_bst; 267 sc->sc_dmat = aa->aa_dmat; 268 269 SIMPLEQ_INIT(&sc->sc_txfreeq); 270 SIMPLEQ_INIT(&sc->sc_txdirtyq); 271 272 /* 273 * Map registers. 274 */ 275 sc->sc_size = aa->aa_size; 276 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 277 &sc->sc_sh)) != 0) { 278 printf("%s: unable to map registers, error = %d\n", 279 sc->sc_dev.dv_xname, error); 280 goto fail_0; 281 } 282 283 /* 284 * Allocate the control data structures, and create and load the 285 * DMA map for it. 286 */ 287 if ((error = bus_dmamem_alloc(sc->sc_dmat, 288 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 289 1, &sc->sc_cdnseg, 0)) != 0) { 290 printf("%s: unable to allocate control data, error = %d\n", 291 sc->sc_dev.dv_xname, error); 292 goto fail_1; 293 } 294 295 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 296 sizeof(struct ae_control_data), (caddr_t *)&sc->sc_control_data, 297 BUS_DMA_COHERENT)) != 0) { 298 printf("%s: unable to map control data, error = %d\n", 299 sc->sc_dev.dv_xname, error); 300 goto fail_2; 301 } 302 303 if ((error = bus_dmamap_create(sc->sc_dmat, 304 sizeof(struct ae_control_data), 1, 305 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 306 printf("%s: unable to create control data DMA map, " 307 "error = %d\n", sc->sc_dev.dv_xname, error); 308 goto fail_3; 309 } 310 311 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 312 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 313 0)) != 0) { 314 printf("%s: unable to load control data DMA map, error = %d\n", 315 sc->sc_dev.dv_xname, error); 316 goto fail_4; 317 } 318 319 /* 320 * Create the transmit buffer DMA maps. 321 */ 322 for (i = 0; i < AE_TXQUEUELEN; i++) { 323 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 324 AE_NTXSEGS, MCLBYTES, 0, 0, 325 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 326 printf("%s: unable to create tx DMA map %d, " 327 "error = %d\n", sc->sc_dev.dv_xname, i, error); 328 goto fail_5; 329 } 330 } 331 332 /* 333 * Create the receive buffer DMA maps. 334 */ 335 for (i = 0; i < AE_NRXDESC; i++) { 336 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 337 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 338 printf("%s: unable to create rx DMA map %d, " 339 "error = %d\n", sc->sc_dev.dv_xname, i, error); 340 goto fail_6; 341 } 342 sc->sc_rxsoft[i].rxs_mbuf = NULL; 343 } 344 345 /* 346 * Reset the chip to a known state. 347 */ 348 ae_reset(sc); 349 350 /* 351 * From this point forward, the attachment cannot fail. A failure 352 * before this point releases all resources that may have been 353 * allocated. 354 */ 355 sc->sc_flags |= AE_ATTACHED; 356 357 /* 358 * Initialize our media structures. This may probe the MII, if 359 * present. 360 */ 361 sc->sc_mii.mii_ifp = ifp; 362 sc->sc_mii.mii_readreg = ae_mii_readreg; 363 sc->sc_mii.mii_writereg = ae_mii_writereg; 364 sc->sc_mii.mii_statchg = ae_mii_statchg; 365 ifmedia_init(&sc->sc_mii.mii_media, 0, ae_mediachange, 366 ae_mediastatus); 367 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 368 MII_OFFSET_ANY, 0); 369 370 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 371 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 372 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 373 } else 374 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 375 376 sc->sc_tick = ae_mii_tick; 377 378 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 379 ifp->if_softc = sc; 380 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 381 sc->sc_if_flags = ifp->if_flags; 382 ifp->if_ioctl = ae_ioctl; 383 ifp->if_start = ae_start; 384 ifp->if_watchdog = ae_watchdog; 385 ifp->if_init = ae_init; 386 ifp->if_stop = ae_stop; 387 IFQ_SET_READY(&ifp->if_snd); 388 389 /* 390 * We can support 802.1Q VLAN-sized frames. 391 */ 392 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 393 394 /* 395 * Attach the interface. 396 */ 397 if_attach(ifp); 398 ether_ifattach(ifp, enaddr); 399 400 #if NRND > 0 401 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 402 RND_TYPE_NET, 0); 403 #endif 404 405 /* 406 * Make sure the interface is shutdown during reboot. 407 */ 408 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 409 if (sc->sc_sdhook == NULL) 410 printf("%s: WARNING: unable to establish shutdown hook\n", 411 sc->sc_dev.dv_xname); 412 413 /* 414 * Add a suspend hook to make sure we come back up after a 415 * resume. 416 */ 417 sc->sc_powerhook = powerhook_establish(ae_power, sc); 418 if (sc->sc_powerhook == NULL) 419 printf("%s: WARNING: unable to establish power hook\n", 420 sc->sc_dev.dv_xname); 421 return; 422 423 /* 424 * Free any resources we've allocated during the failed attach 425 * attempt. Do this in reverse order and fall through. 426 */ 427 fail_6: 428 for (i = 0; i < AE_NRXDESC; i++) { 429 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 430 bus_dmamap_destroy(sc->sc_dmat, 431 sc->sc_rxsoft[i].rxs_dmamap); 432 } 433 fail_5: 434 for (i = 0; i < AE_TXQUEUELEN; i++) { 435 if (sc->sc_txsoft[i].txs_dmamap != NULL) 436 bus_dmamap_destroy(sc->sc_dmat, 437 sc->sc_txsoft[i].txs_dmamap); 438 } 439 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 440 fail_4: 441 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 442 fail_3: 443 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 444 sizeof(struct ae_control_data)); 445 fail_2: 446 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 447 fail_1: 448 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 449 fail_0: 450 return; 451 } 452 453 /* 454 * ae_activate: 455 * 456 * Handle device activation/deactivation requests. 457 */ 458 int 459 ae_activate(struct device *self, enum devact act) 460 { 461 struct ae_softc *sc = (void *) self; 462 int s, error = 0; 463 464 s = splnet(); 465 switch (act) { 466 case DVACT_ACTIVATE: 467 error = EOPNOTSUPP; 468 break; 469 470 case DVACT_DEACTIVATE: 471 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 472 if_deactivate(&sc->sc_ethercom.ec_if); 473 break; 474 } 475 splx(s); 476 477 return (error); 478 } 479 480 /* 481 * ae_detach: 482 * 483 * Detach a device interface. 484 */ 485 int 486 ae_detach(struct device *self, int flags) 487 { 488 struct ae_softc *sc = (void *)self; 489 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 490 struct ae_rxsoft *rxs; 491 struct ae_txsoft *txs; 492 int i; 493 494 /* 495 * Succeed now if there isn't any work to do. 496 */ 497 if ((sc->sc_flags & AE_ATTACHED) == 0) 498 return (0); 499 500 /* Unhook our tick handler. */ 501 if (sc->sc_tick) 502 callout_stop(&sc->sc_tick_callout); 503 504 /* Detach all PHYs */ 505 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 506 507 /* Delete all remaining media. */ 508 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 509 510 #if NRND > 0 511 rnd_detach_source(&sc->sc_rnd_source); 512 #endif 513 ether_ifdetach(ifp); 514 if_detach(ifp); 515 516 for (i = 0; i < AE_NRXDESC; i++) { 517 rxs = &sc->sc_rxsoft[i]; 518 if (rxs->rxs_mbuf != NULL) { 519 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 520 m_freem(rxs->rxs_mbuf); 521 rxs->rxs_mbuf = NULL; 522 } 523 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 524 } 525 for (i = 0; i < AE_TXQUEUELEN; i++) { 526 txs = &sc->sc_txsoft[i]; 527 if (txs->txs_mbuf != NULL) { 528 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 529 m_freem(txs->txs_mbuf); 530 txs->txs_mbuf = NULL; 531 } 532 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 533 } 534 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 535 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 536 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 537 sizeof(struct ae_control_data)); 538 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 539 540 shutdownhook_disestablish(sc->sc_sdhook); 541 powerhook_disestablish(sc->sc_powerhook); 542 543 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 544 545 546 return (0); 547 } 548 549 /* 550 * ae_shutdown: 551 * 552 * Make sure the interface is stopped at reboot time. 553 */ 554 static void 555 ae_shutdown(void *arg) 556 { 557 struct ae_softc *sc = arg; 558 559 ae_stop(&sc->sc_ethercom.ec_if, 1); 560 } 561 562 /* 563 * ae_start: [ifnet interface function] 564 * 565 * Start packet transmission on the interface. 566 */ 567 static void 568 ae_start(struct ifnet *ifp) 569 { 570 struct ae_softc *sc = ifp->if_softc; 571 struct mbuf *m0, *m; 572 struct ae_txsoft *txs, *last_txs = NULL; 573 bus_dmamap_t dmamap; 574 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 575 576 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 577 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 578 579 580 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 581 return; 582 583 /* 584 * Remember the previous number of free descriptors and 585 * the first descriptor we'll use. 586 */ 587 ofree = sc->sc_txfree; 588 firsttx = sc->sc_txnext; 589 590 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 591 sc->sc_dev.dv_xname, ofree, firsttx)); 592 593 /* 594 * Loop through the send queue, setting up transmit descriptors 595 * until we drain the queue, or use up all available transmit 596 * descriptors. 597 */ 598 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 599 sc->sc_txfree != 0) { 600 /* 601 * Grab a packet off the queue. 602 */ 603 IFQ_POLL(&ifp->if_snd, m0); 604 if (m0 == NULL) 605 break; 606 m = NULL; 607 608 dmamap = txs->txs_dmamap; 609 610 /* 611 * Load the DMA map. If this fails, the packet either 612 * didn't fit in the alloted number of segments, or we were 613 * short on resources. In this case, we'll copy and try 614 * again. 615 */ 616 if (((mtod(m0, uintptr_t) & 3) != 0) || 617 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 618 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 619 MGETHDR(m, M_DONTWAIT, MT_DATA); 620 if (m == NULL) { 621 printf("%s: unable to allocate Tx mbuf\n", 622 sc->sc_dev.dv_xname); 623 break; 624 } 625 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 626 if (m0->m_pkthdr.len > MHLEN) { 627 MCLGET(m, M_DONTWAIT); 628 if ((m->m_flags & M_EXT) == 0) { 629 printf("%s: unable to allocate Tx " 630 "cluster\n", sc->sc_dev.dv_xname); 631 m_freem(m); 632 break; 633 } 634 } 635 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 636 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 637 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 638 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 639 if (error) { 640 printf("%s: unable to load Tx buffer, " 641 "error = %d\n", sc->sc_dev.dv_xname, 642 error); 643 break; 644 } 645 } 646 647 /* 648 * Ensure we have enough descriptors free to describe 649 * the packet. 650 */ 651 if (dmamap->dm_nsegs > sc->sc_txfree) { 652 /* 653 * Not enough free descriptors to transmit this 654 * packet. We haven't committed to anything yet, 655 * so just unload the DMA map, put the packet 656 * back on the queue, and punt. Notify the upper 657 * layer that there are no more slots left. 658 * 659 * XXX We could allocate an mbuf and copy, but 660 * XXX it is worth it? 661 */ 662 ifp->if_flags |= IFF_OACTIVE; 663 bus_dmamap_unload(sc->sc_dmat, dmamap); 664 if (m != NULL) 665 m_freem(m); 666 break; 667 } 668 669 IFQ_DEQUEUE(&ifp->if_snd, m0); 670 if (m != NULL) { 671 m_freem(m0); 672 m0 = m; 673 } 674 675 /* 676 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 677 */ 678 679 /* Sync the DMA map. */ 680 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 681 BUS_DMASYNC_PREWRITE); 682 683 /* 684 * Initialize the transmit descriptors. 685 */ 686 for (nexttx = sc->sc_txnext, seg = 0; 687 seg < dmamap->dm_nsegs; 688 seg++, nexttx = AE_NEXTTX(nexttx)) { 689 /* 690 * If this is the first descriptor we're 691 * enqueueing, don't set the OWN bit just 692 * yet. That could cause a race condition. 693 * We'll do it below. 694 */ 695 sc->sc_txdescs[nexttx].ad_status = 696 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 697 sc->sc_txdescs[nexttx].ad_bufaddr1 = 698 dmamap->dm_segs[seg].ds_addr; 699 sc->sc_txdescs[nexttx].ad_ctl = 700 (dmamap->dm_segs[seg].ds_len << 701 ADCTL_SIZE1_SHIFT) | 702 (nexttx == (AE_NTXDESC - 1) ? 703 ADCTL_ER : 0); 704 lasttx = nexttx; 705 } 706 707 KASSERT(lasttx != -1); 708 709 /* Set `first segment' and `last segment' appropriately. */ 710 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 711 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 712 713 #ifdef AE_DEBUG 714 if (ifp->if_flags & IFF_DEBUG) { 715 printf(" txsoft %p transmit chain:\n", txs); 716 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 717 printf(" descriptor %d:\n", seg); 718 printf(" ad_status: 0x%08x\n", 719 sc->sc_txdescs[seg].ad_status); 720 printf(" ad_ctl: 0x%08x\n", 721 sc->sc_txdescs[seg].ad_ctl); 722 printf(" ad_bufaddr1: 0x%08x\n", 723 sc->sc_txdescs[seg].ad_bufaddr1); 724 printf(" ad_bufaddr2: 0x%08x\n", 725 sc->sc_txdescs[seg].ad_bufaddr2); 726 if (seg == lasttx) 727 break; 728 } 729 } 730 #endif 731 732 /* Sync the descriptors we're using. */ 733 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 734 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 735 736 /* 737 * Store a pointer to the packet so we can free it later, 738 * and remember what txdirty will be once the packet is 739 * done. 740 */ 741 txs->txs_mbuf = m0; 742 txs->txs_firstdesc = sc->sc_txnext; 743 txs->txs_lastdesc = lasttx; 744 txs->txs_ndescs = dmamap->dm_nsegs; 745 746 /* Advance the tx pointer. */ 747 sc->sc_txfree -= dmamap->dm_nsegs; 748 sc->sc_txnext = nexttx; 749 750 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 751 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 752 753 last_txs = txs; 754 755 #if NBPFILTER > 0 756 /* 757 * Pass the packet to any BPF listeners. 758 */ 759 if (ifp->if_bpf) 760 bpf_mtap(ifp->if_bpf, m0); 761 #endif /* NBPFILTER > 0 */ 762 } 763 764 if (txs == NULL || sc->sc_txfree == 0) { 765 /* No more slots left; notify upper layer. */ 766 ifp->if_flags |= IFF_OACTIVE; 767 } 768 769 if (sc->sc_txfree != ofree) { 770 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 771 sc->sc_dev.dv_xname, lasttx, firsttx)); 772 /* 773 * Cause a transmit interrupt to happen on the 774 * last packet we enqueued. 775 */ 776 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 777 AE_CDTXSYNC(sc, lasttx, 1, 778 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 779 780 /* 781 * The entire packet chain is set up. Give the 782 * first descriptor to the chip now. 783 */ 784 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 785 AE_CDTXSYNC(sc, firsttx, 1, 786 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 787 788 /* Wake up the transmitter. */ 789 /* XXX USE AUTOPOLLING? */ 790 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 791 AE_BARRIER(sc); 792 793 /* Set a watchdog timer in case the chip flakes out. */ 794 ifp->if_timer = 5; 795 } 796 } 797 798 /* 799 * ae_watchdog: [ifnet interface function] 800 * 801 * Watchdog timer handler. 802 */ 803 static void 804 ae_watchdog(struct ifnet *ifp) 805 { 806 struct ae_softc *sc = ifp->if_softc; 807 int doing_transmit; 808 809 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 810 811 if (doing_transmit) { 812 printf("%s: transmit timeout\n", sc->sc_dev.dv_xname); 813 ifp->if_oerrors++; 814 } 815 else 816 printf("%s: spurious watchdog timeout\n", sc->sc_dev.dv_xname); 817 818 (void) ae_init(ifp); 819 820 /* Try to get more packets going. */ 821 ae_start(ifp); 822 } 823 824 /* 825 * ae_ioctl: [ifnet interface function] 826 * 827 * Handle control requests from the operator. 828 */ 829 static int 830 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 831 { 832 struct ae_softc *sc = ifp->if_softc; 833 struct ifreq *ifr = (struct ifreq *)data; 834 int s, error; 835 836 s = splnet(); 837 838 switch (cmd) { 839 case SIOCSIFMEDIA: 840 case SIOCGIFMEDIA: 841 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 842 break; 843 case SIOCSIFFLAGS: 844 /* If the interface is up and running, only modify the receive 845 * filter when setting promiscuous or debug mode. Otherwise 846 * fall through to ether_ioctl, which will reset the chip. 847 */ 848 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 849 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 850 == (IFF_UP|IFF_RUNNING)) 851 && ((ifp->if_flags & (~RESETIGN)) 852 == (sc->sc_if_flags & (~RESETIGN)))) { 853 /* Set up the receive filter. */ 854 ae_filter_setup(sc); 855 error = 0; 856 break; 857 #undef RESETIGN 858 } 859 /* FALLTHROUGH */ 860 default: 861 error = ether_ioctl(ifp, cmd, data); 862 if (error == ENETRESET) { 863 if (ifp->if_flags & IFF_RUNNING) { 864 /* 865 * Multicast list has changed. Set the 866 * hardware filter accordingly. 867 */ 868 ae_filter_setup(sc); 869 } 870 error = 0; 871 } 872 break; 873 } 874 875 /* Try to get more packets going. */ 876 if (AE_IS_ENABLED(sc)) 877 ae_start(ifp); 878 879 sc->sc_if_flags = ifp->if_flags; 880 splx(s); 881 return (error); 882 } 883 884 /* 885 * ae_intr: 886 * 887 * Interrupt service routine. 888 */ 889 int 890 ae_intr(void *arg) 891 { 892 struct ae_softc *sc = arg; 893 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 894 u_int32_t status, rxstatus, txstatus; 895 int handled = 0, txthresh; 896 897 DPRINTF(sc, ("%s: ae_intr\n", sc->sc_dev.dv_xname)); 898 899 #ifdef DEBUG 900 if (AE_IS_ENABLED(sc) == 0) 901 panic("%s: ae_intr: not enabled", sc->sc_dev.dv_xname); 902 #endif 903 904 /* 905 * If the interface isn't running, the interrupt couldn't 906 * possibly have come from us. 907 */ 908 if ((ifp->if_flags & IFF_RUNNING) == 0 || 909 !device_is_active(&sc->sc_dev)) { 910 printf("spurious?!?\n"); 911 return (0); 912 } 913 914 for (;;) { 915 status = AE_READ(sc, CSR_STATUS); 916 if (status) { 917 AE_WRITE(sc, CSR_STATUS, status); 918 AE_BARRIER(sc); 919 } 920 921 if ((status & sc->sc_inten) == 0) 922 break; 923 924 handled = 1; 925 926 rxstatus = status & sc->sc_rxint_mask; 927 txstatus = status & sc->sc_txint_mask; 928 929 if (rxstatus) { 930 /* Grab new any new packets. */ 931 ae_rxintr(sc); 932 933 if (rxstatus & STATUS_RU) { 934 printf("%s: receive ring overrun\n", 935 sc->sc_dev.dv_xname); 936 /* Get the receive process going again. */ 937 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 938 AE_BARRIER(sc); 939 break; 940 } 941 } 942 943 if (txstatus) { 944 /* Sweep up transmit descriptors. */ 945 ae_txintr(sc); 946 947 if (txstatus & STATUS_TJT) 948 printf("%s: transmit jabber timeout\n", 949 sc->sc_dev.dv_xname); 950 951 if (txstatus & STATUS_UNF) { 952 /* 953 * Increase our transmit threshold if 954 * another is available. 955 */ 956 txthresh = sc->sc_txthresh + 1; 957 if (ae_txthresh[txthresh].txth_name != NULL) { 958 uint32_t opmode; 959 /* Idle the transmit process. */ 960 opmode = AE_READ(sc, CSR_OPMODE); 961 ae_idle(sc, OPMODE_ST); 962 963 sc->sc_txthresh = txthresh; 964 opmode &= 965 ~(OPMODE_TR|OPMODE_SF); 966 opmode |= 967 ae_txthresh[txthresh].txth_opmode; 968 printf("%s: transmit underrun; new " 969 "threshold: %s\n", 970 sc->sc_dev.dv_xname, 971 ae_txthresh[txthresh].txth_name); 972 973 /* 974 * Set the new threshold and restart 975 * the transmit process. 976 */ 977 AE_WRITE(sc, CSR_OPMODE, opmode); 978 AE_BARRIER(sc); 979 } 980 /* 981 * XXX Log every Nth underrun from 982 * XXX now on? 983 */ 984 } 985 } 986 987 if (status & (STATUS_TPS|STATUS_RPS)) { 988 if (status & STATUS_TPS) 989 printf("%s: transmit process stopped\n", 990 sc->sc_dev.dv_xname); 991 if (status & STATUS_RPS) 992 printf("%s: receive process stopped\n", 993 sc->sc_dev.dv_xname); 994 (void) ae_init(ifp); 995 break; 996 } 997 998 if (status & STATUS_SE) { 999 const char *str; 1000 1001 if (status & STATUS_TX_ABORT) 1002 str = "tx abort"; 1003 else if (status & STATUS_RX_ABORT) 1004 str = "rx abort"; 1005 else 1006 str = "unknown error"; 1007 1008 printf("%s: fatal system error: %s\n", 1009 sc->sc_dev.dv_xname, str); 1010 (void) ae_init(ifp); 1011 break; 1012 } 1013 1014 /* 1015 * Not handled: 1016 * 1017 * Transmit buffer unavailable -- normal 1018 * condition, nothing to do, really. 1019 * 1020 * General purpose timer experied -- we don't 1021 * use the general purpose timer. 1022 * 1023 * Early receive interrupt -- not available on 1024 * all chips, we just use RI. We also only 1025 * use single-segment receive DMA, so this 1026 * is mostly useless. 1027 */ 1028 } 1029 1030 /* Try to get more packets going. */ 1031 ae_start(ifp); 1032 1033 #if NRND > 0 1034 if (handled) 1035 rnd_add_uint32(&sc->sc_rnd_source, status); 1036 #endif 1037 return (handled); 1038 } 1039 1040 /* 1041 * ae_rxintr: 1042 * 1043 * Helper; handle receive interrupts. 1044 */ 1045 static void 1046 ae_rxintr(struct ae_softc *sc) 1047 { 1048 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1049 struct ether_header *eh; 1050 struct ae_rxsoft *rxs; 1051 struct mbuf *m; 1052 u_int32_t rxstat; 1053 int i, len; 1054 1055 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1056 rxs = &sc->sc_rxsoft[i]; 1057 1058 AE_CDRXSYNC(sc, i, 1059 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1060 1061 rxstat = sc->sc_rxdescs[i].ad_status; 1062 1063 if (rxstat & ADSTAT_OWN) { 1064 /* 1065 * We have processed all of the receive buffers. 1066 */ 1067 break; 1068 } 1069 1070 /* 1071 * If any collisions were seen on the wire, count one. 1072 */ 1073 if (rxstat & ADSTAT_Rx_CS) 1074 ifp->if_collisions++; 1075 1076 /* 1077 * If an error occurred, update stats, clear the status 1078 * word, and leave the packet buffer in place. It will 1079 * simply be reused the next time the ring comes around. 1080 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1081 * error. 1082 */ 1083 if (rxstat & ADSTAT_ES && 1084 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1085 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1086 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1087 #define PRINTERR(bit, str) \ 1088 if (rxstat & (bit)) \ 1089 printf("%s: receive error: %s\n", \ 1090 sc->sc_dev.dv_xname, str) 1091 ifp->if_ierrors++; 1092 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1093 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1094 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1095 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1096 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1097 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1098 #undef PRINTERR 1099 AE_INIT_RXDESC(sc, i); 1100 continue; 1101 } 1102 1103 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1104 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1105 1106 /* 1107 * No errors; receive the packet. Note the chip 1108 * includes the CRC with every packet. 1109 */ 1110 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1111 1112 /* 1113 * XXX: the Atheros part can align on half words. what 1114 * is the performance implication of this? Probably 1115 * minimal, and we should use it... 1116 */ 1117 #ifdef __NO_STRICT_ALIGNMENT 1118 /* 1119 * Allocate a new mbuf cluster. If that fails, we are 1120 * out of memory, and must drop the packet and recycle 1121 * the buffer that's already attached to this descriptor. 1122 */ 1123 m = rxs->rxs_mbuf; 1124 if (ae_add_rxbuf(sc, i) != 0) { 1125 ifp->if_ierrors++; 1126 AE_INIT_RXDESC(sc, i); 1127 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1128 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1129 continue; 1130 } 1131 #else 1132 /* 1133 * The chip's receive buffers must be 4-byte aligned. 1134 * But this means that the data after the Ethernet header 1135 * is misaligned. We must allocate a new buffer and 1136 * copy the data, shifted forward 2 bytes. 1137 */ 1138 MGETHDR(m, M_DONTWAIT, MT_DATA); 1139 if (m == NULL) { 1140 dropit: 1141 ifp->if_ierrors++; 1142 AE_INIT_RXDESC(sc, i); 1143 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1144 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1145 continue; 1146 } 1147 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1148 if (len > (MHLEN - 2)) { 1149 MCLGET(m, M_DONTWAIT); 1150 if ((m->m_flags & M_EXT) == 0) { 1151 m_freem(m); 1152 goto dropit; 1153 } 1154 } 1155 m->m_data += 2; 1156 1157 /* 1158 * Note that we use clusters for incoming frames, so the 1159 * buffer is virtually contiguous. 1160 */ 1161 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1162 1163 /* Allow the receive descriptor to continue using its mbuf. */ 1164 AE_INIT_RXDESC(sc, i); 1165 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1166 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1167 #endif /* __NO_STRICT_ALIGNMENT */ 1168 1169 ifp->if_ipackets++; 1170 eh = mtod(m, struct ether_header *); 1171 m->m_pkthdr.rcvif = ifp; 1172 m->m_pkthdr.len = m->m_len = len; 1173 1174 #if NBPFILTER > 0 1175 /* 1176 * Pass this up to any BPF listeners, but only 1177 * pass it up the stack if its for us. 1178 */ 1179 if (ifp->if_bpf) 1180 bpf_mtap(ifp->if_bpf, m); 1181 #endif /* NPBFILTER > 0 */ 1182 1183 /* Pass it on. */ 1184 (*ifp->if_input)(ifp, m); 1185 } 1186 1187 /* Update the receive pointer. */ 1188 sc->sc_rxptr = i; 1189 } 1190 1191 /* 1192 * ae_txintr: 1193 * 1194 * Helper; handle transmit interrupts. 1195 */ 1196 static void 1197 ae_txintr(struct ae_softc *sc) 1198 { 1199 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1200 struct ae_txsoft *txs; 1201 u_int32_t txstat; 1202 1203 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1204 sc->sc_dev.dv_xname, sc->sc_flags)); 1205 1206 ifp->if_flags &= ~IFF_OACTIVE; 1207 1208 /* 1209 * Go through our Tx list and free mbufs for those 1210 * frames that have been transmitted. 1211 */ 1212 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1213 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1214 txs->txs_ndescs, 1215 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1216 1217 #ifdef AE_DEBUG 1218 if (ifp->if_flags & IFF_DEBUG) { 1219 int i; 1220 printf(" txsoft %p transmit chain:\n", txs); 1221 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1222 printf(" descriptor %d:\n", i); 1223 printf(" ad_status: 0x%08x\n", 1224 sc->sc_txdescs[i].ad_status); 1225 printf(" ad_ctl: 0x%08x\n", 1226 sc->sc_txdescs[i].ad_ctl); 1227 printf(" ad_bufaddr1: 0x%08x\n", 1228 sc->sc_txdescs[i].ad_bufaddr1); 1229 printf(" ad_bufaddr2: 0x%08x\n", 1230 sc->sc_txdescs[i].ad_bufaddr2); 1231 if (i == txs->txs_lastdesc) 1232 break; 1233 } 1234 } 1235 #endif 1236 1237 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1238 if (txstat & ADSTAT_OWN) 1239 break; 1240 1241 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1242 1243 sc->sc_txfree += txs->txs_ndescs; 1244 1245 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1246 0, txs->txs_dmamap->dm_mapsize, 1247 BUS_DMASYNC_POSTWRITE); 1248 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1249 m_freem(txs->txs_mbuf); 1250 txs->txs_mbuf = NULL; 1251 1252 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1253 1254 /* 1255 * Check for errors and collisions. 1256 */ 1257 #ifdef AE_STATS 1258 if (txstat & ADSTAT_Tx_UF) 1259 sc->sc_stats.ts_tx_uf++; 1260 if (txstat & ADSTAT_Tx_TO) 1261 sc->sc_stats.ts_tx_to++; 1262 if (txstat & ADSTAT_Tx_EC) 1263 sc->sc_stats.ts_tx_ec++; 1264 if (txstat & ADSTAT_Tx_LC) 1265 sc->sc_stats.ts_tx_lc++; 1266 #endif 1267 1268 if (txstat & (ADSTAT_Tx_UF|ADSTAT_Tx_TO)) 1269 ifp->if_oerrors++; 1270 1271 if (txstat & ADSTAT_Tx_EC) 1272 ifp->if_collisions += 16; 1273 else 1274 ifp->if_collisions += ADSTAT_Tx_COLLISIONS(txstat); 1275 if (txstat & ADSTAT_Tx_LC) 1276 ifp->if_collisions++; 1277 1278 ifp->if_opackets++; 1279 } 1280 1281 /* 1282 * If there are no more pending transmissions, cancel the watchdog 1283 * timer. 1284 */ 1285 if (txs == NULL) 1286 ifp->if_timer = 0; 1287 } 1288 1289 #ifdef AE_STATS 1290 void 1291 ae_print_stats(struct ae_softc *sc) 1292 { 1293 1294 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1295 sc->sc_dev.dv_xname, 1296 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1297 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1298 } 1299 #endif 1300 1301 /* 1302 * ae_reset: 1303 * 1304 * Perform a soft reset on the chip. 1305 */ 1306 void 1307 ae_reset(struct ae_softc *sc) 1308 { 1309 int i; 1310 1311 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1312 AE_BARRIER(sc); 1313 1314 /* 1315 * The chip doesn't take itself out of reset automatically. 1316 * We need to do so after 2us. 1317 */ 1318 delay(10); 1319 AE_WRITE(sc, CSR_BUSMODE, 0); 1320 AE_BARRIER(sc); 1321 1322 for (i = 0; i < 1000; i++) { 1323 /* 1324 * Wait a bit for the reset to complete before peeking 1325 * at the chip again. 1326 */ 1327 delay(10); 1328 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1329 break; 1330 } 1331 1332 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1333 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1334 1335 delay(1000); 1336 } 1337 1338 /* 1339 * ae_init: [ ifnet interface function ] 1340 * 1341 * Initialize the interface. Must be called at splnet(). 1342 */ 1343 static int 1344 ae_init(struct ifnet *ifp) 1345 { 1346 struct ae_softc *sc = ifp->if_softc; 1347 struct ae_txsoft *txs; 1348 struct ae_rxsoft *rxs; 1349 uint8_t *enaddr; 1350 int i, error = 0; 1351 1352 if ((error = ae_enable(sc)) != 0) 1353 goto out; 1354 1355 /* 1356 * Cancel any pending I/O. 1357 */ 1358 ae_stop(ifp, 0); 1359 1360 /* 1361 * Reset the chip to a known state. 1362 */ 1363 ae_reset(sc); 1364 1365 /* 1366 * Initialize the BUSMODE register. 1367 */ 1368 AE_WRITE(sc, CSR_BUSMODE, 1369 /* XXX: not sure if this is a good thing or not... */ 1370 //BUSMODE_ALIGN_16B | 1371 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1372 AE_BARRIER(sc); 1373 1374 /* 1375 * Initialize the transmit descriptor ring. 1376 */ 1377 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1378 for (i = 0; i < AE_NTXDESC; i++) { 1379 sc->sc_txdescs[i].ad_ctl = 0; 1380 sc->sc_txdescs[i].ad_bufaddr2 = 1381 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1382 } 1383 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1384 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1385 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1386 sc->sc_txfree = AE_NTXDESC; 1387 sc->sc_txnext = 0; 1388 1389 /* 1390 * Initialize the transmit job descriptors. 1391 */ 1392 SIMPLEQ_INIT(&sc->sc_txfreeq); 1393 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1394 for (i = 0; i < AE_TXQUEUELEN; i++) { 1395 txs = &sc->sc_txsoft[i]; 1396 txs->txs_mbuf = NULL; 1397 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1398 } 1399 1400 /* 1401 * Initialize the receive descriptor and receive job 1402 * descriptor rings. 1403 */ 1404 for (i = 0; i < AE_NRXDESC; i++) { 1405 rxs = &sc->sc_rxsoft[i]; 1406 if (rxs->rxs_mbuf == NULL) { 1407 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1408 printf("%s: unable to allocate or map rx " 1409 "buffer %d, error = %d\n", 1410 sc->sc_dev.dv_xname, i, error); 1411 /* 1412 * XXX Should attempt to run with fewer receive 1413 * XXX buffers instead of just failing. 1414 */ 1415 ae_rxdrain(sc); 1416 goto out; 1417 } 1418 } else 1419 AE_INIT_RXDESC(sc, i); 1420 } 1421 sc->sc_rxptr = 0; 1422 1423 /* 1424 * Initialize the interrupt mask and enable interrupts. 1425 */ 1426 /* normal interrupts */ 1427 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1428 1429 /* abnormal interrupts */ 1430 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1431 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1432 1433 sc->sc_rxint_mask = STATUS_RI|STATUS_RU; 1434 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT; 1435 1436 sc->sc_rxint_mask &= sc->sc_inten; 1437 sc->sc_txint_mask &= sc->sc_inten; 1438 1439 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1440 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1441 1442 /* 1443 * Give the transmit and receive rings to the chip. 1444 */ 1445 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1446 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1447 AE_BARRIER(sc); 1448 1449 /* 1450 * Set the station address. 1451 */ 1452 enaddr = LLADDR(ifp->if_sadl); 1453 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1454 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1455 enaddr[1] << 8 | enaddr[0]); 1456 AE_BARRIER(sc); 1457 1458 /* 1459 * Set the receive filter. This will start the transmit and 1460 * receive processes. 1461 */ 1462 ae_filter_setup(sc); 1463 1464 /* 1465 * Set the current media. 1466 */ 1467 ae_mediachange(ifp); 1468 1469 /* 1470 * Start the mac. 1471 */ 1472 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1473 AE_BARRIER(sc); 1474 1475 /* 1476 * Write out the opmode. 1477 */ 1478 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1479 ae_txthresh[sc->sc_txthresh].txth_opmode); 1480 /* 1481 * Start the receive process. 1482 */ 1483 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1484 AE_BARRIER(sc); 1485 1486 if (sc->sc_tick != NULL) { 1487 /* Start the one second clock. */ 1488 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1489 } 1490 1491 /* 1492 * Note that the interface is now running. 1493 */ 1494 ifp->if_flags |= IFF_RUNNING; 1495 ifp->if_flags &= ~IFF_OACTIVE; 1496 sc->sc_if_flags = ifp->if_flags; 1497 1498 out: 1499 if (error) { 1500 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1501 ifp->if_timer = 0; 1502 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1503 } 1504 return (error); 1505 } 1506 1507 /* 1508 * ae_enable: 1509 * 1510 * Enable the chip. 1511 */ 1512 static int 1513 ae_enable(struct ae_softc *sc) 1514 { 1515 1516 if (AE_IS_ENABLED(sc) == 0) { 1517 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1518 ae_intr, sc); 1519 if (sc->sc_ih == NULL) { 1520 printf("%s: unable to establish interrupt\n", 1521 sc->sc_dev.dv_xname); 1522 return (EIO); 1523 } 1524 sc->sc_flags |= AE_ENABLED; 1525 } 1526 return (0); 1527 } 1528 1529 /* 1530 * ae_disable: 1531 * 1532 * Disable the chip. 1533 */ 1534 static void 1535 ae_disable(struct ae_softc *sc) 1536 { 1537 1538 if (AE_IS_ENABLED(sc)) { 1539 arbus_intr_disestablish(sc->sc_ih); 1540 sc->sc_flags &= ~AE_ENABLED; 1541 } 1542 } 1543 1544 /* 1545 * ae_power: 1546 * 1547 * Power management (suspend/resume) hook. 1548 */ 1549 static void 1550 ae_power(int why, void *arg) 1551 { 1552 struct ae_softc *sc = arg; 1553 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1554 int s; 1555 1556 printf("power called: %d, %x\n", why, (uint32_t)arg); 1557 s = splnet(); 1558 switch (why) { 1559 case PWR_STANDBY: 1560 /* do nothing! */ 1561 break; 1562 case PWR_SUSPEND: 1563 ae_stop(ifp, 0); 1564 ae_disable(sc); 1565 break; 1566 case PWR_RESUME: 1567 if (ifp->if_flags & IFF_UP) { 1568 ae_enable(sc); 1569 ae_init(ifp); 1570 } 1571 break; 1572 case PWR_SOFTSUSPEND: 1573 case PWR_SOFTSTANDBY: 1574 case PWR_SOFTRESUME: 1575 break; 1576 } 1577 splx(s); 1578 } 1579 1580 /* 1581 * ae_rxdrain: 1582 * 1583 * Drain the receive queue. 1584 */ 1585 static void 1586 ae_rxdrain(struct ae_softc *sc) 1587 { 1588 struct ae_rxsoft *rxs; 1589 int i; 1590 1591 for (i = 0; i < AE_NRXDESC; i++) { 1592 rxs = &sc->sc_rxsoft[i]; 1593 if (rxs->rxs_mbuf != NULL) { 1594 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1595 m_freem(rxs->rxs_mbuf); 1596 rxs->rxs_mbuf = NULL; 1597 } 1598 } 1599 } 1600 1601 /* 1602 * ae_stop: [ ifnet interface function ] 1603 * 1604 * Stop transmission on the interface. 1605 */ 1606 static void 1607 ae_stop(struct ifnet *ifp, int disable) 1608 { 1609 struct ae_softc *sc = ifp->if_softc; 1610 struct ae_txsoft *txs; 1611 1612 if (sc->sc_tick != NULL) { 1613 /* Stop the one second clock. */ 1614 callout_stop(&sc->sc_tick_callout); 1615 } 1616 1617 /* Down the MII. */ 1618 mii_down(&sc->sc_mii); 1619 1620 /* Disable interrupts. */ 1621 AE_WRITE(sc, CSR_INTEN, 0); 1622 1623 /* Stop the transmit and receive processes. */ 1624 AE_WRITE(sc, CSR_OPMODE, 0); 1625 AE_WRITE(sc, CSR_RXLIST, 0); 1626 AE_WRITE(sc, CSR_TXLIST, 0); 1627 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1628 AE_BARRIER(sc); 1629 1630 /* 1631 * Release any queued transmit buffers. 1632 */ 1633 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1634 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1635 if (txs->txs_mbuf != NULL) { 1636 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1637 m_freem(txs->txs_mbuf); 1638 txs->txs_mbuf = NULL; 1639 } 1640 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1641 } 1642 1643 if (disable) { 1644 ae_rxdrain(sc); 1645 ae_disable(sc); 1646 } 1647 1648 /* 1649 * Mark the interface down and cancel the watchdog timer. 1650 */ 1651 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1652 sc->sc_if_flags = ifp->if_flags; 1653 ifp->if_timer = 0; 1654 1655 /* 1656 * Reset the chip (needed on some flavors to actually disable it). 1657 */ 1658 ae_reset(sc); 1659 } 1660 1661 /* 1662 * ae_add_rxbuf: 1663 * 1664 * Add a receive buffer to the indicated descriptor. 1665 */ 1666 static int 1667 ae_add_rxbuf(struct ae_softc *sc, int idx) 1668 { 1669 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1670 struct mbuf *m; 1671 int error; 1672 1673 MGETHDR(m, M_DONTWAIT, MT_DATA); 1674 if (m == NULL) 1675 return (ENOBUFS); 1676 1677 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1678 MCLGET(m, M_DONTWAIT); 1679 if ((m->m_flags & M_EXT) == 0) { 1680 m_freem(m); 1681 return (ENOBUFS); 1682 } 1683 1684 if (rxs->rxs_mbuf != NULL) 1685 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1686 1687 rxs->rxs_mbuf = m; 1688 1689 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1690 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1691 BUS_DMA_READ|BUS_DMA_NOWAIT); 1692 if (error) { 1693 printf("%s: can't load rx DMA map %d, error = %d\n", 1694 sc->sc_dev.dv_xname, idx, error); 1695 panic("ae_add_rxbuf"); /* XXX */ 1696 } 1697 1698 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1699 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1700 1701 AE_INIT_RXDESC(sc, idx); 1702 1703 return (0); 1704 } 1705 1706 /* 1707 * ae_filter_setup: 1708 * 1709 * Set the chip's receive filter. 1710 */ 1711 static void 1712 ae_filter_setup(struct ae_softc *sc) 1713 { 1714 struct ethercom *ec = &sc->sc_ethercom; 1715 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1716 struct ether_multi *enm; 1717 struct ether_multistep step; 1718 uint32_t hash, mchash[2]; 1719 uint32_t macctl = 0; 1720 1721 /* 1722 * If the chip is running, we need to reset the interface, 1723 * and will revisit here (with IFF_RUNNING) clear. The 1724 * chip seems to really not like to have its multicast 1725 * filter programmed without a reset. 1726 */ 1727 if (ifp->if_flags & IFF_RUNNING) { 1728 (void) ae_init(ifp); 1729 return; 1730 } 1731 1732 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1733 sc->sc_dev.dv_xname, sc->sc_flags)); 1734 1735 macctl = AE_READ(sc, CSR_MACCTL); 1736 macctl &= ~(MACCTL_PR | MACCTL_PM); 1737 macctl |= MACCTL_HASH; 1738 macctl |= MACCTL_HBD; 1739 macctl |= MACCTL_PR; 1740 1741 if (ifp->if_flags & IFF_PROMISC) { 1742 macctl |= MACCTL_PR; 1743 goto allmulti; 1744 } 1745 1746 mchash[0] = mchash[1] = 0; 1747 1748 ETHER_FIRST_MULTI(step, ec, enm); 1749 while (enm != NULL) { 1750 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1751 /* 1752 * We must listen to a range of multicast addresses. 1753 * For now, just accept all multicasts, rather than 1754 * trying to set only those filter bits needed to match 1755 * the range. (At this time, the only use of address 1756 * ranges is for IP multicast routing, for which the 1757 * range is big enough to require all bits set.) 1758 */ 1759 goto allmulti; 1760 } 1761 1762 /* Verify whether we use big or little endian hashes */ 1763 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1764 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1765 ETHER_NEXT_MULTI(step, enm); 1766 } 1767 ifp->if_flags &= ~IFF_ALLMULTI; 1768 goto setit; 1769 1770 allmulti: 1771 ifp->if_flags |= IFF_ALLMULTI; 1772 mchash[0] = mchash[1] = 0xffffffff; 1773 macctl |= MACCTL_PM; 1774 1775 setit: 1776 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1777 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1778 1779 AE_WRITE(sc, CSR_MACCTL, macctl); 1780 AE_BARRIER(sc); 1781 1782 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1783 sc->sc_dev.dv_xname, macctl)); 1784 } 1785 1786 /* 1787 * ae_idle: 1788 * 1789 * Cause the transmit and/or receive processes to go idle. 1790 */ 1791 void 1792 ae_idle(struct ae_softc *sc, u_int32_t bits) 1793 { 1794 static const char * const txstate_names[] = { 1795 "STOPPED", 1796 "RUNNING - FETCH", 1797 "RUNNING - WAIT", 1798 "RUNNING - READING", 1799 "-- RESERVED --", 1800 "RUNNING - SETUP", 1801 "SUSPENDED", 1802 "RUNNING - CLOSE", 1803 }; 1804 static const char * const rxstate_names[] = { 1805 "STOPPED", 1806 "RUNNING - FETCH", 1807 "RUNNING - CHECK", 1808 "RUNNING - WAIT", 1809 "SUSPENDED", 1810 "RUNNING - CLOSE", 1811 "RUNNING - FLUSH", 1812 "RUNNING - QUEUE", 1813 }; 1814 1815 u_int32_t csr, ackmask = 0; 1816 int i; 1817 1818 if (bits & OPMODE_ST) 1819 ackmask |= STATUS_TPS; 1820 1821 if (bits & OPMODE_SR) 1822 ackmask |= STATUS_RPS; 1823 1824 AE_CLR(sc, CSR_OPMODE, bits); 1825 1826 for (i = 0; i < 1000; i++) { 1827 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1828 break; 1829 delay(10); 1830 } 1831 1832 csr = AE_READ(sc, CSR_STATUS); 1833 if ((csr & ackmask) != ackmask) { 1834 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1835 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1836 printf("%s: transmit process failed to idle: " 1837 "state %s\n", sc->sc_dev.dv_xname, 1838 txstate_names[(csr & STATUS_TS) >> 20]); 1839 } 1840 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1841 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1842 printf("%s: receive process failed to idle: " 1843 "state %s\n", sc->sc_dev.dv_xname, 1844 rxstate_names[(csr & STATUS_RS) >> 17]); 1845 } 1846 } 1847 } 1848 1849 /***************************************************************************** 1850 * Generic media support functions. 1851 *****************************************************************************/ 1852 1853 /* 1854 * ae_mediastatus: [ifmedia interface function] 1855 * 1856 * Query the current media. 1857 */ 1858 void 1859 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1860 { 1861 struct ae_softc *sc = ifp->if_softc; 1862 1863 if (AE_IS_ENABLED(sc) == 0) { 1864 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1865 ifmr->ifm_status = 0; 1866 return; 1867 } 1868 1869 mii_pollstat(&sc->sc_mii); 1870 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1871 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1872 } 1873 1874 /* 1875 * ae_mediachange: [ifmedia interface function] 1876 * 1877 * Update the current media. 1878 */ 1879 int 1880 ae_mediachange(struct ifnet *ifp) 1881 { 1882 struct ae_softc *sc = ifp->if_softc; 1883 1884 if ((ifp->if_flags & IFF_UP) == 0) 1885 return (0); 1886 1887 mii_mediachg(&sc->sc_mii); 1888 return (0); 1889 } 1890 1891 /***************************************************************************** 1892 * Support functions for MII-attached media. 1893 *****************************************************************************/ 1894 1895 /* 1896 * ae_mii_tick: 1897 * 1898 * One second timer, used to tick the MII. 1899 */ 1900 static void 1901 ae_mii_tick(void *arg) 1902 { 1903 struct ae_softc *sc = arg; 1904 int s; 1905 1906 if (!device_is_active(&sc->sc_dev)) 1907 return; 1908 1909 s = splnet(); 1910 mii_tick(&sc->sc_mii); 1911 splx(s); 1912 1913 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1914 } 1915 1916 /* 1917 * ae_mii_statchg: [mii interface function] 1918 * 1919 * Callback from PHY when media changes. 1920 */ 1921 static void 1922 ae_mii_statchg(struct device *self) 1923 { 1924 struct ae_softc *sc = (struct ae_softc *)self; 1925 uint32_t macctl, flowc; 1926 1927 //opmode = AE_READ(sc, CSR_OPMODE); 1928 macctl = AE_READ(sc, CSR_MACCTL); 1929 1930 /* XXX: do we need to do this? */ 1931 /* Idle the transmit and receive processes. */ 1932 //ae_idle(sc, OPMODE_ST|OPMODE_SR); 1933 1934 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1935 flowc = FLOWC_FCE; 1936 macctl &= ~MACCTL_DRO; 1937 macctl |= MACCTL_FDX; 1938 } else { 1939 flowc = 0; /* cannot do flow control in HDX */ 1940 macctl |= MACCTL_DRO; 1941 macctl &= ~MACCTL_FDX; 1942 } 1943 1944 AE_WRITE(sc, CSR_FLOWC, flowc); 1945 AE_WRITE(sc, CSR_MACCTL, macctl); 1946 1947 /* restore operational mode */ 1948 //AE_WRITE(sc, CSR_OPMODE, opmode); 1949 AE_BARRIER(sc); 1950 } 1951 1952 /* 1953 * ae_mii_readreg: 1954 * 1955 * Read a PHY register. 1956 */ 1957 static int 1958 ae_mii_readreg(struct device *self, int phy, int reg) 1959 { 1960 struct ae_softc *sc = (struct ae_softc *)self; 1961 uint32_t addr; 1962 int i; 1963 1964 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1965 AE_WRITE(sc, CSR_MIIADDR, addr); 1966 AE_BARRIER(sc); 1967 for (i = 0; i < 100000000; i++) { 1968 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1969 break; 1970 } 1971 1972 return (AE_READ(sc, CSR_MIIDATA) & 0xffff); 1973 } 1974 1975 /* 1976 * ae_mii_writereg: 1977 * 1978 * Write a PHY register. 1979 */ 1980 static void 1981 ae_mii_writereg(struct device *self, int phy, int reg, int val) 1982 { 1983 struct ae_softc *sc = (struct ae_softc *)self; 1984 uint32_t addr; 1985 int i; 1986 1987 /* write the data register */ 1988 AE_WRITE(sc, CSR_MIIDATA, val); 1989 1990 /* write the address to latch it in */ 1991 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1992 MIIADDR_WRITE; 1993 AE_WRITE(sc, CSR_MIIADDR, addr); 1994 AE_BARRIER(sc); 1995 1996 for (i = 0; i < 100000000; i++) { 1997 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1998 break; 1999 } 2000 } 2001
Indexes created Wed Sep 24 15:09:51 GMT 2025