if_ae.c revision 1.37.2.1
1 /* $Id: if_ae.c,v 1.37.2.1 2020/02/29 20:18:27 ad Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the onboard ethernet MAC found on the AR5312 74 * chip's AHB bus. 75 * 76 * This device is very simliar to the tulip in most regards, and 77 * the code is directly derived from NetBSD's tulip.c. However, it 78 * is different enough that it did not seem to be a good idea to 79 * add further complexity to the tulip driver, so we have our own. 80 * 81 * Also tulip has a lot of complexity in it for various parts/options 82 * that we don't need, and on these little boxes with only ~8MB RAM, we 83 * don't want any extra bloat. 84 */ 85 86 /* 87 * TODO: 88 * 89 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 90 * inbound packets on a half-word boundary, which would make life easier 91 * for TCP/IP. (Aligning IP headers on a word.) 92 * 93 * 2) There is stuff in original tulip to shut down the device when reacting 94 * to a change in link status. Is that needed. 95 * 96 * 3) Test with variety of 10/100 HDX/FDX scenarios. 97 * 98 */ 99 100 #include <sys/cdefs.h> 101 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.37.2.1 2020/02/29 20:18:27 ad Exp $"); 102 103 104 #include <sys/param.h> 105 #include <sys/bus.h> 106 #include <sys/callout.h> 107 #include <sys/device.h> 108 #include <sys/endian.h> 109 #include <sys/errno.h> 110 #include <sys/intr.h> 111 #include <sys/ioctl.h> 112 #include <sys/kernel.h> 113 #include <sys/malloc.h> 114 #include <sys/mbuf.h> 115 #include <sys/socket.h> 116 117 #include <uvm/uvm_extern.h> 118 119 #include <net/if.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/if_ether.h> 123 124 #include <net/bpf.h> 125 126 #include <dev/mii/mii.h> 127 #include <dev/mii/miivar.h> 128 #include <dev/mii/mii_bitbang.h> 129 130 #include <mips/atheros/include/arbusvar.h> 131 #include <mips/atheros/dev/aereg.h> 132 #include <mips/atheros/dev/aevar.h> 133 134 static const struct { 135 uint32_t txth_opmode; /* OPMODE bits */ 136 const char *txth_name; /* name of mode */ 137 } ae_txthresh[] = { 138 { OPMODE_TR_32, "32 words" }, 139 { OPMODE_TR_64, "64 words" }, 140 { OPMODE_TR_128, "128 words" }, 141 { OPMODE_TR_256, "256 words" }, 142 { OPMODE_SF, "store and forward mode" }, 143 { 0, NULL }, 144 }; 145 146 static int ae_match(device_t, struct cfdata *, void *); 147 static void ae_attach(device_t, device_t, void *); 148 static int ae_detach(device_t, int); 149 static int ae_activate(device_t, enum devact); 150 151 static int ae_ifflags_cb(struct ethercom *); 152 static void ae_reset(struct ae_softc *); 153 static void ae_idle(struct ae_softc *, uint32_t); 154 155 static void ae_start(struct ifnet *); 156 static void ae_watchdog(struct ifnet *); 157 static int ae_ioctl(struct ifnet *, u_long, void *); 158 static int ae_init(struct ifnet *); 159 static void ae_stop(struct ifnet *, int); 160 161 static void ae_shutdown(void *); 162 163 static void ae_rxdrain(struct ae_softc *); 164 static int ae_add_rxbuf(struct ae_softc *, int); 165 166 static int ae_enable(struct ae_softc *); 167 static void ae_disable(struct ae_softc *); 168 static void ae_power(int, void *); 169 170 static void ae_filter_setup(struct ae_softc *); 171 172 static int ae_intr(void *); 173 static void ae_rxintr(struct ae_softc *); 174 static void ae_txintr(struct ae_softc *); 175 176 static void ae_mii_tick(void *); 177 static void ae_mii_statchg(struct ifnet *); 178 179 static int ae_mii_readreg(device_t, int, int, uint16_t *); 180 static int ae_mii_writereg(device_t, int, int, uint16_t); 181 182 #ifdef AE_DEBUG 183 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 184 printf x 185 #else 186 #define DPRINTF(sc, x) /* nothing */ 187 #endif 188 189 #ifdef AE_STATS 190 static void ae_print_stats(struct ae_softc *); 191 #endif 192 193 CFATTACH_DECL_NEW(ae, sizeof(struct ae_softc), 194 ae_match, ae_attach, ae_detach, ae_activate); 195 196 /* 197 * ae_match: 198 * 199 * Check for a device match. 200 */ 201 int 202 ae_match(device_t parent, struct cfdata *cf, void *aux) 203 { 204 struct arbus_attach_args *aa = aux; 205 206 if (strcmp(aa->aa_name, cf->cf_name) == 0) 207 return 1; 208 209 return 0; 210 211 } 212 213 /* 214 * ae_attach: 215 * 216 * Attach an ae interface to the system. 217 */ 218 void 219 ae_attach(device_t parent, device_t self, void *aux) 220 { 221 const uint8_t *enaddr; 222 prop_data_t ea; 223 struct ae_softc *sc = device_private(self); 224 struct arbus_attach_args *aa = aux; 225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 226 struct mii_data * const mii = &sc->sc_mii; 227 int i, error; 228 229 sc->sc_dev = self; 230 231 callout_init(&sc->sc_tick_callout, 0); 232 233 printf(": Atheros AR531X 10/100 Ethernet\n"); 234 235 /* 236 * Try to get MAC address. 237 */ 238 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-address"); 239 if (ea == NULL) { 240 printf("%s: unable to get mac-addr property\n", 241 device_xname(sc->sc_dev)); 242 return; 243 } 244 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 245 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 246 enaddr = prop_data_data_nocopy(ea); 247 248 /* Announce ourselves. */ 249 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 250 ether_sprintf(enaddr)); 251 252 sc->sc_cirq = aa->aa_cirq; 253 sc->sc_mirq = aa->aa_mirq; 254 sc->sc_st = aa->aa_bst; 255 sc->sc_dmat = aa->aa_dmat; 256 257 SIMPLEQ_INIT(&sc->sc_txfreeq); 258 SIMPLEQ_INIT(&sc->sc_txdirtyq); 259 260 /* 261 * Map registers. 262 */ 263 sc->sc_size = aa->aa_size; 264 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 265 &sc->sc_sh)) != 0) { 266 printf("%s: unable to map registers, error = %d\n", 267 device_xname(sc->sc_dev), error); 268 goto fail_0; 269 } 270 271 /* 272 * Allocate the control data structures, and create and load the 273 * DMA map for it. 274 */ 275 if ((error = bus_dmamem_alloc(sc->sc_dmat, 276 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 277 1, &sc->sc_cdnseg, 0)) != 0) { 278 printf("%s: unable to allocate control data, error = %d\n", 279 device_xname(sc->sc_dev), error); 280 goto fail_1; 281 } 282 283 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 284 sizeof(struct ae_control_data), (void **)&sc->sc_control_data, 285 BUS_DMA_COHERENT)) != 0) { 286 printf("%s: unable to map control data, error = %d\n", 287 device_xname(sc->sc_dev), error); 288 goto fail_2; 289 } 290 291 if ((error = bus_dmamap_create(sc->sc_dmat, 292 sizeof(struct ae_control_data), 1, 293 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 294 printf("%s: unable to create control data DMA map, " 295 "error = %d\n", device_xname(sc->sc_dev), error); 296 goto fail_3; 297 } 298 299 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 300 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 301 0)) != 0) { 302 printf("%s: unable to load control data DMA map, error = %d\n", 303 device_xname(sc->sc_dev), error); 304 goto fail_4; 305 } 306 307 /* 308 * Create the transmit buffer DMA maps. 309 */ 310 for (i = 0; i < AE_TXQUEUELEN; i++) { 311 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 312 AE_NTXSEGS, MCLBYTES, 0, 0, 313 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 314 printf("%s: unable to create tx DMA map %d, " 315 "error = %d\n", device_xname(sc->sc_dev), i, error); 316 goto fail_5; 317 } 318 } 319 320 /* 321 * Create the receive buffer DMA maps. 322 */ 323 for (i = 0; i < AE_NRXDESC; i++) { 324 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 325 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 326 printf("%s: unable to create rx DMA map %d, " 327 "error = %d\n", device_xname(sc->sc_dev), i, error); 328 goto fail_6; 329 } 330 sc->sc_rxsoft[i].rxs_mbuf = NULL; 331 } 332 333 /* 334 * Reset the chip to a known state. 335 */ 336 ae_reset(sc); 337 338 /* 339 * From this point forward, the attachment cannot fail. A failure 340 * before this point releases all resources that may have been 341 * allocated. 342 */ 343 sc->sc_flags |= AE_ATTACHED; 344 345 /* 346 * Initialize our media structures. This may probe the MII, if 347 * present. 348 */ 349 mii->mii_ifp = ifp; 350 mii->mii_readreg = ae_mii_readreg; 351 mii->mii_writereg = ae_mii_writereg; 352 mii->mii_statchg = ae_mii_statchg; 353 sc->sc_ethercom.ec_mii = mii; 354 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 355 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 356 MII_OFFSET_ANY, 0); 357 358 if (LIST_FIRST(&mii->mii_phys) == NULL) { 359 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 360 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 361 } else 362 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 363 364 sc->sc_tick = ae_mii_tick; 365 366 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 sc->sc_if_flags = ifp->if_flags; 370 ifp->if_ioctl = ae_ioctl; 371 ifp->if_start = ae_start; 372 ifp->if_watchdog = ae_watchdog; 373 ifp->if_init = ae_init; 374 ifp->if_stop = ae_stop; 375 IFQ_SET_READY(&ifp->if_snd); 376 377 /* 378 * We can support 802.1Q VLAN-sized frames. 379 */ 380 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 381 382 /* 383 * Attach the interface. 384 */ 385 if_attach(ifp); 386 if_deferred_start_init(ifp, NULL); 387 ether_ifattach(ifp, enaddr); 388 ether_set_ifflags_cb(&sc->sc_ethercom, ae_ifflags_cb); 389 390 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 391 RND_TYPE_NET, RND_FLAG_DEFAULT); 392 393 /* 394 * Make sure the interface is shutdown during reboot. 395 */ 396 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 397 if (sc->sc_sdhook == NULL) 398 printf("%s: WARNING: unable to establish shutdown hook\n", 399 device_xname(sc->sc_dev)); 400 401 /* 402 * Add a suspend hook to make sure we come back up after a 403 * resume. 404 */ 405 sc->sc_powerhook = powerhook_establish(device_xname(sc->sc_dev), 406 ae_power, sc); 407 if (sc->sc_powerhook == NULL) 408 printf("%s: WARNING: unable to establish power hook\n", 409 device_xname(sc->sc_dev)); 410 return; 411 412 /* 413 * Free any resources we've allocated during the failed attach 414 * attempt. Do this in reverse order and fall through. 415 */ 416 fail_6: 417 for (i = 0; i < AE_NRXDESC; i++) { 418 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 419 bus_dmamap_destroy(sc->sc_dmat, 420 sc->sc_rxsoft[i].rxs_dmamap); 421 } 422 fail_5: 423 for (i = 0; i < AE_TXQUEUELEN; i++) { 424 if (sc->sc_txsoft[i].txs_dmamap != NULL) 425 bus_dmamap_destroy(sc->sc_dmat, 426 sc->sc_txsoft[i].txs_dmamap); 427 } 428 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 429 fail_4: 430 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 431 fail_3: 432 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 433 sizeof(struct ae_control_data)); 434 fail_2: 435 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 436 fail_1: 437 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 438 fail_0: 439 return; 440 } 441 442 /* 443 * ae_activate: 444 * 445 * Handle device activation/deactivation requests. 446 */ 447 int 448 ae_activate(device_t self, enum devact act) 449 { 450 struct ae_softc *sc = device_private(self); 451 452 switch (act) { 453 case DVACT_DEACTIVATE: 454 if_deactivate(&sc->sc_ethercom.ec_if); 455 return 0; 456 default: 457 return EOPNOTSUPP; 458 } 459 } 460 461 /* 462 * ae_detach: 463 * 464 * Detach a device interface. 465 */ 466 int 467 ae_detach(device_t self, int flags) 468 { 469 struct ae_softc *sc = device_private(self); 470 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 471 struct ae_rxsoft *rxs; 472 struct ae_txsoft *txs; 473 int i; 474 475 /* 476 * Succeed now if there isn't any work to do. 477 */ 478 if ((sc->sc_flags & AE_ATTACHED) == 0) 479 return (0); 480 481 /* Unhook our tick handler. */ 482 if (sc->sc_tick) 483 callout_stop(&sc->sc_tick_callout); 484 485 /* Detach all PHYs */ 486 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 487 488 rnd_detach_source(&sc->sc_rnd_source); 489 ether_ifdetach(ifp); 490 if_detach(ifp); 491 492 /* Delete all remaining media. */ 493 ifmedia_fini(&sc->sc_mii.mii_media); 494 495 for (i = 0; i < AE_NRXDESC; i++) { 496 rxs = &sc->sc_rxsoft[i]; 497 if (rxs->rxs_mbuf != NULL) { 498 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 499 m_freem(rxs->rxs_mbuf); 500 rxs->rxs_mbuf = NULL; 501 } 502 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 503 } 504 for (i = 0; i < AE_TXQUEUELEN; i++) { 505 txs = &sc->sc_txsoft[i]; 506 if (txs->txs_mbuf != NULL) { 507 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 508 m_freem(txs->txs_mbuf); 509 txs->txs_mbuf = NULL; 510 } 511 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 512 } 513 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 514 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 515 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 516 sizeof(struct ae_control_data)); 517 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 518 519 shutdownhook_disestablish(sc->sc_sdhook); 520 powerhook_disestablish(sc->sc_powerhook); 521 522 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 523 524 525 return (0); 526 } 527 528 /* 529 * ae_shutdown: 530 * 531 * Make sure the interface is stopped at reboot time. 532 */ 533 static void 534 ae_shutdown(void *arg) 535 { 536 struct ae_softc *sc = arg; 537 538 ae_stop(&sc->sc_ethercom.ec_if, 1); 539 } 540 541 /* 542 * ae_start: [ifnet interface function] 543 * 544 * Start packet transmission on the interface. 545 */ 546 static void 547 ae_start(struct ifnet *ifp) 548 { 549 struct ae_softc *sc = ifp->if_softc; 550 struct mbuf *m0, *m; 551 struct ae_txsoft *txs; 552 bus_dmamap_t dmamap; 553 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 554 555 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 556 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 557 558 559 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 560 return; 561 562 /* 563 * Remember the previous number of free descriptors and 564 * the first descriptor we'll use. 565 */ 566 ofree = sc->sc_txfree; 567 firsttx = sc->sc_txnext; 568 569 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 570 device_xname(sc->sc_dev), ofree, firsttx)); 571 572 /* 573 * Loop through the send queue, setting up transmit descriptors 574 * until we drain the queue, or use up all available transmit 575 * descriptors. 576 */ 577 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 578 sc->sc_txfree != 0) { 579 /* 580 * Grab a packet off the queue. 581 */ 582 IFQ_POLL(&ifp->if_snd, m0); 583 if (m0 == NULL) 584 break; 585 m = NULL; 586 587 dmamap = txs->txs_dmamap; 588 589 /* 590 * Load the DMA map. If this fails, the packet either 591 * didn't fit in the alloted number of segments, or we were 592 * short on resources. In this case, we'll copy and try 593 * again. 594 */ 595 if (((mtod(m0, uintptr_t) & 3) != 0) || 596 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 597 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 598 MGETHDR(m, M_DONTWAIT, MT_DATA); 599 if (m == NULL) { 600 printf("%s: unable to allocate Tx mbuf\n", 601 device_xname(sc->sc_dev)); 602 break; 603 } 604 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 605 if (m0->m_pkthdr.len > MHLEN) { 606 MCLGET(m, M_DONTWAIT); 607 if ((m->m_flags & M_EXT) == 0) { 608 printf("%s: unable to allocate Tx " 609 "cluster\n", device_xname(sc->sc_dev)); 610 m_freem(m); 611 break; 612 } 613 } 614 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 615 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 616 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 617 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 618 if (error) { 619 printf("%s: unable to load Tx buffer, " 620 "error = %d\n", device_xname(sc->sc_dev), 621 error); 622 break; 623 } 624 } 625 626 /* 627 * Ensure we have enough descriptors free to describe 628 * the packet. 629 */ 630 if (dmamap->dm_nsegs > sc->sc_txfree) { 631 /* 632 * Not enough free descriptors to transmit this 633 * packet. We haven't committed to anything yet, 634 * so just unload the DMA map, put the packet 635 * back on the queue, and punt. Notify the upper 636 * layer that there are no more slots left. 637 * 638 * XXX We could allocate an mbuf and copy, but 639 * XXX it is worth it? 640 */ 641 ifp->if_flags |= IFF_OACTIVE; 642 bus_dmamap_unload(sc->sc_dmat, dmamap); 643 if (m != NULL) 644 m_freem(m); 645 break; 646 } 647 648 IFQ_DEQUEUE(&ifp->if_snd, m0); 649 if (m != NULL) { 650 m_freem(m0); 651 m0 = m; 652 } 653 654 /* 655 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 656 */ 657 658 /* Sync the DMA map. */ 659 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 660 BUS_DMASYNC_PREWRITE); 661 662 /* 663 * Initialize the transmit descriptors. 664 */ 665 for (nexttx = sc->sc_txnext, seg = 0; 666 seg < dmamap->dm_nsegs; 667 seg++, nexttx = AE_NEXTTX(nexttx)) { 668 /* 669 * If this is the first descriptor we're 670 * enqueueing, don't set the OWN bit just 671 * yet. That could cause a race condition. 672 * We'll do it below. 673 */ 674 sc->sc_txdescs[nexttx].ad_status = 675 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 676 sc->sc_txdescs[nexttx].ad_bufaddr1 = 677 dmamap->dm_segs[seg].ds_addr; 678 sc->sc_txdescs[nexttx].ad_ctl = 679 (dmamap->dm_segs[seg].ds_len << 680 ADCTL_SIZE1_SHIFT) | 681 (nexttx == (AE_NTXDESC - 1) ? 682 ADCTL_ER : 0); 683 lasttx = nexttx; 684 } 685 686 KASSERT(lasttx != -1); 687 688 /* Set `first segment' and `last segment' appropriately. */ 689 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 690 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 691 692 #ifdef AE_DEBUG 693 if (ifp->if_flags & IFF_DEBUG) { 694 printf(" txsoft %p transmit chain:\n", txs); 695 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 696 printf(" descriptor %d:\n", seg); 697 printf(" ad_status: 0x%08x\n", 698 sc->sc_txdescs[seg].ad_status); 699 printf(" ad_ctl: 0x%08x\n", 700 sc->sc_txdescs[seg].ad_ctl); 701 printf(" ad_bufaddr1: 0x%08x\n", 702 sc->sc_txdescs[seg].ad_bufaddr1); 703 printf(" ad_bufaddr2: 0x%08x\n", 704 sc->sc_txdescs[seg].ad_bufaddr2); 705 if (seg == lasttx) 706 break; 707 } 708 } 709 #endif 710 711 /* Sync the descriptors we're using. */ 712 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 713 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 714 715 /* 716 * Store a pointer to the packet so we can free it later, 717 * and remember what txdirty will be once the packet is 718 * done. 719 */ 720 txs->txs_mbuf = m0; 721 txs->txs_firstdesc = sc->sc_txnext; 722 txs->txs_lastdesc = lasttx; 723 txs->txs_ndescs = dmamap->dm_nsegs; 724 725 /* Advance the tx pointer. */ 726 sc->sc_txfree -= dmamap->dm_nsegs; 727 sc->sc_txnext = nexttx; 728 729 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 730 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 731 732 /* 733 * Pass the packet to any BPF listeners. 734 */ 735 bpf_mtap(ifp, m0, BPF_D_OUT); 736 } 737 738 if (txs == NULL || sc->sc_txfree == 0) { 739 /* No more slots left; notify upper layer. */ 740 ifp->if_flags |= IFF_OACTIVE; 741 } 742 743 if (sc->sc_txfree != ofree) { 744 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 745 device_xname(sc->sc_dev), lasttx, firsttx)); 746 /* 747 * Cause a transmit interrupt to happen on the 748 * last packet we enqueued. 749 */ 750 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 751 AE_CDTXSYNC(sc, lasttx, 1, 752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 753 754 /* 755 * The entire packet chain is set up. Give the 756 * first descriptor to the chip now. 757 */ 758 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 759 AE_CDTXSYNC(sc, firsttx, 1, 760 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 761 762 /* Wake up the transmitter. */ 763 /* XXX USE AUTOPOLLING? */ 764 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 765 AE_BARRIER(sc); 766 767 /* Set a watchdog timer in case the chip flakes out. */ 768 ifp->if_timer = 5; 769 } 770 } 771 772 /* 773 * ae_watchdog: [ifnet interface function] 774 * 775 * Watchdog timer handler. 776 */ 777 static void 778 ae_watchdog(struct ifnet *ifp) 779 { 780 struct ae_softc *sc = ifp->if_softc; 781 int doing_transmit; 782 783 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 784 785 if (doing_transmit) { 786 printf("%s: transmit timeout\n", device_xname(sc->sc_dev)); 787 if_statinc(ifp, if_oerrors); 788 } 789 else 790 printf("%s: spurious watchdog timeout\n", device_xname(sc->sc_dev)); 791 792 (void) ae_init(ifp); 793 794 /* Try to get more packets going. */ 795 ae_start(ifp); 796 } 797 798 /* If the interface is up and running, only modify the receive 799 * filter when changing to/from promiscuous mode. Otherwise return 800 * ENETRESET so that ether_ioctl will reset the chip. 801 */ 802 static int 803 ae_ifflags_cb(struct ethercom *ec) 804 { 805 struct ifnet *ifp = &ec->ec_if; 806 struct ae_softc *sc = ifp->if_softc; 807 u_short change = ifp->if_flags ^ sc->sc_if_flags; 808 809 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 810 return ENETRESET; 811 else if ((change & IFF_PROMISC) != 0) 812 ae_filter_setup(sc); 813 return 0; 814 } 815 816 /* 817 * ae_ioctl: [ifnet interface function] 818 * 819 * Handle control requests from the operator. 820 */ 821 static int 822 ae_ioctl(struct ifnet *ifp, u_long cmd, void *data) 823 { 824 struct ae_softc *sc = ifp->if_softc; 825 int s, error; 826 827 s = splnet(); 828 829 error = ether_ioctl(ifp, cmd, data); 830 if (error == ENETRESET) { 831 if (ifp->if_flags & IFF_RUNNING) { 832 /* 833 * Multicast list has changed. Set the 834 * hardware filter accordingly. 835 */ 836 ae_filter_setup(sc); 837 } 838 error = 0; 839 } 840 841 /* Try to get more packets going. */ 842 if (AE_IS_ENABLED(sc)) 843 ae_start(ifp); 844 845 sc->sc_if_flags = ifp->if_flags; 846 splx(s); 847 return (error); 848 } 849 850 /* 851 * ae_intr: 852 * 853 * Interrupt service routine. 854 */ 855 int 856 ae_intr(void *arg) 857 { 858 struct ae_softc *sc = arg; 859 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 860 uint32_t status, rxstatus, txstatus; 861 int handled = 0, txthresh; 862 863 DPRINTF(sc, ("%s: ae_intr\n", device_xname(sc->sc_dev))); 864 865 #ifdef DEBUG 866 if (AE_IS_ENABLED(sc) == 0) 867 panic("%s: ae_intr: not enabled", device_xname(sc->sc_dev)); 868 #endif 869 870 /* 871 * If the interface isn't running, the interrupt couldn't 872 * possibly have come from us. 873 */ 874 if ((ifp->if_flags & IFF_RUNNING) == 0 || 875 !device_is_active(sc->sc_dev)) { 876 printf("spurious?!?\n"); 877 return (0); 878 } 879 880 for (;;) { 881 status = AE_READ(sc, CSR_STATUS); 882 if (status) { 883 AE_WRITE(sc, CSR_STATUS, status); 884 AE_BARRIER(sc); 885 } 886 887 if ((status & sc->sc_inten) == 0) 888 break; 889 890 handled = 1; 891 892 rxstatus = status & sc->sc_rxint_mask; 893 txstatus = status & sc->sc_txint_mask; 894 895 if (rxstatus) { 896 /* Grab new any new packets. */ 897 ae_rxintr(sc); 898 899 if (rxstatus & STATUS_RU) { 900 printf("%s: receive ring overrun\n", 901 device_xname(sc->sc_dev)); 902 /* Get the receive process going again. */ 903 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 904 AE_BARRIER(sc); 905 break; 906 } 907 } 908 909 if (txstatus) { 910 /* Sweep up transmit descriptors. */ 911 ae_txintr(sc); 912 913 if (txstatus & STATUS_TJT) 914 printf("%s: transmit jabber timeout\n", 915 device_xname(sc->sc_dev)); 916 917 if (txstatus & STATUS_UNF) { 918 /* 919 * Increase our transmit threshold if 920 * another is available. 921 */ 922 txthresh = sc->sc_txthresh + 1; 923 if (ae_txthresh[txthresh].txth_name != NULL) { 924 uint32_t opmode; 925 /* Idle the transmit process. */ 926 opmode = AE_READ(sc, CSR_OPMODE); 927 ae_idle(sc, OPMODE_ST); 928 929 sc->sc_txthresh = txthresh; 930 opmode &= ~(OPMODE_TR | OPMODE_SF); 931 opmode |= 932 ae_txthresh[txthresh].txth_opmode; 933 printf("%s: transmit underrun; new " 934 "threshold: %s\n", 935 device_xname(sc->sc_dev), 936 ae_txthresh[txthresh].txth_name); 937 938 /* 939 * Set the new threshold and restart 940 * the transmit process. 941 */ 942 AE_WRITE(sc, CSR_OPMODE, opmode); 943 AE_BARRIER(sc); 944 } 945 /* 946 * XXX Log every Nth underrun from 947 * XXX now on? 948 */ 949 } 950 } 951 952 if (status & (STATUS_TPS | STATUS_RPS)) { 953 if (status & STATUS_TPS) 954 printf("%s: transmit process stopped\n", 955 device_xname(sc->sc_dev)); 956 if (status & STATUS_RPS) 957 printf("%s: receive process stopped\n", 958 device_xname(sc->sc_dev)); 959 (void) ae_init(ifp); 960 break; 961 } 962 963 if (status & STATUS_SE) { 964 const char *str; 965 966 if (status & STATUS_TX_ABORT) 967 str = "tx abort"; 968 else if (status & STATUS_RX_ABORT) 969 str = "rx abort"; 970 else 971 str = "unknown error"; 972 973 printf("%s: fatal system error: %s\n", 974 device_xname(sc->sc_dev), str); 975 (void) ae_init(ifp); 976 break; 977 } 978 979 /* 980 * Not handled: 981 * 982 * Transmit buffer unavailable -- normal 983 * condition, nothing to do, really. 984 * 985 * General purpose timer experied -- we don't 986 * use the general purpose timer. 987 * 988 * Early receive interrupt -- not available on 989 * all chips, we just use RI. We also only 990 * use single-segment receive DMA, so this 991 * is mostly useless. 992 */ 993 } 994 995 /* Try to get more packets going. */ 996 if_schedule_deferred_start(ifp); 997 998 if (handled) 999 rnd_add_uint32(&sc->sc_rnd_source, status); 1000 return (handled); 1001 } 1002 1003 /* 1004 * ae_rxintr: 1005 * 1006 * Helper; handle receive interrupts. 1007 */ 1008 static void 1009 ae_rxintr(struct ae_softc *sc) 1010 { 1011 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1012 struct ae_rxsoft *rxs; 1013 struct mbuf *m; 1014 uint32_t rxstat; 1015 int i, len; 1016 1017 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1018 rxs = &sc->sc_rxsoft[i]; 1019 1020 AE_CDRXSYNC(sc, i, 1021 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1022 1023 rxstat = sc->sc_rxdescs[i].ad_status; 1024 1025 if (rxstat & ADSTAT_OWN) { 1026 /* 1027 * We have processed all of the receive buffers. 1028 */ 1029 break; 1030 } 1031 1032 /* 1033 * If any collisions were seen on the wire, count one. 1034 */ 1035 if (rxstat & ADSTAT_Rx_CS) 1036 if_statinc(ifp, if_collisions); 1037 1038 /* 1039 * If an error occurred, update stats, clear the status 1040 * word, and leave the packet buffer in place. It will 1041 * simply be reused the next time the ring comes around. 1042 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1043 * error. 1044 */ 1045 if (rxstat & ADSTAT_ES && 1046 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1047 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1048 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1049 #define PRINTERR(bit, str) \ 1050 if (rxstat & (bit)) \ 1051 printf("%s: receive error: %s\n", \ 1052 device_xname(sc->sc_dev), str) 1053 if_statinc(ifp, if_ierrors); 1054 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1055 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1056 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1057 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1058 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1059 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1060 #undef PRINTERR 1061 AE_INIT_RXDESC(sc, i); 1062 continue; 1063 } 1064 1065 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1066 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1067 1068 /* 1069 * No errors; receive the packet. Note the chip 1070 * includes the CRC with every packet. 1071 */ 1072 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1073 1074 /* 1075 * XXX: the Atheros part can align on half words. what 1076 * is the performance implication of this? Probably 1077 * minimal, and we should use it... 1078 */ 1079 #ifdef __NO_STRICT_ALIGNMENT 1080 /* 1081 * Allocate a new mbuf cluster. If that fails, we are 1082 * out of memory, and must drop the packet and recycle 1083 * the buffer that's already attached to this descriptor. 1084 */ 1085 m = rxs->rxs_mbuf; 1086 if (ae_add_rxbuf(sc, i) != 0) { 1087 if_statinc(ifp, if_ierrors); 1088 AE_INIT_RXDESC(sc, i); 1089 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1090 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1091 continue; 1092 } 1093 #else 1094 /* 1095 * The chip's receive buffers must be 4-byte aligned. 1096 * But this means that the data after the Ethernet header 1097 * is misaligned. We must allocate a new buffer and 1098 * copy the data, shifted forward 2 bytes. 1099 */ 1100 MGETHDR(m, M_DONTWAIT, MT_DATA); 1101 if (m == NULL) { 1102 dropit: 1103 if_statinc(ifp, if_ierrors); 1104 AE_INIT_RXDESC(sc, i); 1105 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1106 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1107 continue; 1108 } 1109 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1110 if (len > (MHLEN - 2)) { 1111 MCLGET(m, M_DONTWAIT); 1112 if ((m->m_flags & M_EXT) == 0) { 1113 m_freem(m); 1114 goto dropit; 1115 } 1116 } 1117 m->m_data += 2; 1118 1119 /* 1120 * Note that we use clusters for incoming frames, so the 1121 * buffer is virtually contiguous. 1122 */ 1123 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 1124 1125 /* Allow the receive descriptor to continue using its mbuf. */ 1126 AE_INIT_RXDESC(sc, i); 1127 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1128 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1129 #endif /* __NO_STRICT_ALIGNMENT */ 1130 1131 m_set_rcvif(m, ifp); 1132 m->m_pkthdr.len = m->m_len = len; 1133 1134 /* Pass it on. */ 1135 if_percpuq_enqueue(ifp->if_percpuq, m); 1136 } 1137 1138 /* Update the receive pointer. */ 1139 sc->sc_rxptr = i; 1140 } 1141 1142 /* 1143 * ae_txintr: 1144 * 1145 * Helper; handle transmit interrupts. 1146 */ 1147 static void 1148 ae_txintr(struct ae_softc *sc) 1149 { 1150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1151 struct ae_txsoft *txs; 1152 uint32_t txstat; 1153 1154 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1155 device_xname(sc->sc_dev), sc->sc_flags)); 1156 1157 ifp->if_flags &= ~IFF_OACTIVE; 1158 1159 /* 1160 * Go through our Tx list and free mbufs for those 1161 * frames that have been transmitted. 1162 */ 1163 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1164 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1165 txs->txs_ndescs, 1166 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1167 1168 #ifdef AE_DEBUG 1169 if (ifp->if_flags & IFF_DEBUG) { 1170 int i; 1171 printf(" txsoft %p transmit chain:\n", txs); 1172 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1173 printf(" descriptor %d:\n", i); 1174 printf(" ad_status: 0x%08x\n", 1175 sc->sc_txdescs[i].ad_status); 1176 printf(" ad_ctl: 0x%08x\n", 1177 sc->sc_txdescs[i].ad_ctl); 1178 printf(" ad_bufaddr1: 0x%08x\n", 1179 sc->sc_txdescs[i].ad_bufaddr1); 1180 printf(" ad_bufaddr2: 0x%08x\n", 1181 sc->sc_txdescs[i].ad_bufaddr2); 1182 if (i == txs->txs_lastdesc) 1183 break; 1184 } 1185 } 1186 #endif 1187 1188 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1189 if (txstat & ADSTAT_OWN) 1190 break; 1191 1192 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1193 1194 sc->sc_txfree += txs->txs_ndescs; 1195 1196 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1197 0, txs->txs_dmamap->dm_mapsize, 1198 BUS_DMASYNC_POSTWRITE); 1199 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1200 m_freem(txs->txs_mbuf); 1201 txs->txs_mbuf = NULL; 1202 1203 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1204 1205 /* 1206 * Check for errors and collisions. 1207 */ 1208 #ifdef AE_STATS 1209 if (txstat & ADSTAT_Tx_UF) 1210 sc->sc_stats.ts_tx_uf++; 1211 if (txstat & ADSTAT_Tx_TO) 1212 sc->sc_stats.ts_tx_to++; 1213 if (txstat & ADSTAT_Tx_EC) 1214 sc->sc_stats.ts_tx_ec++; 1215 if (txstat & ADSTAT_Tx_LC) 1216 sc->sc_stats.ts_tx_lc++; 1217 #endif 1218 1219 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1220 if (txstat & (ADSTAT_Tx_UF | ADSTAT_Tx_TO)) 1221 if_statinc_ref(nsr, if_oerrors); 1222 1223 if (txstat & ADSTAT_Tx_EC) 1224 if_statadd_ref(nsr, if_collisions, 16); 1225 else if (ADSTAT_Tx_COLLISIONS(txstat)) 1226 if_statadd_ref(nsr, if_collisions, 1227 ADSTAT_Tx_COLLISIONS(txstat)); 1228 if (txstat & ADSTAT_Tx_LC) 1229 if_statinc_ref(nsr, if_collisions); 1230 1231 if_statinc_ref(nsr, if_opackets); 1232 IF_STAT_PUTREF(ifp); 1233 } 1234 1235 /* 1236 * If there are no more pending transmissions, cancel the watchdog 1237 * timer. 1238 */ 1239 if (txs == NULL) 1240 ifp->if_timer = 0; 1241 } 1242 1243 #ifdef AE_STATS 1244 void 1245 ae_print_stats(struct ae_softc *sc) 1246 { 1247 1248 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1249 device_xname(sc->sc_dev), 1250 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1251 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1252 } 1253 #endif 1254 1255 /* 1256 * ae_reset: 1257 * 1258 * Perform a soft reset on the chip. 1259 */ 1260 void 1261 ae_reset(struct ae_softc *sc) 1262 { 1263 int i; 1264 1265 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1266 AE_BARRIER(sc); 1267 1268 /* 1269 * The chip doesn't take itself out of reset automatically. 1270 * We need to do so after 2us. 1271 */ 1272 delay(10); 1273 AE_WRITE(sc, CSR_BUSMODE, 0); 1274 AE_BARRIER(sc); 1275 1276 for (i = 0; i < 1000; i++) { 1277 /* 1278 * Wait a bit for the reset to complete before peeking 1279 * at the chip again. 1280 */ 1281 delay(10); 1282 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1283 break; 1284 } 1285 1286 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1287 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 1288 1289 delay(1000); 1290 } 1291 1292 /* 1293 * ae_init: [ ifnet interface function ] 1294 * 1295 * Initialize the interface. Must be called at splnet(). 1296 */ 1297 static int 1298 ae_init(struct ifnet *ifp) 1299 { 1300 struct ae_softc *sc = ifp->if_softc; 1301 struct ae_txsoft *txs; 1302 struct ae_rxsoft *rxs; 1303 const uint8_t *enaddr; 1304 int i, error = 0; 1305 1306 if ((error = ae_enable(sc)) != 0) 1307 goto out; 1308 1309 /* 1310 * Cancel any pending I/O. 1311 */ 1312 ae_stop(ifp, 0); 1313 1314 /* 1315 * Reset the chip to a known state. 1316 */ 1317 ae_reset(sc); 1318 1319 /* 1320 * Initialize the BUSMODE register. 1321 */ 1322 AE_WRITE(sc, CSR_BUSMODE, 1323 /* XXX: not sure if this is a good thing or not... */ 1324 //BUSMODE_ALIGN_16B | 1325 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1326 AE_BARRIER(sc); 1327 1328 /* 1329 * Initialize the transmit descriptor ring. 1330 */ 1331 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1332 for (i = 0; i < AE_NTXDESC; i++) { 1333 sc->sc_txdescs[i].ad_ctl = 0; 1334 sc->sc_txdescs[i].ad_bufaddr2 = 1335 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1336 } 1337 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1338 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1339 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1340 sc->sc_txfree = AE_NTXDESC; 1341 sc->sc_txnext = 0; 1342 1343 /* 1344 * Initialize the transmit job descriptors. 1345 */ 1346 SIMPLEQ_INIT(&sc->sc_txfreeq); 1347 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1348 for (i = 0; i < AE_TXQUEUELEN; i++) { 1349 txs = &sc->sc_txsoft[i]; 1350 txs->txs_mbuf = NULL; 1351 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1352 } 1353 1354 /* 1355 * Initialize the receive descriptor and receive job 1356 * descriptor rings. 1357 */ 1358 for (i = 0; i < AE_NRXDESC; i++) { 1359 rxs = &sc->sc_rxsoft[i]; 1360 if (rxs->rxs_mbuf == NULL) { 1361 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1362 printf("%s: unable to allocate or map rx " 1363 "buffer %d, error = %d\n", 1364 device_xname(sc->sc_dev), i, error); 1365 /* 1366 * XXX Should attempt to run with fewer receive 1367 * XXX buffers instead of just failing. 1368 */ 1369 ae_rxdrain(sc); 1370 goto out; 1371 } 1372 } else 1373 AE_INIT_RXDESC(sc, i); 1374 } 1375 sc->sc_rxptr = 0; 1376 1377 /* 1378 * Initialize the interrupt mask and enable interrupts. 1379 */ 1380 /* normal interrupts */ 1381 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1382 1383 /* abnormal interrupts */ 1384 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1385 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1386 1387 sc->sc_rxint_mask = STATUS_RI | STATUS_RU; 1388 sc->sc_txint_mask = STATUS_TI | STATUS_UNF | STATUS_TJT; 1389 1390 sc->sc_rxint_mask &= sc->sc_inten; 1391 sc->sc_txint_mask &= sc->sc_inten; 1392 1393 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1394 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1395 1396 /* 1397 * Give the transmit and receive rings to the chip. 1398 */ 1399 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1400 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1401 AE_BARRIER(sc); 1402 1403 /* 1404 * Set the station address. 1405 */ 1406 enaddr = CLLADDR(ifp->if_sadl); 1407 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1408 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1409 enaddr[1] << 8 | enaddr[0]); 1410 AE_BARRIER(sc); 1411 1412 /* 1413 * Set the receive filter. This will start the transmit and 1414 * receive processes. 1415 */ 1416 ae_filter_setup(sc); 1417 1418 /* 1419 * Set the current media. 1420 */ 1421 if ((error = ether_mediachange(ifp)) != 0) 1422 goto out; 1423 1424 /* 1425 * Start the mac. 1426 */ 1427 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1428 AE_BARRIER(sc); 1429 1430 /* 1431 * Write out the opmode. 1432 */ 1433 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1434 ae_txthresh[sc->sc_txthresh].txth_opmode); 1435 /* 1436 * Start the receive process. 1437 */ 1438 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1439 AE_BARRIER(sc); 1440 1441 if (sc->sc_tick != NULL) { 1442 /* Start the one second clock. */ 1443 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1444 } 1445 1446 /* 1447 * Note that the interface is now running. 1448 */ 1449 ifp->if_flags |= IFF_RUNNING; 1450 ifp->if_flags &= ~IFF_OACTIVE; 1451 sc->sc_if_flags = ifp->if_flags; 1452 1453 out: 1454 if (error) { 1455 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1456 ifp->if_timer = 0; 1457 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1458 } 1459 return (error); 1460 } 1461 1462 /* 1463 * ae_enable: 1464 * 1465 * Enable the chip. 1466 */ 1467 static int 1468 ae_enable(struct ae_softc *sc) 1469 { 1470 1471 if (AE_IS_ENABLED(sc) == 0) { 1472 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1473 ae_intr, sc); 1474 if (sc->sc_ih == NULL) { 1475 printf("%s: unable to establish interrupt\n", 1476 device_xname(sc->sc_dev)); 1477 return (EIO); 1478 } 1479 sc->sc_flags |= AE_ENABLED; 1480 } 1481 return (0); 1482 } 1483 1484 /* 1485 * ae_disable: 1486 * 1487 * Disable the chip. 1488 */ 1489 static void 1490 ae_disable(struct ae_softc *sc) 1491 { 1492 1493 if (AE_IS_ENABLED(sc)) { 1494 arbus_intr_disestablish(sc->sc_ih); 1495 sc->sc_flags &= ~AE_ENABLED; 1496 } 1497 } 1498 1499 /* 1500 * ae_power: 1501 * 1502 * Power management (suspend/resume) hook. 1503 */ 1504 static void 1505 ae_power(int why, void *arg) 1506 { 1507 struct ae_softc *sc = arg; 1508 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1509 int s; 1510 1511 printf("power called: %d, %x\n", why, (uint32_t)arg); 1512 s = splnet(); 1513 switch (why) { 1514 case PWR_STANDBY: 1515 /* do nothing! */ 1516 break; 1517 case PWR_SUSPEND: 1518 ae_stop(ifp, 0); 1519 ae_disable(sc); 1520 break; 1521 case PWR_RESUME: 1522 if (ifp->if_flags & IFF_UP) { 1523 ae_enable(sc); 1524 ae_init(ifp); 1525 } 1526 break; 1527 case PWR_SOFTSUSPEND: 1528 case PWR_SOFTSTANDBY: 1529 case PWR_SOFTRESUME: 1530 break; 1531 } 1532 splx(s); 1533 } 1534 1535 /* 1536 * ae_rxdrain: 1537 * 1538 * Drain the receive queue. 1539 */ 1540 static void 1541 ae_rxdrain(struct ae_softc *sc) 1542 { 1543 struct ae_rxsoft *rxs; 1544 int i; 1545 1546 for (i = 0; i < AE_NRXDESC; i++) { 1547 rxs = &sc->sc_rxsoft[i]; 1548 if (rxs->rxs_mbuf != NULL) { 1549 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1550 m_freem(rxs->rxs_mbuf); 1551 rxs->rxs_mbuf = NULL; 1552 } 1553 } 1554 } 1555 1556 /* 1557 * ae_stop: [ ifnet interface function ] 1558 * 1559 * Stop transmission on the interface. 1560 */ 1561 static void 1562 ae_stop(struct ifnet *ifp, int disable) 1563 { 1564 struct ae_softc *sc = ifp->if_softc; 1565 struct ae_txsoft *txs; 1566 1567 if (sc->sc_tick != NULL) { 1568 /* Stop the one second clock. */ 1569 callout_stop(&sc->sc_tick_callout); 1570 } 1571 1572 /* Down the MII. */ 1573 mii_down(&sc->sc_mii); 1574 1575 /* Disable interrupts. */ 1576 AE_WRITE(sc, CSR_INTEN, 0); 1577 1578 /* Stop the transmit and receive processes. */ 1579 AE_WRITE(sc, CSR_OPMODE, 0); 1580 AE_WRITE(sc, CSR_RXLIST, 0); 1581 AE_WRITE(sc, CSR_TXLIST, 0); 1582 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1583 AE_BARRIER(sc); 1584 1585 /* 1586 * Release any queued transmit buffers. 1587 */ 1588 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1589 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1590 if (txs->txs_mbuf != NULL) { 1591 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1592 m_freem(txs->txs_mbuf); 1593 txs->txs_mbuf = NULL; 1594 } 1595 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1596 } 1597 1598 /* 1599 * Mark the interface down and cancel the watchdog timer. 1600 */ 1601 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1602 sc->sc_if_flags = ifp->if_flags; 1603 ifp->if_timer = 0; 1604 1605 if (disable) { 1606 ae_rxdrain(sc); 1607 ae_disable(sc); 1608 } 1609 1610 /* 1611 * Reset the chip (needed on some flavors to actually disable it). 1612 */ 1613 ae_reset(sc); 1614 } 1615 1616 /* 1617 * ae_add_rxbuf: 1618 * 1619 * Add a receive buffer to the indicated descriptor. 1620 */ 1621 static int 1622 ae_add_rxbuf(struct ae_softc *sc, int idx) 1623 { 1624 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1625 struct mbuf *m; 1626 int error; 1627 1628 MGETHDR(m, M_DONTWAIT, MT_DATA); 1629 if (m == NULL) 1630 return (ENOBUFS); 1631 1632 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1633 MCLGET(m, M_DONTWAIT); 1634 if ((m->m_flags & M_EXT) == 0) { 1635 m_freem(m); 1636 return (ENOBUFS); 1637 } 1638 1639 if (rxs->rxs_mbuf != NULL) 1640 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1641 1642 rxs->rxs_mbuf = m; 1643 1644 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1645 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1646 BUS_DMA_READ | BUS_DMA_NOWAIT); 1647 if (error) { 1648 printf("%s: can't load rx DMA map %d, error = %d\n", 1649 device_xname(sc->sc_dev), idx, error); 1650 panic("ae_add_rxbuf"); /* XXX */ 1651 } 1652 1653 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1654 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1655 1656 AE_INIT_RXDESC(sc, idx); 1657 1658 return (0); 1659 } 1660 1661 /* 1662 * ae_filter_setup: 1663 * 1664 * Set the chip's receive filter. 1665 */ 1666 static void 1667 ae_filter_setup(struct ae_softc *sc) 1668 { 1669 struct ethercom *ec = &sc->sc_ethercom; 1670 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1671 struct ether_multi *enm; 1672 struct ether_multistep step; 1673 uint32_t hash, mchash[2]; 1674 uint32_t macctl = 0; 1675 1676 /* 1677 * If the chip is running, we need to reset the interface, 1678 * and will revisit here (with IFF_RUNNING) clear. The 1679 * chip seems to really not like to have its multicast 1680 * filter programmed without a reset. 1681 */ 1682 if (ifp->if_flags & IFF_RUNNING) { 1683 (void) ae_init(ifp); 1684 return; 1685 } 1686 1687 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1688 device_xname(sc->sc_dev), sc->sc_flags)); 1689 1690 macctl = AE_READ(sc, CSR_MACCTL); 1691 macctl &= ~(MACCTL_PR | MACCTL_PM); 1692 macctl |= MACCTL_HASH; 1693 macctl |= MACCTL_HBD; 1694 macctl |= MACCTL_PR; 1695 1696 if (ifp->if_flags & IFF_PROMISC) { 1697 macctl |= MACCTL_PR; 1698 goto allmulti; 1699 } 1700 1701 mchash[0] = mchash[1] = 0; 1702 1703 ETHER_LOCK(ec); 1704 ETHER_FIRST_MULTI(step, ec, enm); 1705 while (enm != NULL) { 1706 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1707 /* 1708 * We must listen to a range of multicast addresses. 1709 * For now, just accept all multicasts, rather than 1710 * trying to set only those filter bits needed to match 1711 * the range. (At this time, the only use of address 1712 * ranges is for IP multicast routing, for which the 1713 * range is big enough to require all bits set.) 1714 */ 1715 ETHER_UNLOCK(ec); 1716 goto allmulti; 1717 } 1718 1719 /* Verify whether we use big or little endian hashes */ 1720 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1721 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1722 ETHER_NEXT_MULTI(step, enm); 1723 } 1724 ETHER_UNLOCK(ec); 1725 ifp->if_flags &= ~IFF_ALLMULTI; 1726 goto setit; 1727 1728 allmulti: 1729 ifp->if_flags |= IFF_ALLMULTI; 1730 mchash[0] = mchash[1] = 0xffffffff; 1731 macctl |= MACCTL_PM; 1732 1733 setit: 1734 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1735 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1736 1737 AE_WRITE(sc, CSR_MACCTL, macctl); 1738 AE_BARRIER(sc); 1739 1740 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1741 device_xname(sc->sc_dev), macctl)); 1742 } 1743 1744 /* 1745 * ae_idle: 1746 * 1747 * Cause the transmit and/or receive processes to go idle. 1748 */ 1749 void 1750 ae_idle(struct ae_softc *sc, uint32_t bits) 1751 { 1752 static const char * const txstate_names[] = { 1753 "STOPPED", 1754 "RUNNING - FETCH", 1755 "RUNNING - WAIT", 1756 "RUNNING - READING", 1757 "-- RESERVED --", 1758 "RUNNING - SETUP", 1759 "SUSPENDED", 1760 "RUNNING - CLOSE", 1761 }; 1762 static const char * const rxstate_names[] = { 1763 "STOPPED", 1764 "RUNNING - FETCH", 1765 "RUNNING - CHECK", 1766 "RUNNING - WAIT", 1767 "SUSPENDED", 1768 "RUNNING - CLOSE", 1769 "RUNNING - FLUSH", 1770 "RUNNING - QUEUE", 1771 }; 1772 1773 uint32_t csr, ackmask = 0; 1774 int i; 1775 1776 if (bits & OPMODE_ST) 1777 ackmask |= STATUS_TPS; 1778 1779 if (bits & OPMODE_SR) 1780 ackmask |= STATUS_RPS; 1781 1782 AE_CLR(sc, CSR_OPMODE, bits); 1783 1784 for (i = 0; i < 1000; i++) { 1785 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1786 break; 1787 delay(10); 1788 } 1789 1790 csr = AE_READ(sc, CSR_STATUS); 1791 if ((csr & ackmask) != ackmask) { 1792 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1793 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1794 printf("%s: transmit process failed to idle: " 1795 "state %s\n", device_xname(sc->sc_dev), 1796 txstate_names[(csr & STATUS_TS) >> 20]); 1797 } 1798 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1799 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1800 printf("%s: receive process failed to idle: " 1801 "state %s\n", device_xname(sc->sc_dev), 1802 rxstate_names[(csr & STATUS_RS) >> 17]); 1803 } 1804 } 1805 } 1806 1807 /***************************************************************************** 1808 * Support functions for MII-attached media. 1809 *****************************************************************************/ 1810 1811 /* 1812 * ae_mii_tick: 1813 * 1814 * One second timer, used to tick the MII. 1815 */ 1816 static void 1817 ae_mii_tick(void *arg) 1818 { 1819 struct ae_softc *sc = arg; 1820 int s; 1821 1822 if (!device_is_active(sc->sc_dev)) 1823 return; 1824 1825 s = splnet(); 1826 mii_tick(&sc->sc_mii); 1827 splx(s); 1828 1829 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1830 } 1831 1832 /* 1833 * ae_mii_statchg: [mii interface function] 1834 * 1835 * Callback from PHY when media changes. 1836 */ 1837 static void 1838 ae_mii_statchg(struct ifnet *ifp) 1839 { 1840 struct ae_softc *sc = ifp->if_softc; 1841 uint32_t macctl, flowc; 1842 1843 //opmode = AE_READ(sc, CSR_OPMODE); 1844 macctl = AE_READ(sc, CSR_MACCTL); 1845 1846 /* XXX: do we need to do this? */ 1847 /* Idle the transmit and receive processes. */ 1848 //ae_idle(sc, OPMODE_ST | OPMODE_SR); 1849 1850 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1851 flowc = FLOWC_FCE; 1852 macctl &= ~MACCTL_DRO; 1853 macctl |= MACCTL_FDX; 1854 } else { 1855 flowc = 0; /* cannot do flow control in HDX */ 1856 macctl |= MACCTL_DRO; 1857 macctl &= ~MACCTL_FDX; 1858 } 1859 1860 AE_WRITE(sc, CSR_FLOWC, flowc); 1861 AE_WRITE(sc, CSR_MACCTL, macctl); 1862 1863 /* restore operational mode */ 1864 //AE_WRITE(sc, CSR_OPMODE, opmode); 1865 AE_BARRIER(sc); 1866 } 1867 1868 /* 1869 * ae_mii_readreg: 1870 * 1871 * Read a PHY register. 1872 */ 1873 static int 1874 ae_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1875 { 1876 struct ae_softc *sc = device_private(self); 1877 uint32_t addr; 1878 int i; 1879 1880 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1881 AE_WRITE(sc, CSR_MIIADDR, addr); 1882 AE_BARRIER(sc); 1883 for (i = 0; i < 100000000; i++) { 1884 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1885 break; 1886 } 1887 1888 if (i >= 100000000) 1889 return ETIMEDOUT; 1890 1891 *val = AE_READ(sc, CSR_MIIDATA) & 0xffff; 1892 return 0; 1893 } 1894 1895 /* 1896 * ae_mii_writereg: 1897 * 1898 * Write a PHY register. 1899 */ 1900 static int 1901 ae_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1902 { 1903 struct ae_softc *sc = device_private(self); 1904 uint32_t addr; 1905 int i; 1906 1907 /* write the data register */ 1908 AE_WRITE(sc, CSR_MIIDATA, val); 1909 1910 /* write the address to latch it in */ 1911 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1912 MIIADDR_WRITE; 1913 AE_WRITE(sc, CSR_MIIADDR, addr); 1914 AE_BARRIER(sc); 1915 1916 for (i = 0; i < 100000000; i++) { 1917 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1918 break; 1919 } 1920 1921 if (i >= 100000000) 1922 return ETIMEDOUT; 1923 1924 return 0; 1925 } 1926
Indexes created Thu Oct 02 14:10:14 GMT 2025