if_ae.c revision 1.41
1 /* $NetBSD: if_ae.c,v 1.41 2022/09/18 11:30:40 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the onboard ethernet MAC found on the AR5312 74 * chip's AHB bus. 75 * 76 * This device is very simliar to the tulip in most regards, and 77 * the code is directly derived from NetBSD's tulip.c. However, it 78 * is different enough that it did not seem to be a good idea to 79 * add further complexity to the tulip driver, so we have our own. 80 * 81 * Also tulip has a lot of complexity in it for various parts/options 82 * that we don't need, and on these little boxes with only ~8MB RAM, we 83 * don't want any extra bloat. 84 */ 85 86 /* 87 * TODO: 88 * 89 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 90 * inbound packets on a half-word boundary, which would make life easier 91 * for TCP/IP. (Aligning IP headers on a word.) 92 * 93 * 2) There is stuff in original tulip to shut down the device when reacting 94 * to a change in link status. Is that needed. 95 * 96 * 3) Test with variety of 10/100 HDX/FDX scenarios. 97 * 98 */ 99 100 #include <sys/cdefs.h> 101 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.41 2022/09/18 11:30:40 thorpej Exp $"); 102 103 104 #include <sys/param.h> 105 #include <sys/bus.h> 106 #include <sys/callout.h> 107 #include <sys/device.h> 108 #include <sys/endian.h> 109 #include <sys/errno.h> 110 #include <sys/intr.h> 111 #include <sys/ioctl.h> 112 #include <sys/kernel.h> 113 #include <sys/malloc.h> 114 #include <sys/mbuf.h> 115 #include <sys/socket.h> 116 117 #include <uvm/uvm_extern.h> 118 119 #include <net/if.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/if_ether.h> 123 124 #include <net/bpf.h> 125 126 #include <dev/mii/mii.h> 127 #include <dev/mii/miivar.h> 128 #include <dev/mii/mii_bitbang.h> 129 130 #include <mips/atheros/include/arbusvar.h> 131 #include <mips/atheros/dev/aereg.h> 132 #include <mips/atheros/dev/aevar.h> 133 134 static const struct { 135 uint32_t txth_opmode; /* OPMODE bits */ 136 const char *txth_name; /* name of mode */ 137 } ae_txthresh[] = { 138 { OPMODE_TR_32, "32 words" }, 139 { OPMODE_TR_64, "64 words" }, 140 { OPMODE_TR_128, "128 words" }, 141 { OPMODE_TR_256, "256 words" }, 142 { OPMODE_SF, "store and forward mode" }, 143 { 0, NULL }, 144 }; 145 146 static int ae_match(device_t, struct cfdata *, void *); 147 static void ae_attach(device_t, device_t, void *); 148 static int ae_detach(device_t, int); 149 static int ae_activate(device_t, enum devact); 150 151 static int ae_ifflags_cb(struct ethercom *); 152 static void ae_reset(struct ae_softc *); 153 static void ae_idle(struct ae_softc *, uint32_t); 154 155 static void ae_start(struct ifnet *); 156 static void ae_watchdog(struct ifnet *); 157 static int ae_ioctl(struct ifnet *, u_long, void *); 158 static int ae_init(struct ifnet *); 159 static void ae_stop(struct ifnet *, int); 160 161 static void ae_shutdown(void *); 162 163 static void ae_rxdrain(struct ae_softc *); 164 static int ae_add_rxbuf(struct ae_softc *, int); 165 166 static int ae_enable(struct ae_softc *); 167 static void ae_disable(struct ae_softc *); 168 static void ae_power(int, void *); 169 170 static void ae_filter_setup(struct ae_softc *); 171 172 static int ae_intr(void *); 173 static void ae_rxintr(struct ae_softc *); 174 static void ae_txintr(struct ae_softc *); 175 176 static void ae_mii_tick(void *); 177 static void ae_mii_statchg(struct ifnet *); 178 179 static int ae_mii_readreg(device_t, int, int, uint16_t *); 180 static int ae_mii_writereg(device_t, int, int, uint16_t); 181 182 #ifdef AE_DEBUG 183 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 184 printf x 185 #else 186 #define DPRINTF(sc, x) /* nothing */ 187 #endif 188 189 #ifdef AE_STATS 190 static void ae_print_stats(struct ae_softc *); 191 #endif 192 193 CFATTACH_DECL_NEW(ae, sizeof(struct ae_softc), 194 ae_match, ae_attach, ae_detach, ae_activate); 195 196 /* 197 * ae_match: 198 * 199 * Check for a device match. 200 */ 201 int 202 ae_match(device_t parent, struct cfdata *cf, void *aux) 203 { 204 struct arbus_attach_args *aa = aux; 205 206 if (strcmp(aa->aa_name, cf->cf_name) == 0) 207 return 1; 208 209 return 0; 210 211 } 212 213 /* 214 * ae_attach: 215 * 216 * Attach an ae interface to the system. 217 */ 218 void 219 ae_attach(device_t parent, device_t self, void *aux) 220 { 221 const uint8_t *enaddr; 222 prop_data_t ea; 223 struct ae_softc *sc = device_private(self); 224 struct arbus_attach_args *aa = aux; 225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 226 struct mii_data * const mii = &sc->sc_mii; 227 int i, error; 228 229 sc->sc_dev = self; 230 231 callout_init(&sc->sc_tick_callout, 0); 232 233 printf(": Atheros AR531X 10/100 Ethernet\n"); 234 235 /* 236 * Try to get MAC address. 237 */ 238 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-address"); 239 if (ea == NULL) { 240 printf("%s: unable to get mac-addr property\n", 241 device_xname(sc->sc_dev)); 242 return; 243 } 244 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 245 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 246 enaddr = prop_data_data_nocopy(ea); 247 248 /* Announce ourselves. */ 249 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 250 ether_sprintf(enaddr)); 251 252 sc->sc_cirq = aa->aa_cirq; 253 sc->sc_mirq = aa->aa_mirq; 254 sc->sc_st = aa->aa_bst; 255 sc->sc_dmat = aa->aa_dmat; 256 257 SIMPLEQ_INIT(&sc->sc_txfreeq); 258 SIMPLEQ_INIT(&sc->sc_txdirtyq); 259 260 /* 261 * Map registers. 262 */ 263 sc->sc_size = aa->aa_size; 264 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 265 &sc->sc_sh)) != 0) { 266 printf("%s: unable to map registers, error = %d\n", 267 device_xname(sc->sc_dev), error); 268 goto fail_0; 269 } 270 271 /* 272 * Allocate the control data structures, and create and load the 273 * DMA map for it. 274 */ 275 if ((error = bus_dmamem_alloc(sc->sc_dmat, 276 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 277 1, &sc->sc_cdnseg, 0)) != 0) { 278 printf("%s: unable to allocate control data, error = %d\n", 279 device_xname(sc->sc_dev), error); 280 goto fail_1; 281 } 282 283 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 284 sizeof(struct ae_control_data), (void **)&sc->sc_control_data, 285 BUS_DMA_COHERENT)) != 0) { 286 printf("%s: unable to map control data, error = %d\n", 287 device_xname(sc->sc_dev), error); 288 goto fail_2; 289 } 290 291 if ((error = bus_dmamap_create(sc->sc_dmat, 292 sizeof(struct ae_control_data), 1, 293 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 294 printf("%s: unable to create control data DMA map, " 295 "error = %d\n", device_xname(sc->sc_dev), error); 296 goto fail_3; 297 } 298 299 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 300 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 301 0)) != 0) { 302 printf("%s: unable to load control data DMA map, error = %d\n", 303 device_xname(sc->sc_dev), error); 304 goto fail_4; 305 } 306 307 /* 308 * Create the transmit buffer DMA maps. 309 */ 310 for (i = 0; i < AE_TXQUEUELEN; i++) { 311 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 312 AE_NTXSEGS, MCLBYTES, 0, 0, 313 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 314 printf("%s: unable to create tx DMA map %d, " 315 "error = %d\n", device_xname(sc->sc_dev), i, error); 316 goto fail_5; 317 } 318 } 319 320 /* 321 * Create the receive buffer DMA maps. 322 */ 323 for (i = 0; i < AE_NRXDESC; i++) { 324 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 325 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 326 printf("%s: unable to create rx DMA map %d, " 327 "error = %d\n", device_xname(sc->sc_dev), i, error); 328 goto fail_6; 329 } 330 sc->sc_rxsoft[i].rxs_mbuf = NULL; 331 } 332 333 /* 334 * Reset the chip to a known state. 335 */ 336 ae_reset(sc); 337 338 /* 339 * From this point forward, the attachment cannot fail. A failure 340 * before this point releases all resources that may have been 341 * allocated. 342 */ 343 sc->sc_flags |= AE_ATTACHED; 344 345 /* 346 * Initialize our media structures. This may probe the MII, if 347 * present. 348 */ 349 mii->mii_ifp = ifp; 350 mii->mii_readreg = ae_mii_readreg; 351 mii->mii_writereg = ae_mii_writereg; 352 mii->mii_statchg = ae_mii_statchg; 353 sc->sc_ethercom.ec_mii = mii; 354 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 355 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 356 MII_OFFSET_ANY, 0); 357 358 if (LIST_FIRST(&mii->mii_phys) == NULL) { 359 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 360 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 361 } else 362 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 363 364 sc->sc_tick = ae_mii_tick; 365 366 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 sc->sc_if_flags = ifp->if_flags; 370 ifp->if_ioctl = ae_ioctl; 371 ifp->if_start = ae_start; 372 ifp->if_watchdog = ae_watchdog; 373 ifp->if_init = ae_init; 374 ifp->if_stop = ae_stop; 375 IFQ_SET_READY(&ifp->if_snd); 376 377 /* 378 * We can support 802.1Q VLAN-sized frames. 379 */ 380 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 381 382 /* 383 * Attach the interface. 384 */ 385 if_attach(ifp); 386 if_deferred_start_init(ifp, NULL); 387 ether_ifattach(ifp, enaddr); 388 ether_set_ifflags_cb(&sc->sc_ethercom, ae_ifflags_cb); 389 390 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 391 RND_TYPE_NET, RND_FLAG_DEFAULT); 392 393 /* 394 * Make sure the interface is shutdown during reboot. 395 */ 396 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 397 if (sc->sc_sdhook == NULL) 398 printf("%s: WARNING: unable to establish shutdown hook\n", 399 device_xname(sc->sc_dev)); 400 401 /* 402 * Add a suspend hook to make sure we come back up after a 403 * resume. 404 */ 405 sc->sc_powerhook = powerhook_establish(device_xname(sc->sc_dev), 406 ae_power, sc); 407 if (sc->sc_powerhook == NULL) 408 printf("%s: WARNING: unable to establish power hook\n", 409 device_xname(sc->sc_dev)); 410 return; 411 412 /* 413 * Free any resources we've allocated during the failed attach 414 * attempt. Do this in reverse order and fall through. 415 */ 416 fail_6: 417 for (i = 0; i < AE_NRXDESC; i++) { 418 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 419 bus_dmamap_destroy(sc->sc_dmat, 420 sc->sc_rxsoft[i].rxs_dmamap); 421 } 422 fail_5: 423 for (i = 0; i < AE_TXQUEUELEN; i++) { 424 if (sc->sc_txsoft[i].txs_dmamap != NULL) 425 bus_dmamap_destroy(sc->sc_dmat, 426 sc->sc_txsoft[i].txs_dmamap); 427 } 428 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 429 fail_4: 430 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 431 fail_3: 432 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 433 sizeof(struct ae_control_data)); 434 fail_2: 435 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 436 fail_1: 437 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 438 fail_0: 439 return; 440 } 441 442 /* 443 * ae_activate: 444 * 445 * Handle device activation/deactivation requests. 446 */ 447 int 448 ae_activate(device_t self, enum devact act) 449 { 450 struct ae_softc *sc = device_private(self); 451 452 switch (act) { 453 case DVACT_DEACTIVATE: 454 if_deactivate(&sc->sc_ethercom.ec_if); 455 return 0; 456 default: 457 return EOPNOTSUPP; 458 } 459 } 460 461 /* 462 * ae_detach: 463 * 464 * Detach a device interface. 465 */ 466 int 467 ae_detach(device_t self, int flags) 468 { 469 struct ae_softc *sc = device_private(self); 470 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 471 struct ae_rxsoft *rxs; 472 struct ae_txsoft *txs; 473 int i; 474 475 /* 476 * Succeed now if there isn't any work to do. 477 */ 478 if ((sc->sc_flags & AE_ATTACHED) == 0) 479 return (0); 480 481 /* Unhook our tick handler. */ 482 if (sc->sc_tick) 483 callout_stop(&sc->sc_tick_callout); 484 485 /* Detach all PHYs */ 486 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 487 488 rnd_detach_source(&sc->sc_rnd_source); 489 ether_ifdetach(ifp); 490 if_detach(ifp); 491 492 /* Delete all remaining media. */ 493 ifmedia_fini(&sc->sc_mii.mii_media); 494 495 for (i = 0; i < AE_NRXDESC; i++) { 496 rxs = &sc->sc_rxsoft[i]; 497 if (rxs->rxs_mbuf != NULL) { 498 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 499 m_freem(rxs->rxs_mbuf); 500 rxs->rxs_mbuf = NULL; 501 } 502 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 503 } 504 for (i = 0; i < AE_TXQUEUELEN; i++) { 505 txs = &sc->sc_txsoft[i]; 506 if (txs->txs_mbuf != NULL) { 507 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 508 m_freem(txs->txs_mbuf); 509 txs->txs_mbuf = NULL; 510 } 511 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 512 } 513 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 514 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 515 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 516 sizeof(struct ae_control_data)); 517 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 518 519 shutdownhook_disestablish(sc->sc_sdhook); 520 powerhook_disestablish(sc->sc_powerhook); 521 522 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 523 524 525 return (0); 526 } 527 528 /* 529 * ae_shutdown: 530 * 531 * Make sure the interface is stopped at reboot time. 532 */ 533 static void 534 ae_shutdown(void *arg) 535 { 536 struct ae_softc *sc = arg; 537 538 ae_stop(&sc->sc_ethercom.ec_if, 1); 539 } 540 541 /* 542 * ae_start: [ifnet interface function] 543 * 544 * Start packet transmission on the interface. 545 */ 546 static void 547 ae_start(struct ifnet *ifp) 548 { 549 struct ae_softc *sc = ifp->if_softc; 550 struct mbuf *m0, *m; 551 struct ae_txsoft *txs; 552 bus_dmamap_t dmamap; 553 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 554 555 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 556 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 557 558 559 if ((ifp->if_flags & IFF_RUNNING) == 0) 560 return; 561 562 /* 563 * Remember the previous number of free descriptors and 564 * the first descriptor we'll use. 565 */ 566 ofree = sc->sc_txfree; 567 firsttx = sc->sc_txnext; 568 569 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 570 device_xname(sc->sc_dev), ofree, firsttx)); 571 572 /* 573 * Loop through the send queue, setting up transmit descriptors 574 * until we drain the queue, or use up all available transmit 575 * descriptors. 576 */ 577 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 578 sc->sc_txfree != 0) { 579 /* 580 * Grab a packet off the queue. 581 */ 582 IFQ_POLL(&ifp->if_snd, m0); 583 if (m0 == NULL) 584 break; 585 m = NULL; 586 587 dmamap = txs->txs_dmamap; 588 589 /* 590 * Load the DMA map. If this fails, the packet either 591 * didn't fit in the alloted number of segments, or we were 592 * short on resources. In this case, we'll copy and try 593 * again. 594 */ 595 if (((mtod(m0, uintptr_t) & 3) != 0) || 596 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 597 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 598 MGETHDR(m, M_DONTWAIT, MT_DATA); 599 if (m == NULL) { 600 printf("%s: unable to allocate Tx mbuf\n", 601 device_xname(sc->sc_dev)); 602 break; 603 } 604 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 605 if (m0->m_pkthdr.len > MHLEN) { 606 MCLGET(m, M_DONTWAIT); 607 if ((m->m_flags & M_EXT) == 0) { 608 printf("%s: unable to allocate Tx " 609 "cluster\n", device_xname(sc->sc_dev)); 610 m_freem(m); 611 break; 612 } 613 } 614 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 615 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 616 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 617 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 618 if (error) { 619 printf("%s: unable to load Tx buffer, " 620 "error = %d\n", device_xname(sc->sc_dev), 621 error); 622 break; 623 } 624 } 625 626 /* 627 * Ensure we have enough descriptors free to describe 628 * the packet. 629 */ 630 if (dmamap->dm_nsegs > sc->sc_txfree) { 631 /* 632 * Not enough free descriptors to transmit this 633 * packet. We haven't committed to anything yet, 634 * so just unload the DMA map, put the packet 635 * back on the queue, and punt. Notify the upper 636 * layer that there are no more slots left. 637 * 638 * XXX We could allocate an mbuf and copy, but 639 * XXX it is worth it? 640 */ 641 bus_dmamap_unload(sc->sc_dmat, dmamap); 642 if (m != NULL) 643 m_freem(m); 644 break; 645 } 646 647 IFQ_DEQUEUE(&ifp->if_snd, m0); 648 if (m != NULL) { 649 m_freem(m0); 650 m0 = m; 651 } 652 653 /* 654 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 655 */ 656 657 /* Sync the DMA map. */ 658 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 659 BUS_DMASYNC_PREWRITE); 660 661 /* 662 * Initialize the transmit descriptors. 663 */ 664 for (nexttx = sc->sc_txnext, seg = 0; 665 seg < dmamap->dm_nsegs; 666 seg++, nexttx = AE_NEXTTX(nexttx)) { 667 /* 668 * If this is the first descriptor we're 669 * enqueueing, don't set the OWN bit just 670 * yet. That could cause a race condition. 671 * We'll do it below. 672 */ 673 sc->sc_txdescs[nexttx].ad_status = 674 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 675 sc->sc_txdescs[nexttx].ad_bufaddr1 = 676 dmamap->dm_segs[seg].ds_addr; 677 sc->sc_txdescs[nexttx].ad_ctl = 678 (dmamap->dm_segs[seg].ds_len << 679 ADCTL_SIZE1_SHIFT) | 680 (nexttx == (AE_NTXDESC - 1) ? 681 ADCTL_ER : 0); 682 lasttx = nexttx; 683 } 684 685 KASSERT(lasttx != -1); 686 687 /* Set `first segment' and `last segment' appropriately. */ 688 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 689 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 690 691 #ifdef AE_DEBUG 692 if (ifp->if_flags & IFF_DEBUG) { 693 printf(" txsoft %p transmit chain:\n", txs); 694 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 695 printf(" descriptor %d:\n", seg); 696 printf(" ad_status: 0x%08x\n", 697 sc->sc_txdescs[seg].ad_status); 698 printf(" ad_ctl: 0x%08x\n", 699 sc->sc_txdescs[seg].ad_ctl); 700 printf(" ad_bufaddr1: 0x%08x\n", 701 sc->sc_txdescs[seg].ad_bufaddr1); 702 printf(" ad_bufaddr2: 0x%08x\n", 703 sc->sc_txdescs[seg].ad_bufaddr2); 704 if (seg == lasttx) 705 break; 706 } 707 } 708 #endif 709 710 /* Sync the descriptors we're using. */ 711 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 713 714 /* 715 * Store a pointer to the packet so we can free it later, 716 * and remember what txdirty will be once the packet is 717 * done. 718 */ 719 txs->txs_mbuf = m0; 720 txs->txs_firstdesc = sc->sc_txnext; 721 txs->txs_lastdesc = lasttx; 722 txs->txs_ndescs = dmamap->dm_nsegs; 723 724 /* Advance the tx pointer. */ 725 sc->sc_txfree -= dmamap->dm_nsegs; 726 sc->sc_txnext = nexttx; 727 728 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 729 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 730 731 /* 732 * Pass the packet to any BPF listeners. 733 */ 734 bpf_mtap(ifp, m0, BPF_D_OUT); 735 } 736 737 if (sc->sc_txfree != ofree) { 738 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 739 device_xname(sc->sc_dev), lasttx, firsttx)); 740 /* 741 * Cause a transmit interrupt to happen on the 742 * last packet we enqueued. 743 */ 744 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 745 AE_CDTXSYNC(sc, lasttx, 1, 746 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 747 748 /* 749 * The entire packet chain is set up. Give the 750 * first descriptor to the chip now. 751 */ 752 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 753 AE_CDTXSYNC(sc, firsttx, 1, 754 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 755 756 /* Wake up the transmitter. */ 757 /* XXX USE AUTOPOLLING? */ 758 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 759 AE_BARRIER(sc); 760 761 /* Set a watchdog timer in case the chip flakes out. */ 762 ifp->if_timer = 5; 763 } 764 } 765 766 /* 767 * ae_watchdog: [ifnet interface function] 768 * 769 * Watchdog timer handler. 770 */ 771 static void 772 ae_watchdog(struct ifnet *ifp) 773 { 774 struct ae_softc *sc = ifp->if_softc; 775 int doing_transmit; 776 777 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 778 779 if (doing_transmit) { 780 printf("%s: transmit timeout\n", device_xname(sc->sc_dev)); 781 if_statinc(ifp, if_oerrors); 782 } 783 else 784 printf("%s: spurious watchdog timeout\n", device_xname(sc->sc_dev)); 785 786 (void) ae_init(ifp); 787 788 /* Try to get more packets going. */ 789 ae_start(ifp); 790 } 791 792 /* If the interface is up and running, only modify the receive 793 * filter when changing to/from promiscuous mode. Otherwise return 794 * ENETRESET so that ether_ioctl will reset the chip. 795 */ 796 static int 797 ae_ifflags_cb(struct ethercom *ec) 798 { 799 struct ifnet *ifp = &ec->ec_if; 800 struct ae_softc *sc = ifp->if_softc; 801 u_short change = ifp->if_flags ^ sc->sc_if_flags; 802 803 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 804 return ENETRESET; 805 else if ((change & IFF_PROMISC) != 0) 806 ae_filter_setup(sc); 807 return 0; 808 } 809 810 /* 811 * ae_ioctl: [ifnet interface function] 812 * 813 * Handle control requests from the operator. 814 */ 815 static int 816 ae_ioctl(struct ifnet *ifp, u_long cmd, void *data) 817 { 818 struct ae_softc *sc = ifp->if_softc; 819 int s, error; 820 821 s = splnet(); 822 823 error = ether_ioctl(ifp, cmd, data); 824 if (error == ENETRESET) { 825 if (ifp->if_flags & IFF_RUNNING) { 826 /* 827 * Multicast list has changed. Set the 828 * hardware filter accordingly. 829 */ 830 ae_filter_setup(sc); 831 } 832 error = 0; 833 } 834 835 /* Try to get more packets going. */ 836 if (AE_IS_ENABLED(sc)) 837 ae_start(ifp); 838 839 sc->sc_if_flags = ifp->if_flags; 840 splx(s); 841 return (error); 842 } 843 844 /* 845 * ae_intr: 846 * 847 * Interrupt service routine. 848 */ 849 int 850 ae_intr(void *arg) 851 { 852 struct ae_softc *sc = arg; 853 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 854 uint32_t status, rxstatus, txstatus; 855 int handled = 0, txthresh; 856 857 DPRINTF(sc, ("%s: ae_intr\n", device_xname(sc->sc_dev))); 858 859 #ifdef DEBUG 860 if (AE_IS_ENABLED(sc) == 0) 861 panic("%s: ae_intr: not enabled", device_xname(sc->sc_dev)); 862 #endif 863 864 /* 865 * If the interface isn't running, the interrupt couldn't 866 * possibly have come from us. 867 */ 868 if ((ifp->if_flags & IFF_RUNNING) == 0 || 869 !device_is_active(sc->sc_dev)) { 870 printf("spurious?!?\n"); 871 return (0); 872 } 873 874 for (;;) { 875 status = AE_READ(sc, CSR_STATUS); 876 if (status) { 877 AE_WRITE(sc, CSR_STATUS, status); 878 AE_BARRIER(sc); 879 } 880 881 if ((status & sc->sc_inten) == 0) 882 break; 883 884 handled = 1; 885 886 rxstatus = status & sc->sc_rxint_mask; 887 txstatus = status & sc->sc_txint_mask; 888 889 if (rxstatus) { 890 /* Grab new any new packets. */ 891 ae_rxintr(sc); 892 893 if (rxstatus & STATUS_RU) { 894 printf("%s: receive ring overrun\n", 895 device_xname(sc->sc_dev)); 896 /* Get the receive process going again. */ 897 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 898 AE_BARRIER(sc); 899 break; 900 } 901 } 902 903 if (txstatus) { 904 /* Sweep up transmit descriptors. */ 905 ae_txintr(sc); 906 907 if (txstatus & STATUS_TJT) 908 printf("%s: transmit jabber timeout\n", 909 device_xname(sc->sc_dev)); 910 911 if (txstatus & STATUS_UNF) { 912 /* 913 * Increase our transmit threshold if 914 * another is available. 915 */ 916 txthresh = sc->sc_txthresh + 1; 917 if (ae_txthresh[txthresh].txth_name != NULL) { 918 uint32_t opmode; 919 /* Idle the transmit process. */ 920 opmode = AE_READ(sc, CSR_OPMODE); 921 ae_idle(sc, OPMODE_ST); 922 923 sc->sc_txthresh = txthresh; 924 opmode &= ~(OPMODE_TR | OPMODE_SF); 925 opmode |= 926 ae_txthresh[txthresh].txth_opmode; 927 printf("%s: transmit underrun; new " 928 "threshold: %s\n", 929 device_xname(sc->sc_dev), 930 ae_txthresh[txthresh].txth_name); 931 932 /* 933 * Set the new threshold and restart 934 * the transmit process. 935 */ 936 AE_WRITE(sc, CSR_OPMODE, opmode); 937 AE_BARRIER(sc); 938 } 939 /* 940 * XXX Log every Nth underrun from 941 * XXX now on? 942 */ 943 } 944 } 945 946 if (status & (STATUS_TPS | STATUS_RPS)) { 947 if (status & STATUS_TPS) 948 printf("%s: transmit process stopped\n", 949 device_xname(sc->sc_dev)); 950 if (status & STATUS_RPS) 951 printf("%s: receive process stopped\n", 952 device_xname(sc->sc_dev)); 953 (void) ae_init(ifp); 954 break; 955 } 956 957 if (status & STATUS_SE) { 958 const char *str; 959 960 if (status & STATUS_TX_ABORT) 961 str = "tx abort"; 962 else if (status & STATUS_RX_ABORT) 963 str = "rx abort"; 964 else 965 str = "unknown error"; 966 967 printf("%s: fatal system error: %s\n", 968 device_xname(sc->sc_dev), str); 969 (void) ae_init(ifp); 970 break; 971 } 972 973 /* 974 * Not handled: 975 * 976 * Transmit buffer unavailable -- normal 977 * condition, nothing to do, really. 978 * 979 * General purpose timer experied -- we don't 980 * use the general purpose timer. 981 * 982 * Early receive interrupt -- not available on 983 * all chips, we just use RI. We also only 984 * use single-segment receive DMA, so this 985 * is mostly useless. 986 */ 987 } 988 989 /* Try to get more packets going. */ 990 if_schedule_deferred_start(ifp); 991 992 if (handled) 993 rnd_add_uint32(&sc->sc_rnd_source, status); 994 return (handled); 995 } 996 997 /* 998 * ae_rxintr: 999 * 1000 * Helper; handle receive interrupts. 1001 */ 1002 static void 1003 ae_rxintr(struct ae_softc *sc) 1004 { 1005 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1006 struct ae_rxsoft *rxs; 1007 struct mbuf *m; 1008 uint32_t rxstat; 1009 int i, len; 1010 1011 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1012 rxs = &sc->sc_rxsoft[i]; 1013 1014 AE_CDRXSYNC(sc, i, 1015 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1016 1017 rxstat = sc->sc_rxdescs[i].ad_status; 1018 1019 if (rxstat & ADSTAT_OWN) { 1020 /* 1021 * We have processed all of the receive buffers. 1022 */ 1023 break; 1024 } 1025 1026 /* 1027 * If any collisions were seen on the wire, count one. 1028 */ 1029 if (rxstat & ADSTAT_Rx_CS) 1030 if_statinc(ifp, if_collisions); 1031 1032 /* 1033 * If an error occurred, update stats, clear the status 1034 * word, and leave the packet buffer in place. It will 1035 * simply be reused the next time the ring comes around. 1036 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1037 * error. 1038 */ 1039 if (rxstat & ADSTAT_ES && 1040 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1041 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1042 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1043 #define PRINTERR(bit, str) \ 1044 if (rxstat & (bit)) \ 1045 printf("%s: receive error: %s\n", \ 1046 device_xname(sc->sc_dev), str) 1047 if_statinc(ifp, if_ierrors); 1048 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1049 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1050 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1051 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1052 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1053 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1054 #undef PRINTERR 1055 AE_INIT_RXDESC(sc, i); 1056 continue; 1057 } 1058 1059 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1060 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1061 1062 /* 1063 * No errors; receive the packet. Note the chip 1064 * includes the CRC with every packet. 1065 */ 1066 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1067 1068 /* 1069 * XXX: the Atheros part can align on half words. what 1070 * is the performance implication of this? Probably 1071 * minimal, and we should use it... 1072 */ 1073 #ifdef __NO_STRICT_ALIGNMENT 1074 /* 1075 * Allocate a new mbuf cluster. If that fails, we are 1076 * out of memory, and must drop the packet and recycle 1077 * the buffer that's already attached to this descriptor. 1078 */ 1079 m = rxs->rxs_mbuf; 1080 if (ae_add_rxbuf(sc, i) != 0) { 1081 if_statinc(ifp, if_ierrors); 1082 AE_INIT_RXDESC(sc, i); 1083 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1084 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1085 continue; 1086 } 1087 #else 1088 /* 1089 * The chip's receive buffers must be 4-byte aligned. 1090 * But this means that the data after the Ethernet header 1091 * is misaligned. We must allocate a new buffer and 1092 * copy the data, shifted forward 2 bytes. 1093 */ 1094 MGETHDR(m, M_DONTWAIT, MT_DATA); 1095 if (m == NULL) { 1096 dropit: 1097 if_statinc(ifp, if_ierrors); 1098 AE_INIT_RXDESC(sc, i); 1099 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1100 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1101 continue; 1102 } 1103 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1104 if (len > (MHLEN - 2)) { 1105 MCLGET(m, M_DONTWAIT); 1106 if ((m->m_flags & M_EXT) == 0) { 1107 m_freem(m); 1108 goto dropit; 1109 } 1110 } 1111 m->m_data += 2; 1112 1113 /* 1114 * Note that we use clusters for incoming frames, so the 1115 * buffer is virtually contiguous. 1116 */ 1117 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 1118 1119 /* Allow the receive descriptor to continue using its mbuf. */ 1120 AE_INIT_RXDESC(sc, i); 1121 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1122 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1123 #endif /* __NO_STRICT_ALIGNMENT */ 1124 1125 m_set_rcvif(m, ifp); 1126 m->m_pkthdr.len = m->m_len = len; 1127 1128 /* Pass it on. */ 1129 if_percpuq_enqueue(ifp->if_percpuq, m); 1130 } 1131 1132 /* Update the receive pointer. */ 1133 sc->sc_rxptr = i; 1134 } 1135 1136 /* 1137 * ae_txintr: 1138 * 1139 * Helper; handle transmit interrupts. 1140 */ 1141 static void 1142 ae_txintr(struct ae_softc *sc) 1143 { 1144 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1145 struct ae_txsoft *txs; 1146 uint32_t txstat; 1147 1148 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1149 device_xname(sc->sc_dev), sc->sc_flags)); 1150 1151 /* 1152 * Go through our Tx list and free mbufs for those 1153 * frames that have been transmitted. 1154 */ 1155 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1156 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1157 txs->txs_ndescs, 1158 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1159 1160 #ifdef AE_DEBUG 1161 if (ifp->if_flags & IFF_DEBUG) { 1162 int i; 1163 printf(" txsoft %p transmit chain:\n", txs); 1164 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1165 printf(" descriptor %d:\n", i); 1166 printf(" ad_status: 0x%08x\n", 1167 sc->sc_txdescs[i].ad_status); 1168 printf(" ad_ctl: 0x%08x\n", 1169 sc->sc_txdescs[i].ad_ctl); 1170 printf(" ad_bufaddr1: 0x%08x\n", 1171 sc->sc_txdescs[i].ad_bufaddr1); 1172 printf(" ad_bufaddr2: 0x%08x\n", 1173 sc->sc_txdescs[i].ad_bufaddr2); 1174 if (i == txs->txs_lastdesc) 1175 break; 1176 } 1177 } 1178 #endif 1179 1180 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1181 if (txstat & ADSTAT_OWN) 1182 break; 1183 1184 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1185 1186 sc->sc_txfree += txs->txs_ndescs; 1187 1188 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1189 0, txs->txs_dmamap->dm_mapsize, 1190 BUS_DMASYNC_POSTWRITE); 1191 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1192 m_freem(txs->txs_mbuf); 1193 txs->txs_mbuf = NULL; 1194 1195 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1196 1197 /* 1198 * Check for errors and collisions. 1199 */ 1200 #ifdef AE_STATS 1201 if (txstat & ADSTAT_Tx_UF) 1202 sc->sc_stats.ts_tx_uf++; 1203 if (txstat & ADSTAT_Tx_TO) 1204 sc->sc_stats.ts_tx_to++; 1205 if (txstat & ADSTAT_Tx_EC) 1206 sc->sc_stats.ts_tx_ec++; 1207 if (txstat & ADSTAT_Tx_LC) 1208 sc->sc_stats.ts_tx_lc++; 1209 #endif 1210 1211 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1212 if (txstat & (ADSTAT_Tx_UF | ADSTAT_Tx_TO)) 1213 if_statinc_ref(nsr, if_oerrors); 1214 1215 if (txstat & ADSTAT_Tx_EC) 1216 if_statadd_ref(nsr, if_collisions, 16); 1217 else if (ADSTAT_Tx_COLLISIONS(txstat)) 1218 if_statadd_ref(nsr, if_collisions, 1219 ADSTAT_Tx_COLLISIONS(txstat)); 1220 if (txstat & ADSTAT_Tx_LC) 1221 if_statinc_ref(nsr, if_collisions); 1222 1223 if_statinc_ref(nsr, if_opackets); 1224 IF_STAT_PUTREF(ifp); 1225 } 1226 1227 /* 1228 * If there are no more pending transmissions, cancel the watchdog 1229 * timer. 1230 */ 1231 if (txs == NULL) 1232 ifp->if_timer = 0; 1233 } 1234 1235 #ifdef AE_STATS 1236 void 1237 ae_print_stats(struct ae_softc *sc) 1238 { 1239 1240 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1241 device_xname(sc->sc_dev), 1242 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1243 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1244 } 1245 #endif 1246 1247 /* 1248 * ae_reset: 1249 * 1250 * Perform a soft reset on the chip. 1251 */ 1252 void 1253 ae_reset(struct ae_softc *sc) 1254 { 1255 int i; 1256 1257 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1258 AE_BARRIER(sc); 1259 1260 /* 1261 * The chip doesn't take itself out of reset automatically. 1262 * We need to do so after 2us. 1263 */ 1264 delay(10); 1265 AE_WRITE(sc, CSR_BUSMODE, 0); 1266 AE_BARRIER(sc); 1267 1268 for (i = 0; i < 1000; i++) { 1269 /* 1270 * Wait a bit for the reset to complete before peeking 1271 * at the chip again. 1272 */ 1273 delay(10); 1274 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1275 break; 1276 } 1277 1278 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1279 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 1280 1281 delay(1000); 1282 } 1283 1284 /* 1285 * ae_init: [ ifnet interface function ] 1286 * 1287 * Initialize the interface. Must be called at splnet(). 1288 */ 1289 static int 1290 ae_init(struct ifnet *ifp) 1291 { 1292 struct ae_softc *sc = ifp->if_softc; 1293 struct ae_txsoft *txs; 1294 struct ae_rxsoft *rxs; 1295 const uint8_t *enaddr; 1296 int i, error = 0; 1297 1298 if ((error = ae_enable(sc)) != 0) 1299 goto out; 1300 1301 /* 1302 * Cancel any pending I/O. 1303 */ 1304 ae_stop(ifp, 0); 1305 1306 /* 1307 * Reset the chip to a known state. 1308 */ 1309 ae_reset(sc); 1310 1311 /* 1312 * Initialize the BUSMODE register. 1313 */ 1314 AE_WRITE(sc, CSR_BUSMODE, 1315 /* XXX: not sure if this is a good thing or not... */ 1316 //BUSMODE_ALIGN_16B | 1317 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1318 AE_BARRIER(sc); 1319 1320 /* 1321 * Initialize the transmit descriptor ring. 1322 */ 1323 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1324 for (i = 0; i < AE_NTXDESC; i++) { 1325 sc->sc_txdescs[i].ad_ctl = 0; 1326 sc->sc_txdescs[i].ad_bufaddr2 = 1327 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1328 } 1329 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1330 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1331 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1332 sc->sc_txfree = AE_NTXDESC; 1333 sc->sc_txnext = 0; 1334 1335 /* 1336 * Initialize the transmit job descriptors. 1337 */ 1338 SIMPLEQ_INIT(&sc->sc_txfreeq); 1339 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1340 for (i = 0; i < AE_TXQUEUELEN; i++) { 1341 txs = &sc->sc_txsoft[i]; 1342 txs->txs_mbuf = NULL; 1343 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1344 } 1345 1346 /* 1347 * Initialize the receive descriptor and receive job 1348 * descriptor rings. 1349 */ 1350 for (i = 0; i < AE_NRXDESC; i++) { 1351 rxs = &sc->sc_rxsoft[i]; 1352 if (rxs->rxs_mbuf == NULL) { 1353 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1354 printf("%s: unable to allocate or map rx " 1355 "buffer %d, error = %d\n", 1356 device_xname(sc->sc_dev), i, error); 1357 /* 1358 * XXX Should attempt to run with fewer receive 1359 * XXX buffers instead of just failing. 1360 */ 1361 ae_rxdrain(sc); 1362 goto out; 1363 } 1364 } else 1365 AE_INIT_RXDESC(sc, i); 1366 } 1367 sc->sc_rxptr = 0; 1368 1369 /* 1370 * Initialize the interrupt mask and enable interrupts. 1371 */ 1372 /* normal interrupts */ 1373 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1374 1375 /* abnormal interrupts */ 1376 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1377 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1378 1379 sc->sc_rxint_mask = STATUS_RI | STATUS_RU; 1380 sc->sc_txint_mask = STATUS_TI | STATUS_UNF | STATUS_TJT; 1381 1382 sc->sc_rxint_mask &= sc->sc_inten; 1383 sc->sc_txint_mask &= sc->sc_inten; 1384 1385 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1386 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1387 1388 /* 1389 * Give the transmit and receive rings to the chip. 1390 */ 1391 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1392 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1393 AE_BARRIER(sc); 1394 1395 /* 1396 * Set the station address. 1397 */ 1398 enaddr = CLLADDR(ifp->if_sadl); 1399 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1400 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1401 enaddr[1] << 8 | enaddr[0]); 1402 AE_BARRIER(sc); 1403 1404 /* 1405 * Set the receive filter. This will start the transmit and 1406 * receive processes. 1407 */ 1408 ae_filter_setup(sc); 1409 1410 /* 1411 * Set the current media. 1412 */ 1413 if ((error = ether_mediachange(ifp)) != 0) 1414 goto out; 1415 1416 /* 1417 * Start the mac. 1418 */ 1419 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1420 AE_BARRIER(sc); 1421 1422 /* 1423 * Write out the opmode. 1424 */ 1425 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1426 ae_txthresh[sc->sc_txthresh].txth_opmode); 1427 /* 1428 * Start the receive process. 1429 */ 1430 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1431 AE_BARRIER(sc); 1432 1433 if (sc->sc_tick != NULL) { 1434 /* Start the one second clock. */ 1435 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1436 } 1437 1438 /* 1439 * Note that the interface is now running. 1440 */ 1441 ifp->if_flags |= IFF_RUNNING; 1442 sc->sc_if_flags = ifp->if_flags; 1443 1444 out: 1445 if (error) { 1446 ifp->if_flags &= ~IFF_RUNNING; 1447 ifp->if_timer = 0; 1448 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1449 } 1450 return (error); 1451 } 1452 1453 /* 1454 * ae_enable: 1455 * 1456 * Enable the chip. 1457 */ 1458 static int 1459 ae_enable(struct ae_softc *sc) 1460 { 1461 1462 if (AE_IS_ENABLED(sc) == 0) { 1463 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1464 ae_intr, sc); 1465 if (sc->sc_ih == NULL) { 1466 printf("%s: unable to establish interrupt\n", 1467 device_xname(sc->sc_dev)); 1468 return (EIO); 1469 } 1470 sc->sc_flags |= AE_ENABLED; 1471 } 1472 return (0); 1473 } 1474 1475 /* 1476 * ae_disable: 1477 * 1478 * Disable the chip. 1479 */ 1480 static void 1481 ae_disable(struct ae_softc *sc) 1482 { 1483 1484 if (AE_IS_ENABLED(sc)) { 1485 arbus_intr_disestablish(sc->sc_ih); 1486 sc->sc_flags &= ~AE_ENABLED; 1487 } 1488 } 1489 1490 /* 1491 * ae_power: 1492 * 1493 * Power management (suspend/resume) hook. 1494 */ 1495 static void 1496 ae_power(int why, void *arg) 1497 { 1498 struct ae_softc *sc = arg; 1499 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1500 int s; 1501 1502 printf("power called: %d, %x\n", why, (uint32_t)arg); 1503 s = splnet(); 1504 switch (why) { 1505 case PWR_STANDBY: 1506 /* do nothing! */ 1507 break; 1508 case PWR_SUSPEND: 1509 ae_stop(ifp, 0); 1510 ae_disable(sc); 1511 break; 1512 case PWR_RESUME: 1513 if (ifp->if_flags & IFF_UP) { 1514 ae_enable(sc); 1515 ae_init(ifp); 1516 } 1517 break; 1518 case PWR_SOFTSUSPEND: 1519 case PWR_SOFTSTANDBY: 1520 case PWR_SOFTRESUME: 1521 break; 1522 } 1523 splx(s); 1524 } 1525 1526 /* 1527 * ae_rxdrain: 1528 * 1529 * Drain the receive queue. 1530 */ 1531 static void 1532 ae_rxdrain(struct ae_softc *sc) 1533 { 1534 struct ae_rxsoft *rxs; 1535 int i; 1536 1537 for (i = 0; i < AE_NRXDESC; i++) { 1538 rxs = &sc->sc_rxsoft[i]; 1539 if (rxs->rxs_mbuf != NULL) { 1540 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1541 m_freem(rxs->rxs_mbuf); 1542 rxs->rxs_mbuf = NULL; 1543 } 1544 } 1545 } 1546 1547 /* 1548 * ae_stop: [ ifnet interface function ] 1549 * 1550 * Stop transmission on the interface. 1551 */ 1552 static void 1553 ae_stop(struct ifnet *ifp, int disable) 1554 { 1555 struct ae_softc *sc = ifp->if_softc; 1556 struct ae_txsoft *txs; 1557 1558 if (sc->sc_tick != NULL) { 1559 /* Stop the one second clock. */ 1560 callout_stop(&sc->sc_tick_callout); 1561 } 1562 1563 /* Down the MII. */ 1564 mii_down(&sc->sc_mii); 1565 1566 /* Disable interrupts. */ 1567 AE_WRITE(sc, CSR_INTEN, 0); 1568 1569 /* Stop the transmit and receive processes. */ 1570 AE_WRITE(sc, CSR_OPMODE, 0); 1571 AE_WRITE(sc, CSR_RXLIST, 0); 1572 AE_WRITE(sc, CSR_TXLIST, 0); 1573 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1574 AE_BARRIER(sc); 1575 1576 /* 1577 * Release any queued transmit buffers. 1578 */ 1579 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1580 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1581 if (txs->txs_mbuf != NULL) { 1582 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1583 m_freem(txs->txs_mbuf); 1584 txs->txs_mbuf = NULL; 1585 } 1586 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1587 } 1588 1589 /* 1590 * Mark the interface down and cancel the watchdog timer. 1591 */ 1592 ifp->if_flags &= ~IFF_RUNNING; 1593 sc->sc_if_flags = ifp->if_flags; 1594 ifp->if_timer = 0; 1595 1596 if (disable) { 1597 ae_rxdrain(sc); 1598 ae_disable(sc); 1599 } 1600 1601 /* 1602 * Reset the chip (needed on some flavors to actually disable it). 1603 */ 1604 ae_reset(sc); 1605 } 1606 1607 /* 1608 * ae_add_rxbuf: 1609 * 1610 * Add a receive buffer to the indicated descriptor. 1611 */ 1612 static int 1613 ae_add_rxbuf(struct ae_softc *sc, int idx) 1614 { 1615 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1616 struct mbuf *m; 1617 int error; 1618 1619 MGETHDR(m, M_DONTWAIT, MT_DATA); 1620 if (m == NULL) 1621 return (ENOBUFS); 1622 1623 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1624 MCLGET(m, M_DONTWAIT); 1625 if ((m->m_flags & M_EXT) == 0) { 1626 m_freem(m); 1627 return (ENOBUFS); 1628 } 1629 1630 if (rxs->rxs_mbuf != NULL) 1631 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1632 1633 rxs->rxs_mbuf = m; 1634 1635 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1636 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1637 BUS_DMA_READ | BUS_DMA_NOWAIT); 1638 if (error) { 1639 printf("%s: can't load rx DMA map %d, error = %d\n", 1640 device_xname(sc->sc_dev), idx, error); 1641 panic("ae_add_rxbuf"); /* XXX */ 1642 } 1643 1644 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1645 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1646 1647 AE_INIT_RXDESC(sc, idx); 1648 1649 return (0); 1650 } 1651 1652 /* 1653 * ae_filter_setup: 1654 * 1655 * Set the chip's receive filter. 1656 */ 1657 static void 1658 ae_filter_setup(struct ae_softc *sc) 1659 { 1660 struct ethercom *ec = &sc->sc_ethercom; 1661 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1662 struct ether_multi *enm; 1663 struct ether_multistep step; 1664 uint32_t hash, mchash[2]; 1665 uint32_t macctl = 0; 1666 1667 /* 1668 * If the chip is running, we need to reset the interface, 1669 * and will revisit here (with IFF_RUNNING) clear. The 1670 * chip seems to really not like to have its multicast 1671 * filter programmed without a reset. 1672 */ 1673 if (ifp->if_flags & IFF_RUNNING) { 1674 (void) ae_init(ifp); 1675 return; 1676 } 1677 1678 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1679 device_xname(sc->sc_dev), sc->sc_flags)); 1680 1681 macctl = AE_READ(sc, CSR_MACCTL); 1682 macctl &= ~(MACCTL_PR | MACCTL_PM); 1683 macctl |= MACCTL_HASH; 1684 macctl |= MACCTL_HBD; 1685 macctl |= MACCTL_PR; 1686 1687 if (ifp->if_flags & IFF_PROMISC) { 1688 macctl |= MACCTL_PR; 1689 goto allmulti; 1690 } 1691 1692 mchash[0] = mchash[1] = 0; 1693 1694 ETHER_LOCK(ec); 1695 ETHER_FIRST_MULTI(step, ec, enm); 1696 while (enm != NULL) { 1697 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1698 /* 1699 * We must listen to a range of multicast addresses. 1700 * For now, just accept all multicasts, rather than 1701 * trying to set only those filter bits needed to match 1702 * the range. (At this time, the only use of address 1703 * ranges is for IP multicast routing, for which the 1704 * range is big enough to require all bits set.) 1705 */ 1706 ETHER_UNLOCK(ec); 1707 goto allmulti; 1708 } 1709 1710 /* Verify whether we use big or little endian hashes */ 1711 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1712 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1713 ETHER_NEXT_MULTI(step, enm); 1714 } 1715 ETHER_UNLOCK(ec); 1716 ifp->if_flags &= ~IFF_ALLMULTI; 1717 goto setit; 1718 1719 allmulti: 1720 ifp->if_flags |= IFF_ALLMULTI; 1721 mchash[0] = mchash[1] = 0xffffffff; 1722 macctl |= MACCTL_PM; 1723 1724 setit: 1725 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1726 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1727 1728 AE_WRITE(sc, CSR_MACCTL, macctl); 1729 AE_BARRIER(sc); 1730 1731 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1732 device_xname(sc->sc_dev), macctl)); 1733 } 1734 1735 /* 1736 * ae_idle: 1737 * 1738 * Cause the transmit and/or receive processes to go idle. 1739 */ 1740 void 1741 ae_idle(struct ae_softc *sc, uint32_t bits) 1742 { 1743 static const char * const txstate_names[] = { 1744 "STOPPED", 1745 "RUNNING - FETCH", 1746 "RUNNING - WAIT", 1747 "RUNNING - READING", 1748 "-- RESERVED --", 1749 "RUNNING - SETUP", 1750 "SUSPENDED", 1751 "RUNNING - CLOSE", 1752 }; 1753 static const char * const rxstate_names[] = { 1754 "STOPPED", 1755 "RUNNING - FETCH", 1756 "RUNNING - CHECK", 1757 "RUNNING - WAIT", 1758 "SUSPENDED", 1759 "RUNNING - CLOSE", 1760 "RUNNING - FLUSH", 1761 "RUNNING - QUEUE", 1762 }; 1763 1764 uint32_t csr, ackmask = 0; 1765 int i; 1766 1767 if (bits & OPMODE_ST) 1768 ackmask |= STATUS_TPS; 1769 1770 if (bits & OPMODE_SR) 1771 ackmask |= STATUS_RPS; 1772 1773 AE_CLR(sc, CSR_OPMODE, bits); 1774 1775 for (i = 0; i < 1000; i++) { 1776 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1777 break; 1778 delay(10); 1779 } 1780 1781 csr = AE_READ(sc, CSR_STATUS); 1782 if ((csr & ackmask) != ackmask) { 1783 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1784 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1785 printf("%s: transmit process failed to idle: " 1786 "state %s\n", device_xname(sc->sc_dev), 1787 txstate_names[(csr & STATUS_TS) >> 20]); 1788 } 1789 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1790 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1791 printf("%s: receive process failed to idle: " 1792 "state %s\n", device_xname(sc->sc_dev), 1793 rxstate_names[(csr & STATUS_RS) >> 17]); 1794 } 1795 } 1796 } 1797 1798 /***************************************************************************** 1799 * Support functions for MII-attached media. 1800 *****************************************************************************/ 1801 1802 /* 1803 * ae_mii_tick: 1804 * 1805 * One second timer, used to tick the MII. 1806 */ 1807 static void 1808 ae_mii_tick(void *arg) 1809 { 1810 struct ae_softc *sc = arg; 1811 int s; 1812 1813 if (!device_is_active(sc->sc_dev)) 1814 return; 1815 1816 s = splnet(); 1817 mii_tick(&sc->sc_mii); 1818 splx(s); 1819 1820 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1821 } 1822 1823 /* 1824 * ae_mii_statchg: [mii interface function] 1825 * 1826 * Callback from PHY when media changes. 1827 */ 1828 static void 1829 ae_mii_statchg(struct ifnet *ifp) 1830 { 1831 struct ae_softc *sc = ifp->if_softc; 1832 uint32_t macctl, flowc; 1833 1834 //opmode = AE_READ(sc, CSR_OPMODE); 1835 macctl = AE_READ(sc, CSR_MACCTL); 1836 1837 /* XXX: do we need to do this? */ 1838 /* Idle the transmit and receive processes. */ 1839 //ae_idle(sc, OPMODE_ST | OPMODE_SR); 1840 1841 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1842 flowc = FLOWC_FCE; 1843 macctl &= ~MACCTL_DRO; 1844 macctl |= MACCTL_FDX; 1845 } else { 1846 flowc = 0; /* cannot do flow control in HDX */ 1847 macctl |= MACCTL_DRO; 1848 macctl &= ~MACCTL_FDX; 1849 } 1850 1851 AE_WRITE(sc, CSR_FLOWC, flowc); 1852 AE_WRITE(sc, CSR_MACCTL, macctl); 1853 1854 /* restore operational mode */ 1855 //AE_WRITE(sc, CSR_OPMODE, opmode); 1856 AE_BARRIER(sc); 1857 } 1858 1859 /* 1860 * ae_mii_readreg: 1861 * 1862 * Read a PHY register. 1863 */ 1864 static int 1865 ae_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1866 { 1867 struct ae_softc *sc = device_private(self); 1868 uint32_t addr; 1869 int i; 1870 1871 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1872 AE_WRITE(sc, CSR_MIIADDR, addr); 1873 AE_BARRIER(sc); 1874 for (i = 0; i < 100000000; i++) { 1875 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1876 break; 1877 } 1878 1879 if (i >= 100000000) 1880 return ETIMEDOUT; 1881 1882 *val = AE_READ(sc, CSR_MIIDATA) & 0xffff; 1883 return 0; 1884 } 1885 1886 /* 1887 * ae_mii_writereg: 1888 * 1889 * Write a PHY register. 1890 */ 1891 static int 1892 ae_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1893 { 1894 struct ae_softc *sc = device_private(self); 1895 uint32_t addr; 1896 int i; 1897 1898 /* write the data register */ 1899 AE_WRITE(sc, CSR_MIIDATA, val); 1900 1901 /* write the address to latch it in */ 1902 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1903 MIIADDR_WRITE; 1904 AE_WRITE(sc, CSR_MIIADDR, addr); 1905 AE_BARRIER(sc); 1906 1907 for (i = 0; i < 100000000; i++) { 1908 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1909 break; 1910 } 1911 1912 if (i >= 100000000) 1913 return ETIMEDOUT; 1914 1915 return 0; 1916 } 1917
Indexes created Wed Sep 24 15:09:51 GMT 2025