ar5312reg.h revision 1.2.4.2
1 1.2.4.2 rpaulo /* $Id: ar5312reg.h,v 1.2.4.2 2006/09/09 02:41:25 rpaulo Exp $ */ 2 1.2.4.2 rpaulo /* 3 1.2.4.2 rpaulo * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 1.2.4.2 rpaulo * Copyright (c) 2006 Garrett D'Amore. 5 1.2.4.2 rpaulo * All rights reserved. 6 1.2.4.2 rpaulo * 7 1.2.4.2 rpaulo * This code was written by Garrett D'Amore for the Champaign-Urbana 8 1.2.4.2 rpaulo * Community Wireless Network Project. 9 1.2.4.2 rpaulo * 10 1.2.4.2 rpaulo * Redistribution and use in source and binary forms, with or 11 1.2.4.2 rpaulo * without modification, are permitted provided that the following 12 1.2.4.2 rpaulo * conditions are met: 13 1.2.4.2 rpaulo * 1. Redistributions of source code must retain the above copyright 14 1.2.4.2 rpaulo * notice, this list of conditions and the following disclaimer. 15 1.2.4.2 rpaulo * 2. Redistributions in binary form must reproduce the above 16 1.2.4.2 rpaulo * copyright notice, this list of conditions and the following 17 1.2.4.2 rpaulo * disclaimer in the documentation and/or other materials provided 18 1.2.4.2 rpaulo * with the distribution. 19 1.2.4.2 rpaulo * 3. All advertising materials mentioning features or use of this 20 1.2.4.2 rpaulo * software must display the following acknowledgements: 21 1.2.4.2 rpaulo * This product includes software developed by the Urbana-Champaign 22 1.2.4.2 rpaulo * Independent Media Center. 23 1.2.4.2 rpaulo * This product includes software developed by Garrett D'Amore. 24 1.2.4.2 rpaulo * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 1.2.4.2 rpaulo * D'Amore's name may not be used to endorse or promote products 26 1.2.4.2 rpaulo * derived from this software without specific prior written permission. 27 1.2.4.2 rpaulo * 28 1.2.4.2 rpaulo * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 1.2.4.2 rpaulo * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 1.2.4.2 rpaulo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 1.2.4.2 rpaulo * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 1.2.4.2 rpaulo * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 1.2.4.2 rpaulo * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 1.2.4.2 rpaulo * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 1.2.4.2 rpaulo * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 1.2.4.2 rpaulo * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 1.2.4.2 rpaulo * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 1.2.4.2 rpaulo * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 1.2.4.2 rpaulo * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 1.2.4.2 rpaulo * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 1.2.4.2 rpaulo */ 42 1.2.4.2 rpaulo 43 1.2.4.2 rpaulo #ifndef _MIPS_ATHEROS_AR5312REG_H_ 44 1.2.4.2 rpaulo #define _MIPS_ATHEROS_AR5312REG_H_ 45 1.2.4.2 rpaulo 46 1.2.4.2 rpaulo #define AR5312_MEM0_BASE 0x00000000 /* sdram */ 47 1.2.4.2 rpaulo #define AR5312_MEM1_BASE 0x08000000 /* sdram/flash */ 48 1.2.4.2 rpaulo #define AR5312_MEM3_BASE 0x10000000 /* flash */ 49 1.2.4.2 rpaulo #define AR5312_WLAN0_BASE 0x18000000 50 1.2.4.2 rpaulo #define AR5312_ENET0_BASE 0x18100000 51 1.2.4.2 rpaulo #define AR5312_ENET1_BASE 0x18200000 52 1.2.4.2 rpaulo #define AR5312_SDRAMCTL_BASE 0x18300000 53 1.2.4.2 rpaulo #define AR5312_FLASHCTL_BASE 0x18400000 54 1.2.4.2 rpaulo #define AR5312_WLAN1_BASE 0x18500000 55 1.2.4.2 rpaulo #define AR5312_UART0_BASE 0x1C000000 /* high speed */ 56 1.2.4.2 rpaulo #define AR5312_UART1_BASE 0x1C001000 57 1.2.4.2 rpaulo #define AR5312_GPIO_BASE 0x1C002000 58 1.2.4.2 rpaulo #define AR5312_SYSREG_BASE 0x1C003000 59 1.2.4.2 rpaulo #define AR5312_UARTDMA_BASE 0x1C004000 60 1.2.4.2 rpaulo #define AR5312_FLASH_BASE 0x1E000000 61 1.2.4.2 rpaulo #define AR5312_FLASH_END 0x20000000 /* possibly aliased */ 62 1.2.4.2 rpaulo 63 1.2.4.2 rpaulo /* 64 1.2.4.2 rpaulo * FLASHCTL registers -- offset relative to AR531X_FLASHCTL_BASE 65 1.2.4.2 rpaulo */ 66 1.2.4.2 rpaulo #define AR5312_FLASHCTL_0 0x00 67 1.2.4.2 rpaulo #define AR5312_FLASHCTL_1 0x04 68 1.2.4.2 rpaulo #define AR5312_FLASHCTL_2 0x08 69 1.2.4.2 rpaulo 70 1.2.4.2 rpaulo #define AR5312_FLASHCTL_IDCY_MASK 0xf /* idle cycle turn */ 71 1.2.4.2 rpaulo #define AR5312_FLASHCTL_IDCY_SHIFT 0 72 1.2.4.2 rpaulo #define AR5312_FLASHCTL_WST1_MASK 0x3e0 /* wait state 1 */ 73 1.2.4.2 rpaulo #define AR5312_FLASHCTL_WST1_SHIFT 5 74 1.2.4.2 rpaulo #define AR5312_FLASHCTL_WST2_MASK 0xf800 /* wait state 1 */ 75 1.2.4.2 rpaulo #define AR5312_FLASHCTL_WST2_SHIFT 11 76 1.2.4.2 rpaulo #define AR5312_FLASHCTL_RBLE 0x00000400 /* rd byte enable */ 77 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_MASK 0x00070000 /* addr chk */ 78 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_SHIFT 16 79 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_128K 0x00000000 80 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_256K 0x00010000 81 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_512K 0x00020000 82 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_1M 0x00030000 83 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_2M 0x00040000 84 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_4M 0x00050000 85 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_8M 0x00060000 86 1.2.4.2 rpaulo #define AR5312_FLASHCTL_AC_16M 0x00070000 87 1.2.4.2 rpaulo #define AR5312_FLASHCTL_E 0x00080000 /* enable */ 88 1.2.4.2 rpaulo #define AR5312_FLASHCTL_MW_MASK 0x30000000 /* mem width */ 89 1.2.4.2 rpaulo 90 1.2.4.2 rpaulo /* 91 1.2.4.2 rpaulo * SYSREG registers -- offset relative to AR531X_SYSREG_BASE 92 1.2.4.2 rpaulo */ 93 1.2.4.2 rpaulo #define AR5312_SYSREG_TIMER 0x0000 94 1.2.4.2 rpaulo #define AR5312_SYSREG_TIMER_RELOAD 0x0004 95 1.2.4.2 rpaulo #define AR5312_SYSREG_WDOG_CTL 0x0008 96 1.2.4.2 rpaulo #define AR5312_SYSREG_WDOG_TIMER 0x000c 97 1.2.4.2 rpaulo #define AR5312_SYSREG_MISC_INTSTAT 0x0010 98 1.2.4.2 rpaulo #define AR5312_SYSREG_MISC_INTMASK 0x0014 99 1.2.4.2 rpaulo #define AR5312_SYSREG_INTSTAT 0x0018 100 1.2.4.2 rpaulo #define AR5312_SYSREG_RESETCTL 0x0020 101 1.2.4.2 rpaulo #define AR5312_SYSREG_CLOCKCTL 0x0064 102 1.2.4.2 rpaulo #define AR5312_SYSREG_SCRATCH 0x006c 103 1.2.4.2 rpaulo #define AR5312_SYSREG_AHBPERR 0x0070 104 1.2.4.2 rpaulo #define AR5312_SYSREG_AHBDMAE 0x0078 105 1.2.4.2 rpaulo #define AR5312_SYSREG_ENABLE 0x0080 106 1.2.4.2 rpaulo #define AR5312_SYSREG_REVISION 0x0090 107 1.2.4.2 rpaulo 108 1.2.4.2 rpaulo /* WDOG_CTL watchdog control bits */ 109 1.2.4.2 rpaulo #define AR5312_WDOG_CTL_IGNORE 0x0000 110 1.2.4.2 rpaulo #define AR5312_WDOG_CTL_NMI 0x0001 111 1.2.4.2 rpaulo #define AR5312_WDOG_CTL_RESET 0x0002 112 1.2.4.2 rpaulo 113 1.2.4.2 rpaulo /* Resets */ 114 1.2.4.2 rpaulo #define AR5312_RESET_SYSTEM 0x00000001 115 1.2.4.2 rpaulo #define AR5312_RESET_CPU 0x00000002 116 1.2.4.2 rpaulo #define AR5312_RESET_WLAN0 0x00000004 /* mac & bb */ 117 1.2.4.2 rpaulo #define AR5312_RESET_PHY0 0x00000008 /* enet phy */ 118 1.2.4.2 rpaulo #define AR5312_RESET_PHY1 0x00000010 /* enet phy */ 119 1.2.4.2 rpaulo #define AR5312_RESET_ENET0 0x00000020 /* mac */ 120 1.2.4.2 rpaulo #define AR5312_RESET_ENET1 0x00000040 /* mac */ 121 1.2.4.2 rpaulo #define AR5312_RESET_UART0 0x00000100 /* mac */ 122 1.2.4.2 rpaulo #define AR5312_RESET_WLAN1 0x00000200 /* mac & bb */ 123 1.2.4.2 rpaulo #define AR5312_RESET_APB 0x00000400 /* bridge */ 124 1.2.4.2 rpaulo #define AR5312_RESET_WARM_CPU 0x00001000 125 1.2.4.2 rpaulo #define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 126 1.2.4.2 rpaulo #define AR5312_RESET_WARM_WLAN0_BB 0x00004000 127 1.2.4.2 rpaulo #define AR5312_RESET_NMI 0x00010000 128 1.2.4.2 rpaulo #define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 129 1.2.4.2 rpaulo #define AR5312_RESET_WARM_WLAN1_BB 0x00040000 130 1.2.4.2 rpaulo #define AR5312_RESET_LOCAL_BUS 0x00080000 131 1.2.4.2 rpaulo #define AR5312_RESET_WDOG 0x00100000 132 1.2.4.2 rpaulo 133 1.2.4.2 rpaulo /* AR5312/2312 clockctl bits */ 134 1.2.4.2 rpaulo #define AR5312_CLOCKCTL_PREDIVIDE_MASK 0x00000030 135 1.2.4.2 rpaulo #define AR5312_CLOCKCTL_PREDIVIDE_SHIFT 4 136 1.2.4.2 rpaulo #define AR5312_CLOCKCTL_MULTIPLIER_MASK 0x00001f00 137 1.2.4.2 rpaulo #define AR5312_CLOCKCTL_MULTIPLIER_SHIFT 8 138 1.2.4.2 rpaulo #define AR5312_CLOCKCTL_DOUBLER_MASK 0x00010000 139 1.2.4.2 rpaulo 140 1.2.4.2 rpaulo /* AR2313 clockctl */ 141 1.2.4.2 rpaulo #define AR2313_CLOCKCTL_PREDIVIDE_MASK 0x00003000 142 1.2.4.2 rpaulo #define AR2313_CLOCKCTL_PREDIVIDE_SHIFT 12 143 1.2.4.2 rpaulo #define AR2313_CLOCKCTL_MULTIPLIER_MASK 0x001f0000 144 1.2.4.2 rpaulo #define AR2313_CLOCKCTL_MULTIPLIER_SHIFT 16 145 1.2.4.2 rpaulo #define AR2313_CLOCKCTL_DOUBLER_MASK 0x00000000 146 1.2.4.2 rpaulo 147 1.2.4.2 rpaulo /* Enables */ 148 1.2.4.2 rpaulo #define AR5312_ENABLE_WLAN0 0x0001 149 1.2.4.2 rpaulo #define AR5312_ENABLE_ENET0 0x0002 150 1.2.4.2 rpaulo #define AR5312_ENABLE_ENET1 0x0004 151 1.2.4.2 rpaulo #define AR5312_ENABLE_WLAN1 0x0018 /* both DMA and PIO */ 152 1.2.4.2 rpaulo 153 1.2.4.2 rpaulo /* Revision ids */ 154 1.2.4.2 rpaulo #define AR5312_REVISION_WMAC_MAJOR(x) (((x) >> 12) & 0xf) 155 1.2.4.2 rpaulo #define AR5312_REVISION_WMAC_MINOR(x) (((x) >> 8) & 0xf) 156 1.2.4.2 rpaulo #define AR5312_REVISION_WMAC(x) (((x) >> 8) & 0xff) 157 1.2.4.2 rpaulo #define AR5312_REVISION_MAJOR(x) (((x) >> 4) & 0xf) 158 1.2.4.2 rpaulo #define AR5312_REVISION_MINOR(x) (((x) >> 0) & 0xf) 159 1.2.4.2 rpaulo 160 1.2.4.2 rpaulo #define AR5312_REVISION_MAJ_AR5311 0x1 161 1.2.4.2 rpaulo #define AR5312_REVISION_MAJ_AR5312 0x4 162 1.2.4.2 rpaulo #define AR5312_REVISION_MAJ_AR2313 0x5 163 1.2.4.2 rpaulo #define AR5312_REVISION_MAJ_AR5315 0xB 164 1.2.4.2 rpaulo 165 1.2.4.2 rpaulo /* 166 1.2.4.2 rpaulo * SDRAMCTL registers -- offset relative to SDRAMCTL 167 1.2.4.2 rpaulo */ 168 1.2.4.2 rpaulo #define AR5312_SDRAMCTL_MEM_CFG0 0x0000 169 1.2.4.2 rpaulo #define AR5312_SDRAMCTL_MEM_CFG1 0x0004 170 1.2.4.2 rpaulo 171 1.2.4.2 rpaulo /* memory config 1 bits */ 172 1.2.4.2 rpaulo #define AR5312_MEM_CFG1_BANK0_MASK 0x00000700 173 1.2.4.2 rpaulo #define AR5312_MEM_CFG1_BANK0_SHIFT 8 174 1.2.4.2 rpaulo #define AR5312_MEM_CFG1_BANK1_MASK 0x00007000 175 1.2.4.2 rpaulo #define AR5312_MEM_CFG1_BANK1_SHIFT 12 176 1.2.4.2 rpaulo 177 1.2.4.2 rpaulo /* helper macro for accessing system registers without bus space */ 178 1.2.4.2 rpaulo #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 179 1.2.4.2 rpaulo #define GETSYSREG(x) REGVAL((x) + AR5312_SYSREG_BASE) 180 1.2.4.2 rpaulo #define PUTSYSREG(x,v) (REGVAL((x) + AR5312_SYSREG_BASE)) = (v) 181 1.2.4.2 rpaulo #define GETSDRAMREG(x) REGVAL((x) + AR5312_SDRAMCTL_BASE) 182 1.2.4.2 rpaulo #define PUTSDRAMREG(x,v) (REGVAL((x) + AR5312_SDRAMCTL_BASE)) = (v) 183 1.2.4.2 rpaulo 184 1.2.4.2 rpaulo /* 185 1.2.4.2 rpaulo * Interrupts. 186 1.2.4.2 rpaulo */ 187 1.2.4.2 rpaulo #define AR5312_IRQ_WLAN0 0 188 1.2.4.2 rpaulo #define AR5312_IRQ_ENET0 1 189 1.2.4.2 rpaulo #define AR5312_IRQ_ENET1 2 190 1.2.4.2 rpaulo #define AR5312_IRQ_WLAN1 3 191 1.2.4.2 rpaulo #define AR5312_IRQ_MISC 4 192 1.2.4.2 rpaulo 193 1.2.4.2 rpaulo #define AR5312_MISC_IRQ_TIMER 0 194 1.2.4.2 rpaulo #define AR5312_MISC_IRQ_AHBPERR 1 195 1.2.4.2 rpaulo #define AR5312_MISC_IRQ_AHBDMAE 2 196 1.2.4.2 rpaulo #define AR5312_MISC_IRQ_GPIO 3 197 1.2.4.2 rpaulo #define AR5312_MISC_IRQ_UART0 4 198 1.2.4.2 rpaulo #define AR5312_MISC_IRQ_UART0_DMA 5 199 1.2.4.2 rpaulo #define AR5312_MISC_IRQ_WDOG 6 200 1.2.4.2 rpaulo /* 201 1.2.4.2 rpaulo * Board data. This is located in flash somewhere, ar531x_board_info 202 1.2.4.2 rpaulo * locates it. 203 1.2.4.2 rpaulo */ 204 1.2.4.2 rpaulo #include <contrib/dev/ath/ah_soc.h> /* XXX really doesn't belong in hal */ 205 1.2.4.2 rpaulo 206 1.2.4.2 rpaulo /* XXX write-around for now */ 207 1.2.4.2 rpaulo #define AR5312_BOARD_MAGIC AR531X_BD_MAGIC 208 1.2.4.2 rpaulo 209 1.2.4.2 rpaulo /* config bits */ 210 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_ENET0 BD_ENET0 211 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_ENET1 BD_ENET1 212 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_UART1 BD_UART1 213 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_UART0 BD_UART0 214 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_RSTFACTORY BD_RSTFACTORY 215 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_SYSLED BD_SYSLED 216 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_EXTUARTCLK BD_EXTUARTCLK 217 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_CPUFREQ BD_CPUFREQ 218 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_SYSFREQ BD_SYSFREQ 219 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_WLAN0 BD_WLAN0 220 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_MEMCAP BD_MEMCAP 221 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_DISWDOG BD_DISWATCHDOG 222 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_WLAN1 BD_WLAN1 223 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_AR2312 BD_ISCASPER 224 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_WLAN0_2G BD_WLAN0_2G_EN 225 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_WLAN0_5G BD_WLAN0_5G_EN 226 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_WLAN1_2G BD_WLAN1_2G_EN 227 1.2.4.2 rpaulo #define AR5312_BOARD_CONFIG_WLAN1_5G BD_WLAN1_5G_EN 228 1.2.4.2 rpaulo 229 1.2.4.2 rpaulo #endif /* _MIPS_ATHEROS_AR531XREG_H_ */ 230
Indexes created Thu Oct 23 22:10:10 GMT 2025