ar5312reg.h revision 1.1
1 /* $Id: ar5312reg.h,v 1.1 2006/08/28 07:21:15 gdamore Exp $ */ 2 /* 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 43 #ifndef _MIPS_ATHEROS_AR5312REG_H_ 44 #define _MIPS_ATHEROS_AR5312REG_H_ 45 46 #define AR5312_MEM0_BASE 0x00000000 /* sdram */ 47 #define AR5312_MEM1_BASE 0x08000000 /* sdram/flash */ 48 #define AR5312_MEM3_BASE 0x10000000 /* flash */ 49 #define AR5312_WLAN0_BASE 0x18000000 50 #define AR5312_ENET0_BASE 0x18100000 51 #define AR5312_ENET1_BASE 0x18200000 52 #define AR5312_SDRAMCTL_BASE 0x18300000 53 #define AR5312_FLASHCTL_BASE 0x18400000 54 #define AR5312_WLAN1_BASE 0x18500000 55 #define AR5312_UART0_BASE 0x1C000000 /* high speed */ 56 #define AR5312_UART1_BASE 0x1C001000 57 #define AR5312_GPIO_BASE 0x1C002000 58 #define AR5312_SYSREG_BASE 0x1C003000 59 #define AR5312_UARTDMA_BASE 0x1C004000 60 #define AR5312_FLASH_BASE 0x1E000000 61 #define AR5312_FLASH_END 0x20000000 /* possibly aliased */ 62 63 /* 64 * FLASHCTL registers -- offset relative to AR531X_FLASHCTL_BASE 65 */ 66 #define AR5312_FLASHCTL_0 0x00 67 #define AR5312_FLASHCTL_1 0x04 68 #define AR5312_FLASHCTL_2 0x08 69 70 #define AR5312_FLASHCTL_IDCY_MASK 0xf /* idle cycle turn */ 71 #define AR5312_FLASHCTL_IDCY_SHIFT 0 72 #define AR5312_FLASHCTL_WST1_MASK 0x3e0 /* wait state 1 */ 73 #define AR5312_FLASHCTL_WST1_SHIFT 5 74 #define AR5312_FLASHCTL_WST2_MASK 0xf800 /* wait state 1 */ 75 #define AR5312_FLASHCTL_WST2_SHIFT 11 76 #define AR5312_FLASHCTL_RBLE 0x00000400 /* rd byte enable */ 77 #define AR5312_FLASHCTL_AC_MASK 0x00070000 /* addr chk */ 78 #define AR5312_FLASHCTL_AC_SHIFT 16 79 #define AR5312_FLASHCTL_AC_128K 0x00000000 80 #define AR5312_FLASHCTL_AC_256K 0x00010000 81 #define AR5312_FLASHCTL_AC_512K 0x00020000 82 #define AR5312_FLASHCTL_AC_1M 0x00030000 83 #define AR5312_FLASHCTL_AC_2M 0x00040000 84 #define AR5312_FLASHCTL_AC_4M 0x00050000 85 #define AR5312_FLASHCTL_AC_8M 0x00060000 86 #define AR5312_FLASHCTL_AC_16M 0x00070000 87 #define AR5312_FLASHCTL_E 0x00080000 /* enable */ 88 #define AR5312_FLASHCTL_MW_MASK 0x30000000 /* mem width */ 89 90 /* 91 * SYSREG registers -- offset relative to AR531X_SYSREG_BASE 92 */ 93 #define AR5312_SYSREG_TIMER 0x0000 94 #define AR5312_SYSREG_TIMER_RELOAD 0x0004 95 #define AR5312_SYSREG_WDOG_CTL 0x0008 96 #define AR5312_SYSREG_WDOG_TIMER 0x000c 97 #define AR5312_SYSREG_MISC_INTSTAT 0x0010 98 #define AR5312_SYSREG_MISC_INTMASK 0x0014 99 #define AR5312_SYSREG_INTSTAT 0x0018 100 #define AR5312_SYSREG_RESETCTL 0x0020 101 #define AR5312_SYSREG_CLOCKCTL 0x0064 102 #define AR5312_SYSREG_SCRATCH 0x006c 103 #define AR5312_SYSREG_AHBPERR 0x0070 104 #define AR5312_SYSREG_AHBDMAE 0x0078 105 #define AR5312_SYSREG_ENABLE 0x0080 106 #define AR5312_SYSREG_REVISION 0x0090 107 108 /* WDOG_CTL watchdog control bits */ 109 #define AR5312_WDOG_CTL_IGNORE 0x0000 110 #define AR5312_WDOG_CTL_NMI 0x0001 111 #define AR5312_WDOG_CTL_RESET 0x0002 112 113 /* Resets */ 114 #define AR5312_RESET_SYSTEM 0x00000001 115 #define AR5312_RESET_CPU 0x00000002 116 #define AR5312_RESET_WLAN0 0x00000004 /* mac & bb */ 117 #define AR5312_RESET_PHY0 0x00000008 /* enet phy */ 118 #define AR5312_RESET_PHY1 0x00000010 /* enet phy */ 119 #define AR5312_RESET_ENET0 0x00000020 /* mac */ 120 #define AR5312_RESET_ENET1 0x00000040 /* mac */ 121 #define AR5312_RESET_UART0 0x00000100 /* mac */ 122 #define AR5312_RESET_WLAN1 0x00000200 /* mac & bb */ 123 #define AR5312_RESET_APB 0x00000400 /* bridge */ 124 #define AR5312_RESET_WARM_CPU 0x00001000 125 #define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 126 #define AR5312_RESET_WARM_WLAN0_BB 0x00004000 127 #define AR5312_RESET_NMI 0x00010000 128 #define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 129 #define AR5312_RESET_WARM_WLAN1_BB 0x00040000 130 #define AR5312_RESET_LOCAL_BUS 0x00080000 131 #define AR5312_RESET_WDOG 0x00100000 132 133 /* AR5312/2312 clockctl bits */ 134 #define AR5312_CLOCKCTL_PREDIVIDE_MASK 0x00000030 135 #define AR5312_CLOCKCTL_PREDIVIDE_SHIFT 4 136 #define AR5312_CLOCKCTL_MULTIPLIER_MASK 0x00001f00 137 #define AR5312_CLOCKCTL_MULTIPLIER_SHIFT 8 138 #define AR5312_CLOCKCTL_DOUBLER_MASK 0x00010000 139 140 /* AR2313 clockctl */ 141 #define AR2313_CLOCKCTL_PREDIVIDE_MASK 0x00003000 142 #define AR2313_CLOCKCTL_PREDIVIDE_SHIFT 12 143 #define AR2313_CLOCKCTL_MULTIPLIER_MASK 0x001f0000 144 #define AR2313_CLOCKCTL_MULTIPLIER_SHIFT 16 145 #define AR2313_CLOCKCTL_DOUBLER_MASK 0x00000000 146 147 /* Enables */ 148 #define AR5312_ENABLE_WLAN0 0x0001 149 #define AR5312_ENABLE_ENET0 0x0002 150 #define AR5312_ENABLE_ENET1 0x0004 151 #define AR5312_ENABLE_WLAN1 0x0018 /* both DMA and PIO */ 152 153 /* Revision ids */ 154 #define AR5312_REVISION_WMAC_MAJOR(x) (((x) >> 12) & 0xf) 155 #define AR5312_REVISION_WMAC_MINOR(x) (((x) >> 8) & 0xf) 156 #define AR5312_REVISION_WMAC(x) (((x) >> 8) & 0xff) 157 #define AR5312_REVISION_MAJOR(x) (((x) >> 4) & 0xf) 158 #define AR5312_REVISION_MINOR(x) (((x) >> 0) & 0xf) 159 160 #define AR5312_REVISION_MAJ_AR5311 0x1 161 #define AR5312_REVISION_MAJ_AR5312 0x4 162 #define AR5312_REVISION_MAJ_AR2313 0x5 163 #define AR5312_REVISION_MAJ_AR5315 0xB 164 165 /* 166 * SDRAMCTL registers -- offset relative to SDRAMCTL 167 */ 168 #define AR5312_SDRAMCTL_MEM_CFG0 0x0000 169 #define AR5312_SDRAMCTL_MEM_CFG1 0x0004 170 171 /* memory config 1 bits */ 172 #define AR5312_MEM_CFG1_BANK0_MASK 0x00000700 173 #define AR5312_MEM_CFG1_BANK0_SHIFT 8 174 #define AR5312_MEM_CFG1_BANK1_MASK 0x00007000 175 #define AR5312_MEM_CFG1_BANK1_SHIFT 12 176 177 /* helper macro for accessing system registers without bus space */ 178 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 179 #define GETSYSREG(x) REGVAL((x) + AR5312_SYSREG_BASE) 180 #define PUTSYSREG(x,v) (REGVAL((x) + AR5312_SYSREG_BASE)) = (v) 181 #define GETSDRAMREG(x) REGVAL((x) + AR5312_SDRAMCTL_BASE) 182 #define PUTSDRAMREG(x,v) (REGVAL((x) + AR5312_SDRAMCTL_BASE)) = (v) 183 184 /* 185 * Board data. This is located in flash somewhere, ar531x_board_info 186 * locates it. 187 */ 188 #include <contrib/dev/ath/ah_soc.h> /* XXX really doesn't belong in hal */ 189 190 /* XXX write-around for now */ 191 #define AR5312_BOARD_MAGIC AR531X_BD_MAGIC 192 193 /* config bits */ 194 #define AR5312_BOARD_CONFIG_ENET0 BD_ENET0 195 #define AR5312_BOARD_CONFIG_ENET1 BD_ENET1 196 #define AR5312_BOARD_CONFIG_UART1 BD_UART1 197 #define AR5312_BOARD_CONFIG_UART0 BD_UART0 198 #define AR5312_BOARD_CONFIG_RSTFACTORY BD_RSTFACTORY 199 #define AR5312_BOARD_CONFIG_SYSLED BD_SYSLED 200 #define AR5312_BOARD_CONFIG_EXTUARTCLK BD_EXTUARTCLK 201 #define AR5312_BOARD_CONFIG_CPUFREQ BD_CPUFREQ 202 #define AR5312_BOARD_CONFIG_SYSFREQ BD_SYSFREQ 203 #define AR5312_BOARD_CONFIG_WLAN0 BD_WLAN0 204 #define AR5312_BOARD_CONFIG_MEMCAP BD_MEMCAP 205 #define AR5312_BOARD_CONFIG_DISWDOG BD_DISWATCHDOG 206 #define AR5312_BOARD_CONFIG_WLAN1 BD_WLAN1 207 #define AR5312_BOARD_CONFIG_AR2312 BD_ISCASPER 208 #define AR5312_BOARD_CONFIG_WLAN0_2G BD_WLAN0_2G_EN 209 #define AR5312_BOARD_CONFIG_WLAN0_5G BD_WLAN0_5G_EN 210 #define AR5312_BOARD_CONFIG_WLAN1_2G BD_WLAN1_2G_EN 211 #define AR5312_BOARD_CONFIG_WLAN1_5G BD_WLAN1_5G_EN 212 213 #endif /* _MIPS_ATHEROS_AR531XREG_H_ */ 214
Indexes created Wed Oct 01 13:09:50 GMT 2025