if_cnmac.c revision 1.9 1 1.9 msaitoh /* $NetBSD: if_cnmac.c,v 1.9 2018/06/26 06:47:58 msaitoh Exp $ */
2 1.1 hikaru
3 1.1 hikaru #include <sys/cdefs.h>
4 1.1 hikaru #if 0
5 1.9 msaitoh __KERNEL_RCSID(0, "$NetBSD: if_cnmac.c,v 1.9 2018/06/26 06:47:58 msaitoh Exp $");
6 1.1 hikaru #endif
7 1.1 hikaru
8 1.1 hikaru #include "opt_octeon.h"
9 1.1 hikaru
10 1.1 hikaru #ifdef OCTEON_ETH_DEBUG
11 1.1 hikaru
12 1.1 hikaru #ifndef DIAGNOSTIC
13 1.1 hikaru #define DIAGNOSTIC
14 1.1 hikaru #endif
15 1.1 hikaru
16 1.1 hikaru #ifndef DEBUG
17 1.1 hikaru #define DEBUG
18 1.1 hikaru #endif
19 1.1 hikaru
20 1.1 hikaru #endif
21 1.1 hikaru
22 1.1 hikaru /*
23 1.1 hikaru * If no free send buffer is available, free all the sent buffer and bail out.
24 1.1 hikaru */
25 1.1 hikaru #define OCTEON_ETH_SEND_QUEUE_CHECK
26 1.1 hikaru
27 1.1 hikaru /* XXX XXX XXX XXX XXX XXX */
28 1.1 hikaru
29 1.1 hikaru #include <sys/param.h>
30 1.1 hikaru #include <sys/systm.h>
31 1.1 hikaru #include <sys/pool.h>
32 1.1 hikaru #include <sys/mbuf.h>
33 1.1 hikaru #include <sys/malloc.h>
34 1.1 hikaru #include <sys/kernel.h>
35 1.1 hikaru #include <sys/socket.h>
36 1.1 hikaru #include <sys/ioctl.h>
37 1.1 hikaru #include <sys/errno.h>
38 1.1 hikaru #include <sys/device.h>
39 1.1 hikaru #include <sys/queue.h>
40 1.1 hikaru #include <sys/conf.h>
41 1.1 hikaru #include <sys/sysctl.h>
42 1.1 hikaru #include <sys/syslog.h>
43 1.1 hikaru
44 1.1 hikaru #include <net/if.h>
45 1.1 hikaru #include <net/if_dl.h>
46 1.1 hikaru #include <net/if_media.h>
47 1.1 hikaru #include <net/if_ether.h>
48 1.1 hikaru #include <net/route.h>
49 1.1 hikaru
50 1.1 hikaru #include <net/bpf.h>
51 1.1 hikaru
52 1.1 hikaru #include <netinet/in.h>
53 1.1 hikaru #include <netinet/in_systm.h>
54 1.1 hikaru #include <netinet/in_var.h>
55 1.1 hikaru #include <netinet/ip.h>
56 1.1 hikaru
57 1.1 hikaru #include <sys/bus.h>
58 1.1 hikaru #include <machine/intr.h>
59 1.1 hikaru #include <machine/endian.h>
60 1.1 hikaru #include <machine/locore.h>
61 1.1 hikaru
62 1.1 hikaru #include <dev/mii/mii.h>
63 1.1 hikaru #include <dev/mii/miivar.h>
64 1.1 hikaru
65 1.1 hikaru #include <mips/cpuregs.h>
66 1.1 hikaru
67 1.1 hikaru #include <mips/cavium/dev/octeon_asxreg.h>
68 1.1 hikaru #include <mips/cavium/dev/octeon_ciureg.h>
69 1.1 hikaru #include <mips/cavium/dev/octeon_npireg.h>
70 1.1 hikaru #include <mips/cavium/dev/octeon_gmxreg.h>
71 1.1 hikaru #include <mips/cavium/dev/octeon_ipdreg.h>
72 1.1 hikaru #include <mips/cavium/dev/octeon_pipreg.h>
73 1.1 hikaru #include <mips/cavium/dev/octeon_powreg.h>
74 1.1 hikaru #include <mips/cavium/dev/octeon_faureg.h>
75 1.1 hikaru #include <mips/cavium/dev/octeon_fpareg.h>
76 1.1 hikaru #include <mips/cavium/dev/octeon_bootbusreg.h>
77 1.1 hikaru #include <mips/cavium/include/iobusvar.h>
78 1.1 hikaru #include <mips/cavium/octeonvar.h>
79 1.1 hikaru #include <mips/cavium/dev/octeon_fpavar.h>
80 1.1 hikaru #include <mips/cavium/dev/octeon_gmxvar.h>
81 1.1 hikaru #include <mips/cavium/dev/octeon_fauvar.h>
82 1.1 hikaru #include <mips/cavium/dev/octeon_powvar.h>
83 1.1 hikaru #include <mips/cavium/dev/octeon_ipdvar.h>
84 1.1 hikaru #include <mips/cavium/dev/octeon_pipvar.h>
85 1.1 hikaru #include <mips/cavium/dev/octeon_pkovar.h>
86 1.1 hikaru #include <mips/cavium/dev/octeon_asxvar.h>
87 1.1 hikaru #include <mips/cavium/dev/octeon_smivar.h>
88 1.1 hikaru #include <mips/cavium/dev/if_cnmacvar.h>
89 1.1 hikaru
90 1.1 hikaru #ifdef OCTEON_ETH_DEBUG
91 1.1 hikaru #define OCTEON_ETH_KASSERT(x) KASSERT(x)
92 1.1 hikaru #define OCTEON_ETH_KDASSERT(x) KDASSERT(x)
93 1.1 hikaru #else
94 1.1 hikaru #define OCTEON_ETH_KASSERT(x)
95 1.1 hikaru #define OCTEON_ETH_KDASSERT(x)
96 1.1 hikaru #endif
97 1.1 hikaru
98 1.1 hikaru /*
99 1.1 hikaru * Set the PKO to think command buffers are an odd length. This makes it so we
100 1.1 hikaru * never have to divide a comamnd across two buffers.
101 1.1 hikaru */
102 1.1 hikaru #define OCTEON_POOL_NWORDS_CMD \
103 1.1 hikaru (((uint32_t)OCTEON_POOL_SIZE_CMD / sizeof(uint64_t)) - 1)
104 1.1 hikaru #define FPA_COMMAND_BUFFER_POOL_NWORDS OCTEON_POOL_NWORDS_CMD /* XXX */
105 1.1 hikaru
106 1.1 hikaru static void octeon_eth_buf_init(struct octeon_eth_softc *);
107 1.1 hikaru
108 1.1 hikaru static int octeon_eth_match(device_t, struct cfdata *, void *);
109 1.1 hikaru static void octeon_eth_attach(device_t, device_t, void *);
110 1.1 hikaru static void octeon_eth_pip_init(struct octeon_eth_softc *);
111 1.1 hikaru static void octeon_eth_ipd_init(struct octeon_eth_softc *);
112 1.1 hikaru static void octeon_eth_pko_init(struct octeon_eth_softc *);
113 1.1 hikaru static void octeon_eth_asx_init(struct octeon_eth_softc *);
114 1.1 hikaru static void octeon_eth_smi_init(struct octeon_eth_softc *);
115 1.1 hikaru
116 1.1 hikaru static void octeon_eth_board_mac_addr(uint8_t *, size_t, struct octeon_eth_softc *);
117 1.1 hikaru
118 1.1 hikaru static int octeon_eth_mii_readreg(device_t, int, int);
119 1.1 hikaru static void octeon_eth_mii_writereg(device_t, int, int, int);
120 1.1 hikaru static void octeon_eth_mii_statchg(struct ifnet *);
121 1.1 hikaru
122 1.1 hikaru static int octeon_eth_mediainit(struct octeon_eth_softc *);
123 1.1 hikaru static void octeon_eth_mediastatus(struct ifnet *, struct ifmediareq *);
124 1.1 hikaru static int octeon_eth_mediachange(struct ifnet *);
125 1.1 hikaru
126 1.1 hikaru static inline void octeon_eth_send_queue_flush_prefetch(struct octeon_eth_softc *);
127 1.1 hikaru static inline void octeon_eth_send_queue_flush_fetch(struct octeon_eth_softc *);
128 1.1 hikaru static inline void octeon_eth_send_queue_flush(struct octeon_eth_softc *);
129 1.1 hikaru static inline void octeon_eth_send_queue_flush_sync(struct octeon_eth_softc *);
130 1.1 hikaru static inline int octeon_eth_send_queue_is_full(struct octeon_eth_softc *);
131 1.1 hikaru static inline void octeon_eth_send_queue_add(struct octeon_eth_softc *,
132 1.1 hikaru struct mbuf *, uint64_t *);
133 1.1 hikaru static inline void octeon_eth_send_queue_del(struct octeon_eth_softc *,
134 1.1 hikaru struct mbuf **, uint64_t **);
135 1.1 hikaru static inline int octeon_eth_buf_free_work(struct octeon_eth_softc *,
136 1.1 hikaru uint64_t *, uint64_t);
137 1.1 hikaru static inline void octeon_eth_buf_ext_free_m(struct mbuf *, void *, size_t, void *);
138 1.1 hikaru static inline void octeon_eth_buf_ext_free_ext(struct mbuf *, void *, size_t, void *);
139 1.1 hikaru
140 1.1 hikaru static int octeon_eth_ioctl(struct ifnet *, u_long, void *);
141 1.1 hikaru static void octeon_eth_watchdog(struct ifnet *);
142 1.1 hikaru static int octeon_eth_init(struct ifnet *);
143 1.1 hikaru static void octeon_eth_stop(struct ifnet *, int);
144 1.1 hikaru static void octeon_eth_start(struct ifnet *);
145 1.1 hikaru
146 1.1 hikaru static inline int octeon_eth_send_cmd(struct octeon_eth_softc *, uint64_t,
147 1.8 jmcneill uint64_t, int *);
148 1.1 hikaru static inline uint64_t octeon_eth_send_makecmd_w1(int, paddr_t);
149 1.1 hikaru static inline uint64_t octeon_eth_send_makecmd_w0(uint64_t, uint64_t, size_t,
150 1.1 hikaru int);
151 1.1 hikaru static inline int octeon_eth_send_makecmd_gbuf(struct octeon_eth_softc *,
152 1.1 hikaru struct mbuf *, uint64_t *, int *);
153 1.1 hikaru static inline int octeon_eth_send_makecmd(struct octeon_eth_softc *,
154 1.1 hikaru struct mbuf *, uint64_t *, uint64_t *, uint64_t *);
155 1.1 hikaru static inline int octeon_eth_send_buf(struct octeon_eth_softc *,
156 1.8 jmcneill struct mbuf *, uint64_t *, int *);
157 1.1 hikaru static inline int octeon_eth_send(struct octeon_eth_softc *,
158 1.8 jmcneill struct mbuf *, int *);
159 1.1 hikaru
160 1.1 hikaru static int octeon_eth_reset(struct octeon_eth_softc *);
161 1.1 hikaru static int octeon_eth_configure(struct octeon_eth_softc *);
162 1.1 hikaru static int octeon_eth_configure_common(struct octeon_eth_softc *);
163 1.1 hikaru
164 1.1 hikaru static void octeon_eth_tick_free(void *arg);
165 1.1 hikaru static void octeon_eth_tick_misc(void *);
166 1.1 hikaru
167 1.1 hikaru static inline int octeon_eth_recv_mbuf(struct octeon_eth_softc *,
168 1.1 hikaru uint64_t *, struct mbuf **);
169 1.1 hikaru static inline int octeon_eth_recv_check_code(struct octeon_eth_softc *,
170 1.1 hikaru uint64_t);
171 1.1 hikaru static inline int octeon_eth_recv_check_jumbo(struct octeon_eth_softc *,
172 1.1 hikaru uint64_t);
173 1.1 hikaru static inline int octeon_eth_recv_check_link(struct octeon_eth_softc *,
174 1.1 hikaru uint64_t);
175 1.1 hikaru static inline int octeon_eth_recv_check(struct octeon_eth_softc *,
176 1.1 hikaru uint64_t);
177 1.1 hikaru static inline int octeon_eth_recv(struct octeon_eth_softc *, uint64_t *);
178 1.1 hikaru static void octeon_eth_recv_redir(struct ifnet *, struct mbuf *);
179 1.1 hikaru static inline void octeon_eth_recv_intr(void *, uint64_t *);
180 1.1 hikaru
181 1.1 hikaru /* device driver context */
182 1.1 hikaru static struct octeon_eth_softc *octeon_eth_gsc[GMX_PORT_NUNITS];
183 1.1 hikaru static void *octeon_eth_pow_recv_ih;
184 1.1 hikaru
185 1.1 hikaru /* sysctl'able parameters */
186 1.1 hikaru int octeon_eth_param_pko_cmd_w0_n2 = 1;
187 1.1 hikaru int octeon_eth_param_pip_dyn_rs = 1;
188 1.1 hikaru int octeon_eth_param_redir = 0;
189 1.1 hikaru int octeon_eth_param_pktbuf = 0;
190 1.1 hikaru int octeon_eth_param_rate = 0;
191 1.1 hikaru int octeon_eth_param_intr = 0;
192 1.1 hikaru
193 1.1 hikaru CFATTACH_DECL_NEW(cnmac, sizeof(struct octeon_eth_softc),
194 1.1 hikaru octeon_eth_match, octeon_eth_attach, NULL, NULL);
195 1.1 hikaru
196 1.1 hikaru #ifdef OCTEON_ETH_DEBUG
197 1.1 hikaru
198 1.1 hikaru static const struct octeon_evcnt_entry octeon_evcnt_entries[] = {
199 1.1 hikaru #define _ENTRY(name, type, parent, descr) \
200 1.1 hikaru OCTEON_EVCNT_ENTRY(struct octeon_eth_softc, name, type, parent, descr)
201 1.1 hikaru _ENTRY(rx, MISC, NULL, "rx"),
202 1.1 hikaru _ENTRY(rxint, INTR, NULL, "rx intr"),
203 1.1 hikaru _ENTRY(rxrs, MISC, NULL, "rx dynamic short"),
204 1.1 hikaru _ENTRY(rxbufpkalloc, MISC, NULL, "rx buf pkt alloc"),
205 1.1 hikaru _ENTRY(rxbufpkput, MISC, NULL, "rx buf pkt put"),
206 1.1 hikaru _ENTRY(rxbufwqalloc, MISC, NULL, "rx buf wqe alloc"),
207 1.1 hikaru _ENTRY(rxbufwqput, MISC, NULL, "rx buf wqe put"),
208 1.1 hikaru _ENTRY(rxerrcode, MISC, NULL, "rx code error"),
209 1.1 hikaru _ENTRY(rxerrfix, MISC, NULL, "rx fixup error"),
210 1.1 hikaru _ENTRY(rxerrjmb, MISC, NULL, "rx jmb error"),
211 1.1 hikaru _ENTRY(rxerrlink, MISC, NULL, "rx link error"),
212 1.1 hikaru _ENTRY(rxerroff, MISC, NULL, "rx offload error"),
213 1.1 hikaru _ENTRY(rxonperrshort, MISC, NULL, "rx onp fixup short error"),
214 1.1 hikaru _ENTRY(rxonperrpreamble, MISC, NULL, "rx onp fixup preamble error"),
215 1.1 hikaru _ENTRY(rxonperrcrc, MISC, NULL, "rx onp fixup crc error"),
216 1.1 hikaru _ENTRY(rxonperraddress, MISC, NULL, "rx onp fixup address error"),
217 1.1 hikaru _ENTRY(rxonponp, MISC, NULL, "rx onp fixup onp packets"),
218 1.1 hikaru _ENTRY(rxonpok, MISC, NULL, "rx onp fixup success packets"),
219 1.1 hikaru _ENTRY(tx, MISC, NULL, "tx"),
220 1.1 hikaru _ENTRY(txadd, MISC, NULL, "tx add"),
221 1.1 hikaru _ENTRY(txbufcballoc, MISC, NULL, "tx buf cb alloc"),
222 1.1 hikaru _ENTRY(txbufcbget, MISC, NULL, "tx buf cb get"),
223 1.1 hikaru _ENTRY(txbufgballoc, MISC, NULL, "tx buf gb alloc"),
224 1.1 hikaru _ENTRY(txbufgbget, MISC, NULL, "tx buf gb get"),
225 1.1 hikaru _ENTRY(txbufgbput, MISC, NULL, "tx buf gb put"),
226 1.1 hikaru _ENTRY(txdel, MISC, NULL, "tx del"),
227 1.1 hikaru _ENTRY(txerr, MISC, NULL, "tx error"),
228 1.1 hikaru _ENTRY(txerrcmd, MISC, NULL, "tx cmd error"),
229 1.1 hikaru _ENTRY(txerrgbuf, MISC, NULL, "tx gbuf error"),
230 1.1 hikaru _ENTRY(txerrlink, MISC, NULL, "tx link error"),
231 1.1 hikaru _ENTRY(txerrmkcmd, MISC, NULL, "tx makecmd error"),
232 1.1 hikaru #undef _ENTRY
233 1.1 hikaru };
234 1.1 hikaru #endif
235 1.1 hikaru
236 1.1 hikaru /* ---- buffer management */
237 1.1 hikaru
238 1.1 hikaru static const struct octeon_eth_pool_param {
239 1.1 hikaru int poolno;
240 1.1 hikaru size_t size;
241 1.1 hikaru size_t nelems;
242 1.1 hikaru } octeon_eth_pool_params[] = {
243 1.1 hikaru #define _ENTRY(x) { OCTEON_POOL_NO_##x, OCTEON_POOL_SIZE_##x, OCTEON_POOL_NELEMS_##x }
244 1.1 hikaru _ENTRY(PKT),
245 1.1 hikaru _ENTRY(WQE),
246 1.1 hikaru _ENTRY(CMD),
247 1.1 hikaru _ENTRY(SG)
248 1.1 hikaru #undef _ENTRY
249 1.1 hikaru };
250 1.1 hikaru struct octeon_fpa_buf *octeon_eth_pools[8/* XXX */];
251 1.1 hikaru #define octeon_eth_fb_pkt octeon_eth_pools[OCTEON_POOL_NO_PKT]
252 1.1 hikaru #define octeon_eth_fb_wqe octeon_eth_pools[OCTEON_POOL_NO_WQE]
253 1.1 hikaru #define octeon_eth_fb_cmd octeon_eth_pools[OCTEON_POOL_NO_CMD]
254 1.1 hikaru #define octeon_eth_fb_sg octeon_eth_pools[OCTEON_POOL_NO_SG]
255 1.1 hikaru
256 1.1 hikaru static void
257 1.1 hikaru octeon_eth_buf_init(struct octeon_eth_softc *sc)
258 1.1 hikaru {
259 1.1 hikaru static int once;
260 1.1 hikaru int i;
261 1.1 hikaru const struct octeon_eth_pool_param *pp;
262 1.1 hikaru struct octeon_fpa_buf *fb;
263 1.1 hikaru
264 1.1 hikaru if (once == 1)
265 1.1 hikaru return;
266 1.1 hikaru once = 1;
267 1.1 hikaru
268 1.1 hikaru for (i = 0; i < (int)__arraycount(octeon_eth_pool_params); i++) {
269 1.1 hikaru pp = &octeon_eth_pool_params[i];
270 1.1 hikaru octeon_fpa_buf_init(pp->poolno, pp->size, pp->nelems, &fb);
271 1.1 hikaru octeon_eth_pools[i] = fb;
272 1.1 hikaru }
273 1.1 hikaru }
274 1.1 hikaru
275 1.1 hikaru /* ---- autoconf */
276 1.1 hikaru
277 1.1 hikaru static int
278 1.1 hikaru octeon_eth_match(device_t parent, struct cfdata *match, void *aux)
279 1.1 hikaru {
280 1.1 hikaru struct octeon_gmx_attach_args *ga = aux;
281 1.1 hikaru
282 1.1 hikaru if (strcmp(match->cf_name, ga->ga_name) != 0) {
283 1.1 hikaru return 0;
284 1.1 hikaru }
285 1.1 hikaru return 1;
286 1.1 hikaru }
287 1.1 hikaru
288 1.1 hikaru static void
289 1.1 hikaru octeon_eth_attach(device_t parent, device_t self, void *aux)
290 1.1 hikaru {
291 1.1 hikaru struct octeon_eth_softc *sc = device_private(self);
292 1.1 hikaru struct octeon_gmx_attach_args *ga = aux;
293 1.1 hikaru struct ifnet *ifp = &sc->sc_ethercom.ec_if;
294 1.1 hikaru uint8_t enaddr[ETHER_ADDR_LEN];
295 1.1 hikaru
296 1.1 hikaru sc->sc_dev = self;
297 1.1 hikaru sc->sc_regt = ga->ga_regt;
298 1.1 hikaru sc->sc_port = ga->ga_portno;
299 1.1 hikaru sc->sc_port_type = ga->ga_port_type;
300 1.1 hikaru sc->sc_gmx = ga->ga_gmx;
301 1.1 hikaru sc->sc_gmx_port = ga->ga_gmx_port;
302 1.1 hikaru
303 1.1 hikaru sc->sc_init_flag = 0;
304 1.1 hikaru /*
305 1.1 hikaru * XXXUEBAYASI
306 1.1 hikaru * Setting PIP_IP_OFFSET[OFFSET] to 8 causes panic ... why???
307 1.1 hikaru */
308 1.1 hikaru sc->sc_ip_offset = 0/* XXX */;
309 1.1 hikaru
310 1.1 hikaru if (MIPS_PRID_IMPL(mips_options.mips_cpu_id) <= MIPS_CN30XX) {
311 1.1 hikaru SET(sc->sc_quirks, OCTEON_ETH_QUIRKS_NO_PRE_ALIGN);
312 1.1 hikaru SET(sc->sc_quirks, OCTEON_ETH_QUIRKS_NO_RX_INBND);
313 1.1 hikaru }
314 1.1 hikaru
315 1.1 hikaru octeon_eth_board_mac_addr(enaddr, sizeof(enaddr), sc);
316 1.1 hikaru printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev),
317 1.1 hikaru ether_sprintf(enaddr));
318 1.1 hikaru
319 1.1 hikaru octeon_eth_gsc[sc->sc_port] = sc;
320 1.1 hikaru
321 1.1 hikaru SIMPLEQ_INIT(&sc->sc_sendq);
322 1.1 hikaru sc->sc_soft_req_thresh = 15/* XXX */;
323 1.1 hikaru sc->sc_ext_callback_cnt = 0;
324 1.1 hikaru
325 1.1 hikaru octeon_gmx_stats_init(sc->sc_gmx_port);
326 1.1 hikaru
327 1.1 hikaru callout_init(&sc->sc_tick_misc_ch, 0);
328 1.1 hikaru callout_init(&sc->sc_tick_free_ch, 0);
329 1.1 hikaru
330 1.1 hikaru octeon_fau_op_init(&sc->sc_fau_done,
331 1.1 hikaru OCTEON_CVMSEG_ETHER_OFFSET(sc->sc_port, csm_ether_fau_done),
332 1.1 hikaru OCT_FAU_REG_ADDR_END - (8 * (sc->sc_port + 1))/* XXX */);
333 1.1 hikaru octeon_fau_op_set_8(&sc->sc_fau_done, 0);
334 1.1 hikaru
335 1.1 hikaru octeon_eth_pip_init(sc);
336 1.1 hikaru octeon_eth_ipd_init(sc);
337 1.1 hikaru octeon_eth_pko_init(sc);
338 1.1 hikaru octeon_eth_asx_init(sc);
339 1.1 hikaru octeon_eth_smi_init(sc);
340 1.1 hikaru
341 1.1 hikaru sc->sc_gmx_port->sc_ipd = sc->sc_ipd;
342 1.1 hikaru sc->sc_gmx_port->sc_port_asx = sc->sc_asx;
343 1.1 hikaru sc->sc_gmx_port->sc_port_mii = &sc->sc_mii;
344 1.1 hikaru sc->sc_gmx_port->sc_port_ec = &sc->sc_ethercom;
345 1.1 hikaru /* XXX */
346 1.1 hikaru sc->sc_gmx_port->sc_quirks = sc->sc_quirks;
347 1.1 hikaru
348 1.1 hikaru /* XXX */
349 1.1 hikaru sc->sc_pow = &octeon_pow_softc;
350 1.1 hikaru
351 1.1 hikaru octeon_eth_mediainit(sc);
352 1.1 hikaru
353 1.1 hikaru strncpy(ifp->if_xname, device_xname(sc->sc_dev), sizeof(ifp->if_xname));
354 1.1 hikaru ifp->if_softc = sc;
355 1.1 hikaru ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
356 1.1 hikaru ifp->if_ioctl = octeon_eth_ioctl;
357 1.1 hikaru ifp->if_start = octeon_eth_start;
358 1.1 hikaru ifp->if_watchdog = octeon_eth_watchdog;
359 1.1 hikaru ifp->if_init = octeon_eth_init;
360 1.1 hikaru ifp->if_stop = octeon_eth_stop;
361 1.1 hikaru IFQ_SET_MAXLEN(&ifp->if_snd, max(GATHER_QUEUE_SIZE, IFQ_MAXLEN));
362 1.1 hikaru IFQ_SET_READY(&ifp->if_snd);
363 1.1 hikaru
364 1.1 hikaru /* XXX: not yet tx checksum */
365 1.1 hikaru ifp->if_capabilities =
366 1.1 hikaru IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
367 1.1 hikaru IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
368 1.1 hikaru
369 1.7 jmcneill /* 802.1Q VLAN-sized frames are supported */
370 1.7 jmcneill sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
371 1.7 jmcneill
372 1.1 hikaru octeon_gmx_set_mac_addr(sc->sc_gmx_port, enaddr);
373 1.1 hikaru octeon_gmx_set_filter(sc->sc_gmx_port);
374 1.1 hikaru
375 1.1 hikaru if_attach(ifp);
376 1.1 hikaru ether_ifattach(ifp, enaddr);
377 1.1 hikaru
378 1.1 hikaru /* XXX */
379 1.1 hikaru sc->sc_rate_recv_check_link_cap.tv_sec = 1;
380 1.1 hikaru sc->sc_rate_recv_check_jumbo_cap.tv_sec = 1;
381 1.1 hikaru sc->sc_rate_recv_check_code_cap.tv_sec = 1;
382 1.1 hikaru sc->sc_rate_recv_fixup_odd_nibble_short_cap.tv_sec = 1;
383 1.1 hikaru sc->sc_rate_recv_fixup_odd_nibble_preamble_cap.tv_sec = 1;
384 1.1 hikaru sc->sc_rate_recv_fixup_odd_nibble_crc_cap.tv_sec = 1;
385 1.1 hikaru #ifdef OCTEON_ETH_DEBUG
386 1.1 hikaru sc->sc_rate_recv_fixup_odd_nibble_addr_cap.tv_sec = 1;
387 1.1 hikaru #endif
388 1.1 hikaru /* XXX */
389 1.1 hikaru
390 1.1 hikaru #if 1
391 1.1 hikaru octeon_eth_buf_init(sc);
392 1.1 hikaru #endif
393 1.1 hikaru
394 1.1 hikaru if (octeon_eth_pow_recv_ih == NULL)
395 1.1 hikaru octeon_eth_pow_recv_ih = octeon_pow_intr_establish(OCTEON_POW_GROUP_PIP,
396 1.1 hikaru IPL_NET, octeon_eth_recv_intr, NULL, NULL);
397 1.1 hikaru
398 1.1 hikaru OCTEON_EVCNT_ATTACH_EVCNTS(sc, octeon_evcnt_entries,
399 1.1 hikaru device_xname(sc->sc_dev));
400 1.1 hikaru }
401 1.1 hikaru
402 1.1 hikaru /* ---- submodules */
403 1.1 hikaru
404 1.1 hikaru /* XXX */
405 1.1 hikaru static void
406 1.1 hikaru octeon_eth_pip_init(struct octeon_eth_softc *sc)
407 1.1 hikaru {
408 1.1 hikaru struct octeon_pip_attach_args pip_aa;
409 1.1 hikaru
410 1.1 hikaru pip_aa.aa_port = sc->sc_port;
411 1.1 hikaru pip_aa.aa_regt = sc->sc_regt;
412 1.1 hikaru pip_aa.aa_tag_type = POW_TAG_TYPE_ORDERED/* XXX */;
413 1.1 hikaru pip_aa.aa_receive_group = OCTEON_POW_GROUP_PIP;
414 1.1 hikaru pip_aa.aa_ip_offset = sc->sc_ip_offset;
415 1.1 hikaru octeon_pip_init(&pip_aa, &sc->sc_pip);
416 1.1 hikaru }
417 1.1 hikaru
418 1.1 hikaru /* XXX */
419 1.1 hikaru static void
420 1.1 hikaru octeon_eth_ipd_init(struct octeon_eth_softc *sc)
421 1.1 hikaru {
422 1.1 hikaru struct octeon_ipd_attach_args ipd_aa;
423 1.1 hikaru
424 1.1 hikaru ipd_aa.aa_port = sc->sc_port;
425 1.1 hikaru ipd_aa.aa_regt = sc->sc_regt;
426 1.1 hikaru ipd_aa.aa_first_mbuff_skip = 184/* XXX */;
427 1.1 hikaru ipd_aa.aa_not_first_mbuff_skip = 0/* XXX */;
428 1.1 hikaru octeon_ipd_init(&ipd_aa, &sc->sc_ipd);
429 1.1 hikaru }
430 1.1 hikaru
431 1.1 hikaru /* XXX */
432 1.1 hikaru static void
433 1.1 hikaru octeon_eth_pko_init(struct octeon_eth_softc *sc)
434 1.1 hikaru {
435 1.1 hikaru struct octeon_pko_attach_args pko_aa;
436 1.1 hikaru
437 1.1 hikaru pko_aa.aa_port = sc->sc_port;
438 1.1 hikaru pko_aa.aa_regt = sc->sc_regt;
439 1.1 hikaru pko_aa.aa_cmdptr = &sc->sc_cmdptr;
440 1.1 hikaru pko_aa.aa_cmd_buf_pool = OCTEON_POOL_NO_CMD;
441 1.1 hikaru pko_aa.aa_cmd_buf_size = OCTEON_POOL_NWORDS_CMD;
442 1.1 hikaru octeon_pko_init(&pko_aa, &sc->sc_pko);
443 1.1 hikaru }
444 1.1 hikaru
445 1.1 hikaru /* XXX */
446 1.1 hikaru static void
447 1.1 hikaru octeon_eth_asx_init(struct octeon_eth_softc *sc)
448 1.1 hikaru {
449 1.1 hikaru struct octeon_asx_attach_args asx_aa;
450 1.1 hikaru
451 1.1 hikaru asx_aa.aa_port = sc->sc_port;
452 1.1 hikaru asx_aa.aa_regt = sc->sc_regt;
453 1.1 hikaru octeon_asx_init(&asx_aa, &sc->sc_asx);
454 1.1 hikaru }
455 1.1 hikaru
456 1.1 hikaru static void
457 1.1 hikaru octeon_eth_smi_init(struct octeon_eth_softc *sc)
458 1.1 hikaru {
459 1.1 hikaru struct octeon_smi_attach_args smi_aa;
460 1.1 hikaru
461 1.1 hikaru smi_aa.aa_port = sc->sc_port;
462 1.1 hikaru smi_aa.aa_regt = sc->sc_regt;
463 1.1 hikaru octeon_smi_init(&smi_aa, &sc->sc_smi);
464 1.1 hikaru octeon_smi_set_clock(sc->sc_smi, 0x1464ULL); /* XXX */
465 1.1 hikaru }
466 1.1 hikaru
467 1.1 hikaru /* ---- XXX */
468 1.1 hikaru
469 1.1 hikaru #define ADDR2UINT64(u, a) \
470 1.1 hikaru do { \
471 1.1 hikaru u = \
472 1.1 hikaru (((uint64_t)a[0] << 40) | ((uint64_t)a[1] << 32) | \
473 1.1 hikaru ((uint64_t)a[2] << 24) | ((uint64_t)a[3] << 16) | \
474 1.1 hikaru ((uint64_t)a[4] << 8) | ((uint64_t)a[5] << 0)); \
475 1.1 hikaru } while (0)
476 1.1 hikaru #define UINT642ADDR(a, u) \
477 1.1 hikaru do { \
478 1.1 hikaru a[0] = (uint8_t)((u) >> 40); a[1] = (uint8_t)((u) >> 32); \
479 1.1 hikaru a[2] = (uint8_t)((u) >> 24); a[3] = (uint8_t)((u) >> 16); \
480 1.1 hikaru a[4] = (uint8_t)((u) >> 8); a[5] = (uint8_t)((u) >> 0); \
481 1.1 hikaru } while (0)
482 1.1 hikaru
483 1.1 hikaru static void
484 1.1 hikaru octeon_eth_board_mac_addr(uint8_t *enaddr, size_t size, struct octeon_eth_softc *sc)
485 1.1 hikaru {
486 1.1 hikaru prop_dictionary_t dict;
487 1.1 hikaru prop_data_t ea;
488 1.1 hikaru
489 1.1 hikaru dict = device_properties(sc->sc_dev);
490 1.1 hikaru KASSERT(dict != NULL);
491 1.1 hikaru ea = prop_dictionary_get(dict, "mac-address");
492 1.1 hikaru KASSERT(ea != NULL);
493 1.1 hikaru memcpy(enaddr, prop_data_data_nocopy(ea), size);
494 1.1 hikaru }
495 1.1 hikaru
496 1.1 hikaru /* ---- media */
497 1.1 hikaru
498 1.1 hikaru static int
499 1.1 hikaru octeon_eth_mii_readreg(device_t self, int phy_addr, int reg)
500 1.1 hikaru {
501 1.1 hikaru struct octeon_eth_softc *sc = device_private(self);
502 1.1 hikaru
503 1.1 hikaru return octeon_smi_read(sc->sc_smi, phy_addr, reg);
504 1.1 hikaru }
505 1.1 hikaru
506 1.1 hikaru static void
507 1.1 hikaru octeon_eth_mii_writereg(device_t self, int phy_addr, int reg, int value)
508 1.1 hikaru {
509 1.1 hikaru struct octeon_eth_softc *sc = device_private(self);
510 1.1 hikaru
511 1.1 hikaru octeon_smi_write(sc->sc_smi, phy_addr, reg, value);
512 1.1 hikaru }
513 1.1 hikaru
514 1.1 hikaru static void
515 1.1 hikaru octeon_eth_mii_statchg(struct ifnet *ifp)
516 1.1 hikaru {
517 1.1 hikaru struct octeon_eth_softc *sc = ifp->if_softc;
518 1.1 hikaru
519 1.1 hikaru octeon_pko_port_enable(sc->sc_pko, 0);
520 1.1 hikaru octeon_gmx_port_enable(sc->sc_gmx_port, 0);
521 1.1 hikaru
522 1.1 hikaru octeon_eth_reset(sc);
523 1.1 hikaru
524 1.1 hikaru if (ISSET(ifp->if_flags, IFF_RUNNING))
525 1.1 hikaru octeon_gmx_set_filter(sc->sc_gmx_port);
526 1.1 hikaru
527 1.1 hikaru octeon_pko_port_enable(sc->sc_pko, 1);
528 1.1 hikaru octeon_gmx_port_enable(sc->sc_gmx_port, 1);
529 1.1 hikaru }
530 1.1 hikaru
531 1.1 hikaru static int
532 1.1 hikaru octeon_eth_mediainit(struct octeon_eth_softc *sc)
533 1.1 hikaru {
534 1.1 hikaru struct ifnet *ifp = &sc->sc_ethercom.ec_if;
535 1.1 hikaru prop_object_t phy;
536 1.1 hikaru
537 1.1 hikaru sc->sc_mii.mii_ifp = ifp;
538 1.1 hikaru sc->sc_mii.mii_readreg = octeon_eth_mii_readreg;
539 1.1 hikaru sc->sc_mii.mii_writereg = octeon_eth_mii_writereg;
540 1.1 hikaru sc->sc_mii.mii_statchg = octeon_eth_mii_statchg;
541 1.1 hikaru ifmedia_init(&sc->sc_mii.mii_media, 0, octeon_eth_mediachange,
542 1.1 hikaru octeon_eth_mediastatus);
543 1.1 hikaru
544 1.1 hikaru phy = prop_dictionary_get(device_properties(sc->sc_dev), "phy-addr");
545 1.1 hikaru KASSERT(phy != NULL);
546 1.1 hikaru
547 1.1 hikaru mii_attach(sc->sc_dev, &sc->sc_mii,
548 1.1 hikaru 0xffffffff, prop_number_integer_value(phy),
549 1.1 hikaru MII_OFFSET_ANY, MIIF_DOPAUSE);
550 1.1 hikaru
551 1.1 hikaru /* XXX XXX XXX */
552 1.1 hikaru if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL) {
553 1.1 hikaru /* XXX XXX XXX */
554 1.1 hikaru ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
555 1.1 hikaru /* XXX XXX XXX */
556 1.1 hikaru } else {
557 1.1 hikaru /* XXX XXX XXX */
558 1.1 hikaru ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE,
559 1.1 hikaru MII_MEDIA_NONE, NULL);
560 1.1 hikaru /* XXX XXX XXX */
561 1.1 hikaru ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE);
562 1.1 hikaru /* XXX XXX XXX */
563 1.1 hikaru }
564 1.1 hikaru /* XXX XXX XXX */
565 1.1 hikaru
566 1.1 hikaru return 0;
567 1.1 hikaru }
568 1.1 hikaru
569 1.1 hikaru static void
570 1.1 hikaru octeon_eth_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
571 1.1 hikaru {
572 1.1 hikaru struct octeon_eth_softc *sc = ifp->if_softc;
573 1.1 hikaru
574 1.1 hikaru mii_pollstat(&sc->sc_mii);
575 1.1 hikaru
576 1.1 hikaru ifmr->ifm_status = sc->sc_mii.mii_media_status;
577 1.1 hikaru ifmr->ifm_active = sc->sc_mii.mii_media_active;
578 1.1 hikaru ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) |
579 1.1 hikaru sc->sc_gmx_port->sc_port_flowflags;
580 1.1 hikaru }
581 1.1 hikaru
582 1.1 hikaru static int
583 1.1 hikaru octeon_eth_mediachange(struct ifnet *ifp)
584 1.1 hikaru {
585 1.1 hikaru struct octeon_eth_softc *sc = ifp->if_softc;
586 1.1 hikaru
587 1.1 hikaru mii_mediachg(&sc->sc_mii);
588 1.1 hikaru
589 1.1 hikaru return 0;
590 1.1 hikaru }
591 1.1 hikaru
592 1.1 hikaru /* ---- send buffer garbage collection */
593 1.1 hikaru
594 1.1 hikaru static inline void
595 1.1 hikaru octeon_eth_send_queue_flush_prefetch(struct octeon_eth_softc *sc)
596 1.1 hikaru {
597 1.1 hikaru OCTEON_ETH_KASSERT(sc->sc_prefetch == 0);
598 1.1 hikaru octeon_fau_op_inc_fetch_8(&sc->sc_fau_done, 0);
599 1.1 hikaru sc->sc_prefetch = 1;
600 1.1 hikaru }
601 1.1 hikaru
602 1.1 hikaru static inline void
603 1.1 hikaru octeon_eth_send_queue_flush_fetch(struct octeon_eth_softc *sc)
604 1.1 hikaru {
605 1.1 hikaru #ifndef OCTEON_ETH_DEBUG
606 1.1 hikaru if (!sc->sc_prefetch)
607 1.1 hikaru return;
608 1.1 hikaru #endif
609 1.1 hikaru OCTEON_ETH_KASSERT(sc->sc_prefetch == 1);
610 1.1 hikaru sc->sc_hard_done_cnt = octeon_fau_op_inc_read_8(&sc->sc_fau_done);
611 1.1 hikaru OCTEON_ETH_KASSERT(sc->sc_hard_done_cnt <= 0);
612 1.1 hikaru sc->sc_prefetch = 0;
613 1.1 hikaru }
614 1.1 hikaru
615 1.1 hikaru static inline void
616 1.1 hikaru octeon_eth_send_queue_flush(struct octeon_eth_softc *sc)
617 1.1 hikaru {
618 1.8 jmcneill struct ifnet *ifp = &sc->sc_ethercom.ec_if;
619 1.1 hikaru const int64_t sent_count = sc->sc_hard_done_cnt;
620 1.1 hikaru int i;
621 1.1 hikaru
622 1.1 hikaru OCTEON_ETH_KASSERT(sc->sc_flush == 0);
623 1.1 hikaru OCTEON_ETH_KASSERT(sent_count <= 0);
624 1.1 hikaru
625 1.1 hikaru for (i = 0; i < 0 - sent_count; i++) {
626 1.1 hikaru struct mbuf *m;
627 1.1 hikaru uint64_t *gbuf;
628 1.1 hikaru
629 1.1 hikaru octeon_eth_send_queue_del(sc, &m, &gbuf);
630 1.1 hikaru
631 1.1 hikaru octeon_fpa_buf_put(octeon_eth_fb_sg, gbuf);
632 1.1 hikaru OCTEON_EVCNT_INC(sc, txbufgbput);
633 1.1 hikaru
634 1.1 hikaru m_freem(m);
635 1.8 jmcneill
636 1.8 jmcneill CLR(ifp->if_flags, IFF_OACTIVE);
637 1.1 hikaru }
638 1.1 hikaru
639 1.1 hikaru octeon_fau_op_inc_fetch_8(&sc->sc_fau_done, i);
640 1.1 hikaru sc->sc_flush = i;
641 1.1 hikaru }
642 1.1 hikaru
643 1.1 hikaru static inline void
644 1.1 hikaru octeon_eth_send_queue_flush_sync(struct octeon_eth_softc *sc)
645 1.1 hikaru {
646 1.1 hikaru if (sc->sc_flush == 0)
647 1.1 hikaru return;
648 1.1 hikaru
649 1.1 hikaru OCTEON_ETH_KASSERT(sc->sc_flush > 0);
650 1.1 hikaru
651 1.1 hikaru /* XXX XXX XXX */
652 1.1 hikaru octeon_fau_op_inc_read_8(&sc->sc_fau_done);
653 1.1 hikaru sc->sc_soft_req_cnt -= sc->sc_flush;
654 1.1 hikaru OCTEON_ETH_KASSERT(sc->sc_soft_req_cnt >= 0);
655 1.1 hikaru /* XXX XXX XXX */
656 1.1 hikaru
657 1.1 hikaru sc->sc_flush = 0;
658 1.1 hikaru }
659 1.1 hikaru
660 1.1 hikaru static inline int
661 1.1 hikaru octeon_eth_send_queue_is_full(struct octeon_eth_softc *sc)
662 1.1 hikaru {
663 1.1 hikaru #ifdef OCTEON_ETH_SEND_QUEUE_CHECK
664 1.1 hikaru int64_t nofree_cnt;
665 1.1 hikaru
666 1.1 hikaru nofree_cnt = sc->sc_soft_req_cnt + sc->sc_hard_done_cnt;
667 1.1 hikaru
668 1.1 hikaru if (__predict_false(nofree_cnt == GATHER_QUEUE_SIZE - 1)) {
669 1.1 hikaru octeon_eth_send_queue_flush(sc);
670 1.1 hikaru OCTEON_EVCNT_INC(sc, txerrgbuf);
671 1.1 hikaru octeon_eth_send_queue_flush_sync(sc);
672 1.1 hikaru return 1;
673 1.1 hikaru }
674 1.1 hikaru
675 1.1 hikaru #endif
676 1.1 hikaru return 0;
677 1.1 hikaru }
678 1.1 hikaru
679 1.1 hikaru /*
680 1.1 hikaru * (Ab)use m_nextpkt and m_paddr to maintain mbuf chain and pointer to gather
681 1.1 hikaru * buffer. Other mbuf members may be used by m_freem(), so don't touch them!
682 1.1 hikaru */
683 1.1 hikaru
684 1.1 hikaru struct _send_queue_entry {
685 1.1 hikaru union {
686 1.1 hikaru struct mbuf _sqe_s_mbuf;
687 1.1 hikaru struct {
688 1.1 hikaru char _sqe_s_entry_pad[offsetof(struct mbuf, m_nextpkt)];
689 1.1 hikaru SIMPLEQ_ENTRY(_send_queue_entry) _sqe_s_entry_entry;
690 1.1 hikaru } _sqe_s_entry;
691 1.1 hikaru struct {
692 1.1 hikaru char _sqe_s_gbuf_pad[offsetof(struct mbuf, m_paddr)];
693 1.1 hikaru uint64_t *_sqe_s_gbuf_gbuf;
694 1.1 hikaru } _sqe_s_gbuf;
695 1.1 hikaru } _sqe_u;
696 1.1 hikaru #define _sqe_entry _sqe_u._sqe_s_entry._sqe_s_entry_entry
697 1.1 hikaru #define _sqe_gbuf _sqe_u._sqe_s_gbuf._sqe_s_gbuf_gbuf
698 1.1 hikaru };
699 1.1 hikaru
700 1.1 hikaru static inline void
701 1.1 hikaru octeon_eth_send_queue_add(struct octeon_eth_softc *sc, struct mbuf *m,
702 1.1 hikaru uint64_t *gbuf)
703 1.1 hikaru {
704 1.1 hikaru struct _send_queue_entry *sqe = (struct _send_queue_entry *)m;
705 1.1 hikaru
706 1.1 hikaru sqe->_sqe_gbuf = gbuf;
707 1.1 hikaru SIMPLEQ_INSERT_TAIL(&sc->sc_sendq, sqe, _sqe_entry);
708 1.1 hikaru
709 1.1 hikaru if ((m->m_flags & M_EXT) && m->m_ext.ext_free != NULL)
710 1.1 hikaru sc->sc_ext_callback_cnt++;
711 1.1 hikaru
712 1.1 hikaru OCTEON_EVCNT_INC(sc, txadd);
713 1.1 hikaru }
714 1.1 hikaru
715 1.1 hikaru static inline void
716 1.1 hikaru octeon_eth_send_queue_del(struct octeon_eth_softc *sc, struct mbuf **rm,
717 1.1 hikaru uint64_t **rgbuf)
718 1.1 hikaru {
719 1.1 hikaru struct _send_queue_entry *sqe;
720 1.1 hikaru
721 1.1 hikaru sqe = SIMPLEQ_FIRST(&sc->sc_sendq);
722 1.1 hikaru OCTEON_ETH_KASSERT(sqe != NULL);
723 1.1 hikaru SIMPLEQ_REMOVE_HEAD(&sc->sc_sendq, _sqe_entry);
724 1.1 hikaru
725 1.1 hikaru *rm = (void *)sqe;
726 1.1 hikaru *rgbuf = sqe->_sqe_gbuf;
727 1.1 hikaru
728 1.1 hikaru if (((*rm)->m_flags & M_EXT) && (*rm)->m_ext.ext_free != NULL) {
729 1.1 hikaru sc->sc_ext_callback_cnt--;
730 1.1 hikaru OCTEON_ETH_KASSERT(sc->sc_ext_callback_cnt >= 0);
731 1.1 hikaru }
732 1.1 hikaru
733 1.1 hikaru OCTEON_EVCNT_INC(sc, txdel);
734 1.1 hikaru }
735 1.1 hikaru
736 1.1 hikaru static inline int
737 1.1 hikaru octeon_eth_buf_free_work(struct octeon_eth_softc *sc, uint64_t *work,
738 1.1 hikaru uint64_t word2)
739 1.1 hikaru {
740 1.1 hikaru /* XXX when jumbo frame */
741 1.1 hikaru if (ISSET(word2, PIP_WQE_WORD2_IP_BUFS)) {
742 1.1 hikaru paddr_t addr;
743 1.1 hikaru paddr_t start_buffer;
744 1.1 hikaru
745 1.1 hikaru addr = work[3] & PIP_WQE_WORD3_ADDR;
746 1.1 hikaru start_buffer = addr & ~(2048 - 1);
747 1.1 hikaru
748 1.1 hikaru octeon_fpa_buf_put_paddr(octeon_eth_fb_pkt, start_buffer);
749 1.1 hikaru OCTEON_EVCNT_INC(sc, rxbufpkput);
750 1.1 hikaru }
751 1.1 hikaru
752 1.1 hikaru octeon_fpa_buf_put(octeon_eth_fb_wqe, work);
753 1.1 hikaru OCTEON_EVCNT_INC(sc, rxbufwqput);
754 1.1 hikaru
755 1.1 hikaru return 0;
756 1.1 hikaru }
757 1.1 hikaru
758 1.1 hikaru static inline void
759 1.1 hikaru octeon_eth_buf_ext_free_m(struct mbuf *m, void *buf, size_t size, void *arg)
760 1.1 hikaru {
761 1.1 hikaru uint64_t *work = (void *)arg;
762 1.1 hikaru #ifdef OCTEON_ETH_DEBUG
763 1.1 hikaru struct octeon_eth_softc *sc = (void *)(uintptr_t)work[0];
764 1.1 hikaru #endif
765 1.1 hikaru int s = splnet();
766 1.1 hikaru
767 1.1 hikaru OCTEON_EVCNT_INC(sc, rxrs);
768 1.1 hikaru
769 1.1 hikaru octeon_fpa_buf_put(octeon_eth_fb_wqe, work);
770 1.1 hikaru OCTEON_EVCNT_INC(sc, rxbufwqput);
771 1.1 hikaru
772 1.1 hikaru OCTEON_ETH_KASSERT(m != NULL);
773 1.1 hikaru
774 1.1 hikaru pool_cache_put(mb_cache, m);
775 1.1 hikaru
776 1.1 hikaru splx(s);
777 1.1 hikaru }
778 1.1 hikaru
779 1.1 hikaru static inline void
780 1.1 hikaru octeon_eth_buf_ext_free_ext(struct mbuf *m, void *buf, size_t size,
781 1.1 hikaru void *arg)
782 1.1 hikaru {
783 1.1 hikaru uint64_t *work = (void *)arg;
784 1.1 hikaru #ifdef OCTEON_ETH_DEBUG
785 1.1 hikaru struct octeon_eth_softc *sc = (void *)(uintptr_t)work[0];
786 1.1 hikaru #endif
787 1.1 hikaru int s = splnet();
788 1.1 hikaru
789 1.1 hikaru octeon_fpa_buf_put(octeon_eth_fb_wqe, work);
790 1.1 hikaru OCTEON_EVCNT_INC(sc, rxbufwqput);
791 1.1 hikaru
792 1.1 hikaru octeon_fpa_buf_put(octeon_eth_fb_pkt, buf);
793 1.1 hikaru OCTEON_EVCNT_INC(sc, rxbufpkput);
794 1.1 hikaru
795 1.1 hikaru OCTEON_ETH_KASSERT(m != NULL);
796 1.1 hikaru
797 1.1 hikaru pool_cache_put(mb_cache, m);
798 1.1 hikaru
799 1.1 hikaru splx(s);
800 1.1 hikaru }
801 1.1 hikaru
802 1.1 hikaru /* ---- ifnet interfaces */
803 1.1 hikaru
804 1.1 hikaru static int
805 1.1 hikaru octeon_eth_ioctl(struct ifnet *ifp, u_long cmd, void *data)
806 1.1 hikaru {
807 1.1 hikaru struct octeon_eth_softc *sc = ifp->if_softc;
808 1.1 hikaru struct ifreq *ifr = (struct ifreq *)data;
809 1.1 hikaru int s, error;
810 1.1 hikaru
811 1.1 hikaru s = splnet();
812 1.1 hikaru switch (cmd) {
813 1.1 hikaru case SIOCSIFMEDIA:
814 1.1 hikaru /* Flow control requires full-duplex mode. */
815 1.1 hikaru if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
816 1.1 hikaru (ifr->ifr_media & IFM_FDX) == 0) {
817 1.1 hikaru ifr->ifr_media &= ~IFM_ETH_FMASK;
818 1.1 hikaru }
819 1.1 hikaru if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
820 1.1 hikaru if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
821 1.1 hikaru ifr->ifr_media |=
822 1.1 hikaru IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
823 1.1 hikaru }
824 1.1 hikaru sc->sc_gmx_port->sc_port_flowflags =
825 1.1 hikaru ifr->ifr_media & IFM_ETH_FMASK;
826 1.1 hikaru }
827 1.1 hikaru /* FALLTHROUGH */
828 1.1 hikaru case SIOCGIFMEDIA:
829 1.1 hikaru /* XXX: Flow contorol */
830 1.1 hikaru error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
831 1.1 hikaru break;
832 1.1 hikaru default:
833 1.1 hikaru error = ether_ioctl(ifp, cmd, data);
834 1.1 hikaru if (error == ENETRESET) {
835 1.1 hikaru /*
836 1.1 hikaru * Multicast list has changed; set the hardware filter
837 1.1 hikaru * accordingly.
838 1.1 hikaru */
839 1.1 hikaru if (ISSET(ifp->if_flags, IFF_RUNNING))
840 1.1 hikaru octeon_gmx_set_filter(sc->sc_gmx_port);
841 1.1 hikaru error = 0;
842 1.1 hikaru }
843 1.1 hikaru break;
844 1.1 hikaru }
845 1.1 hikaru octeon_eth_start(ifp);
846 1.1 hikaru splx(s);
847 1.1 hikaru
848 1.1 hikaru return (error);
849 1.1 hikaru }
850 1.1 hikaru
851 1.1 hikaru /* ---- send (output) */
852 1.1 hikaru
853 1.1 hikaru static inline uint64_t
854 1.1 hikaru octeon_eth_send_makecmd_w0(uint64_t fau0, uint64_t fau1, size_t len, int segs)
855 1.1 hikaru {
856 1.1 hikaru return octeon_pko_cmd_word0(
857 1.1 hikaru OCT_FAU_OP_SIZE_64, /* sz1 */
858 1.1 hikaru OCT_FAU_OP_SIZE_64, /* sz0 */
859 1.1 hikaru 1, fau1, 1, fau0, /* s1, reg1, s0, reg0 */
860 1.1 hikaru 0, /* le */
861 1.1 hikaru octeon_eth_param_pko_cmd_w0_n2, /* n2 */
862 1.1 hikaru 1, 0, /* q, r */
863 1.1 hikaru (segs == 1) ? 0 : 1, /* g */
864 1.1 hikaru 0, 0, 1, /* ipoffp1, ii, df */
865 1.1 hikaru segs, (int)len); /* segs, totalbytes */
866 1.1 hikaru }
867 1.1 hikaru
868 1.1 hikaru static inline uint64_t
869 1.1 hikaru octeon_eth_send_makecmd_w1(int size, paddr_t addr)
870 1.1 hikaru {
871 1.1 hikaru return octeon_pko_cmd_word1(
872 1.1 hikaru 0, 0, /* i, back */
873 1.1 hikaru FPA_GATHER_BUFFER_POOL, /* pool */
874 1.1 hikaru size, addr); /* size, addr */
875 1.1 hikaru }
876 1.1 hikaru
877 1.1 hikaru static inline int
878 1.1 hikaru octeon_eth_send_makecmd_gbuf(struct octeon_eth_softc *sc, struct mbuf *m0,
879 1.1 hikaru uint64_t *gbuf, int *rsegs)
880 1.1 hikaru {
881 1.1 hikaru struct mbuf *m;
882 1.1 hikaru int segs = 0;
883 1.1 hikaru uintptr_t laddr, rlen, nlen;
884 1.1 hikaru
885 1.1 hikaru for (m = m0; m != NULL; m = m->m_next) {
886 1.1 hikaru
887 1.1 hikaru if (__predict_false(m->m_len == 0))
888 1.1 hikaru continue;
889 1.1 hikaru
890 1.1 hikaru #if 0
891 1.1 hikaru OCTEON_ETH_KASSERT(((uint32_t)m->m_data & (PAGE_SIZE - 1))
892 1.1 hikaru == (kvtophys((vaddr_t)m->m_data) & (PAGE_SIZE - 1)));
893 1.1 hikaru #endif
894 1.1 hikaru
895 1.1 hikaru /*
896 1.1 hikaru * aligned 4k
897 1.1 hikaru */
898 1.1 hikaru laddr = (uintptr_t)m->m_data & (PAGE_SIZE - 1);
899 1.1 hikaru
900 1.1 hikaru if (laddr + m->m_len > PAGE_SIZE) {
901 1.1 hikaru /* XXX XXX XXX */
902 1.1 hikaru rlen = PAGE_SIZE - laddr;
903 1.1 hikaru nlen = m->m_len - rlen;
904 1.1 hikaru *(gbuf + segs) = octeon_eth_send_makecmd_w1(rlen,
905 1.1 hikaru kvtophys((vaddr_t)m->m_data));
906 1.1 hikaru segs++;
907 1.1 hikaru if (segs > 63) {
908 1.1 hikaru return 1;
909 1.1 hikaru }
910 1.1 hikaru /* XXX XXX XXX */
911 1.1 hikaru } else {
912 1.1 hikaru rlen = 0;
913 1.1 hikaru nlen = m->m_len;
914 1.1 hikaru }
915 1.1 hikaru
916 1.1 hikaru *(gbuf + segs) = octeon_eth_send_makecmd_w1(nlen,
917 1.1 hikaru kvtophys((vaddr_t)(m->m_data + rlen)));
918 1.1 hikaru segs++;
919 1.1 hikaru if (segs > 63) {
920 1.1 hikaru return 1;
921 1.1 hikaru }
922 1.1 hikaru }
923 1.1 hikaru
924 1.1 hikaru OCTEON_ETH_KASSERT(m == NULL);
925 1.1 hikaru
926 1.1 hikaru *rsegs = segs;
927 1.1 hikaru
928 1.1 hikaru return 0;
929 1.1 hikaru }
930 1.1 hikaru
931 1.1 hikaru static inline int
932 1.1 hikaru octeon_eth_send_makecmd(struct octeon_eth_softc *sc, struct mbuf *m,
933 1.1 hikaru uint64_t *gbuf, uint64_t *rpko_cmd_w0, uint64_t *rpko_cmd_w1)
934 1.1 hikaru {
935 1.1 hikaru uint64_t pko_cmd_w0, pko_cmd_w1;
936 1.1 hikaru int segs;
937 1.1 hikaru int result = 0;
938 1.1 hikaru
939 1.1 hikaru if (octeon_eth_send_makecmd_gbuf(sc, m, gbuf, &segs)) {
940 1.1 hikaru log(LOG_WARNING, "%s: there are a lot of number of segments"
941 1.1 hikaru " of transmission data", device_xname(sc->sc_dev));
942 1.1 hikaru result = 1;
943 1.1 hikaru goto done;
944 1.1 hikaru }
945 1.1 hikaru
946 1.1 hikaru /*
947 1.1 hikaru * segs == 1 -> link mode (single continuous buffer)
948 1.1 hikaru * WORD1[size] is number of bytes pointed by segment
949 1.1 hikaru *
950 1.1 hikaru * segs > 1 -> gather mode (scatter-gather buffer)
951 1.1 hikaru * WORD1[size] is number of segments
952 1.1 hikaru */
953 1.1 hikaru pko_cmd_w0 = octeon_eth_send_makecmd_w0(sc->sc_fau_done.fd_regno,
954 1.1 hikaru 0, m->m_pkthdr.len, segs);
955 1.4 matt if (segs == 1) {
956 1.4 matt pko_cmd_w1 = octeon_eth_send_makecmd_w1(
957 1.4 matt m->m_pkthdr.len, kvtophys((vaddr_t)m->m_data));
958 1.4 matt } else {
959 1.4 matt #ifdef __mips_n32
960 1.4 matt KASSERT(MIPS_KSEG0_P(gbuf));
961 1.4 matt pko_cmd_w1 = octeon_eth_send_makecmd_w1(segs,
962 1.4 matt MIPS_KSEG0_TO_PHYS(gbuf));
963 1.4 matt #else
964 1.4 matt pko_cmd_w1 = octeon_eth_send_makecmd_w1(segs,
965 1.4 matt MIPS_XKPHYS_TO_PHYS(gbuf));
966 1.4 matt #endif
967 1.4 matt }
968 1.1 hikaru
969 1.1 hikaru *rpko_cmd_w0 = pko_cmd_w0;
970 1.1 hikaru *rpko_cmd_w1 = pko_cmd_w1;
971 1.1 hikaru
972 1.1 hikaru done:
973 1.1 hikaru return result;
974 1.1 hikaru }
975 1.1 hikaru
976 1.1 hikaru static inline int
977 1.1 hikaru octeon_eth_send_cmd(struct octeon_eth_softc *sc, uint64_t pko_cmd_w0,
978 1.8 jmcneill uint64_t pko_cmd_w1, int *pwdc)
979 1.1 hikaru {
980 1.1 hikaru uint64_t *cmdptr;
981 1.1 hikaru int result = 0;
982 1.1 hikaru
983 1.4 matt #ifdef __mips_n32
984 1.4 matt KASSERT((sc->sc_cmdptr.cmdptr & ~MIPS_PHYS_MASK) == 0);
985 1.4 matt cmdptr = (uint64_t *)MIPS_PHYS_TO_KSEG0(sc->sc_cmdptr.cmdptr);
986 1.4 matt #else
987 1.1 hikaru cmdptr = (uint64_t *)MIPS_PHYS_TO_XKPHYS_CACHED(sc->sc_cmdptr.cmdptr);
988 1.4 matt #endif
989 1.1 hikaru cmdptr += sc->sc_cmdptr.cmdptr_idx;
990 1.1 hikaru
991 1.1 hikaru OCTEON_ETH_KASSERT(cmdptr != NULL);
992 1.1 hikaru
993 1.1 hikaru *cmdptr++ = pko_cmd_w0;
994 1.1 hikaru *cmdptr++ = pko_cmd_w1;
995 1.1 hikaru
996 1.1 hikaru OCTEON_ETH_KASSERT(sc->sc_cmdptr.cmdptr_idx + 2 <= FPA_COMMAND_BUFFER_POOL_NWORDS - 1);
997 1.1 hikaru
998 1.1 hikaru if (sc->sc_cmdptr.cmdptr_idx + 2 == FPA_COMMAND_BUFFER_POOL_NWORDS - 1) {
999 1.1 hikaru paddr_t buf;
1000 1.1 hikaru
1001 1.1 hikaru buf = octeon_fpa_buf_get_paddr(octeon_eth_fb_cmd);
1002 1.1 hikaru if (buf == 0) {
1003 1.1 hikaru log(LOG_WARNING,
1004 1.1 hikaru "%s: can not allocate command buffer from free pool allocator\n",
1005 1.1 hikaru device_xname(sc->sc_dev));
1006 1.1 hikaru result = 1;
1007 1.1 hikaru goto done;
1008 1.1 hikaru }
1009 1.1 hikaru OCTEON_EVCNT_INC(sc, txbufcbget);
1010 1.1 hikaru *cmdptr++ = buf;
1011 1.1 hikaru sc->sc_cmdptr.cmdptr = (uint64_t)buf;
1012 1.1 hikaru sc->sc_cmdptr.cmdptr_idx = 0;
1013 1.1 hikaru } else {
1014 1.1 hikaru sc->sc_cmdptr.cmdptr_idx += 2;
1015 1.1 hikaru }
1016 1.1 hikaru
1017 1.8 jmcneill *pwdc += 2;
1018 1.1 hikaru
1019 1.1 hikaru done:
1020 1.1 hikaru return result;
1021 1.1 hikaru }
1022 1.1 hikaru
1023 1.1 hikaru static inline int
1024 1.1 hikaru octeon_eth_send_buf(struct octeon_eth_softc *sc, struct mbuf *m,
1025 1.8 jmcneill uint64_t *gbuf, int *pwdc)
1026 1.1 hikaru {
1027 1.1 hikaru int result = 0, error;
1028 1.1 hikaru uint64_t pko_cmd_w0, pko_cmd_w1;
1029 1.1 hikaru
1030 1.1 hikaru error = octeon_eth_send_makecmd(sc, m, gbuf, &pko_cmd_w0, &pko_cmd_w1);
1031 1.1 hikaru if (error != 0) {
1032 1.1 hikaru /* already logging */
1033 1.1 hikaru OCTEON_EVCNT_INC(sc, txerrmkcmd);
1034 1.1 hikaru result = error;
1035 1.1 hikaru goto done;
1036 1.1 hikaru }
1037 1.1 hikaru
1038 1.8 jmcneill error = octeon_eth_send_cmd(sc, pko_cmd_w0, pko_cmd_w1, pwdc);
1039 1.1 hikaru if (error != 0) {
1040 1.1 hikaru /* already logging */
1041 1.1 hikaru OCTEON_EVCNT_INC(sc, txerrcmd);
1042 1.1 hikaru result = error;
1043 1.1 hikaru }
1044 1.1 hikaru
1045 1.1 hikaru done:
1046 1.1 hikaru return result;
1047 1.1 hikaru }
1048 1.1 hikaru
1049 1.1 hikaru static inline int
1050 1.8 jmcneill octeon_eth_send(struct octeon_eth_softc *sc, struct mbuf *m, int *pwdc)
1051 1.1 hikaru {
1052 1.1 hikaru paddr_t gaddr = 0;
1053 1.1 hikaru uint64_t *gbuf = NULL;
1054 1.1 hikaru int result = 0, error;
1055 1.1 hikaru
1056 1.1 hikaru OCTEON_EVCNT_INC(sc, tx);
1057 1.1 hikaru
1058 1.1 hikaru gaddr = octeon_fpa_buf_get_paddr(octeon_eth_fb_sg);
1059 1.1 hikaru if (gaddr == 0) {
1060 1.1 hikaru log(LOG_WARNING,
1061 1.1 hikaru "%s: can not allocate gather buffer from free pool allocator\n",
1062 1.1 hikaru device_xname(sc->sc_dev));
1063 1.1 hikaru OCTEON_EVCNT_INC(sc, txerrgbuf);
1064 1.1 hikaru result = 1;
1065 1.1 hikaru goto done;
1066 1.1 hikaru }
1067 1.1 hikaru OCTEON_EVCNT_INC(sc, txbufgbget);
1068 1.1 hikaru
1069 1.4 matt #ifdef __mips_n32
1070 1.4 matt KASSERT((gaddr & ~MIPS_PHYS_MASK) == 0);
1071 1.4 matt gbuf = (uint64_t *)(uintptr_t)MIPS_PHYS_TO_KSEG0(gaddr);
1072 1.4 matt #else
1073 1.1 hikaru gbuf = (uint64_t *)(uintptr_t)MIPS_PHYS_TO_XKPHYS_CACHED(gaddr);
1074 1.4 matt #endif
1075 1.1 hikaru
1076 1.1 hikaru OCTEON_ETH_KASSERT(gbuf != NULL);
1077 1.1 hikaru
1078 1.8 jmcneill error = octeon_eth_send_buf(sc, m, gbuf, pwdc);
1079 1.1 hikaru if (error != 0) {
1080 1.1 hikaru /* already logging */
1081 1.1 hikaru octeon_fpa_buf_put_paddr(octeon_eth_fb_sg, gaddr);
1082 1.1 hikaru OCTEON_EVCNT_INC(sc, txbufgbput);
1083 1.1 hikaru result = error;
1084 1.1 hikaru goto done;
1085 1.1 hikaru }
1086 1.1 hikaru
1087 1.1 hikaru octeon_eth_send_queue_add(sc, m, gbuf);
1088 1.1 hikaru
1089 1.1 hikaru done:
1090 1.1 hikaru return result;
1091 1.1 hikaru }
1092 1.1 hikaru
1093 1.1 hikaru static void
1094 1.1 hikaru octeon_eth_start(struct ifnet *ifp)
1095 1.1 hikaru {
1096 1.1 hikaru struct octeon_eth_softc *sc = ifp->if_softc;
1097 1.1 hikaru struct mbuf *m;
1098 1.8 jmcneill int wdc = 0;
1099 1.1 hikaru
1100 1.1 hikaru /*
1101 1.1 hikaru * performance tuning
1102 1.1 hikaru * presend iobdma request
1103 1.1 hikaru */
1104 1.1 hikaru octeon_eth_send_queue_flush_prefetch(sc);
1105 1.1 hikaru
1106 1.1 hikaru if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1107 1.1 hikaru goto last;
1108 1.1 hikaru
1109 1.1 hikaru /* XXX assume that OCTEON doesn't buffer packets */
1110 1.1 hikaru if (__predict_false(!octeon_gmx_link_status(sc->sc_gmx_port))) {
1111 1.1 hikaru /* dequeue and drop them */
1112 1.1 hikaru while (1) {
1113 1.1 hikaru IFQ_DEQUEUE(&ifp->if_snd, m);
1114 1.1 hikaru if (m == NULL)
1115 1.1 hikaru break;
1116 1.1 hikaru
1117 1.1 hikaru m_freem(m);
1118 1.1 hikaru IF_DROP(&ifp->if_snd);
1119 1.1 hikaru OCTEON_EVCNT_INC(sc, txerrlink);
1120 1.1 hikaru }
1121 1.1 hikaru goto last;
1122 1.1 hikaru }
1123 1.1 hikaru
1124 1.1 hikaru for (;;) {
1125 1.1 hikaru IFQ_POLL(&ifp->if_snd, m);
1126 1.1 hikaru if (__predict_false(m == NULL))
1127 1.1 hikaru break;
1128 1.1 hikaru
1129 1.1 hikaru /* XXX XXX XXX */
1130 1.1 hikaru octeon_eth_send_queue_flush_fetch(sc);
1131 1.1 hikaru
1132 1.1 hikaru /*
1133 1.1 hikaru * If no free send buffer is available, free all the sent buffer
1134 1.1 hikaru * and bail out.
1135 1.1 hikaru */
1136 1.1 hikaru if (octeon_eth_send_queue_is_full(sc)) {
1137 1.8 jmcneill SET(ifp->if_flags, IFF_OACTIVE);
1138 1.8 jmcneill if (wdc > 0)
1139 1.8 jmcneill octeon_pko_op_doorbell_write(sc->sc_port,
1140 1.8 jmcneill sc->sc_port, wdc);
1141 1.1 hikaru return;
1142 1.1 hikaru }
1143 1.1 hikaru /* XXX XXX XXX */
1144 1.1 hikaru
1145 1.1 hikaru IFQ_DEQUEUE(&ifp->if_snd, m);
1146 1.1 hikaru
1147 1.9 msaitoh bpf_mtap(ifp, m, BPF_D_OUT);
1148 1.1 hikaru
1149 1.1 hikaru /* XXX XXX XXX */
1150 1.1 hikaru if (sc->sc_soft_req_cnt > sc->sc_soft_req_thresh)
1151 1.1 hikaru octeon_eth_send_queue_flush(sc);
1152 1.8 jmcneill if (octeon_eth_send(sc, m, &wdc)) {
1153 1.1 hikaru IF_DROP(&ifp->if_snd);
1154 1.1 hikaru m_freem(m);
1155 1.1 hikaru log(LOG_WARNING,
1156 1.1 hikaru "%s: failed in the transmission of the packet\n",
1157 1.1 hikaru device_xname(sc->sc_dev));
1158 1.1 hikaru OCTEON_EVCNT_INC(sc, txerr);
1159 1.1 hikaru } else {
1160 1.1 hikaru sc->sc_soft_req_cnt++;
1161 1.1 hikaru }
1162 1.1 hikaru if (sc->sc_flush)
1163 1.1 hikaru octeon_eth_send_queue_flush_sync(sc);
1164 1.1 hikaru /* XXX XXX XXX */
1165 1.1 hikaru
1166 1.1 hikaru /*
1167 1.1 hikaru * send next iobdma request
1168 1.1 hikaru */
1169 1.1 hikaru octeon_eth_send_queue_flush_prefetch(sc);
1170 1.1 hikaru }
1171 1.1 hikaru
1172 1.8 jmcneill if (wdc > 0)
1173 1.8 jmcneill octeon_pko_op_doorbell_write(sc->sc_port, sc->sc_port, wdc);
1174 1.8 jmcneill
1175 1.1 hikaru /*
1176 1.1 hikaru * Don't schedule send-buffer-free callout every time - those buffers are freed
1177 1.1 hikaru * by "free tick". This makes some packets like NFS slower.
1178 1.1 hikaru */
1179 1.1 hikaru #ifdef OCTEON_ETH_USENFS
1180 1.1 hikaru if (__predict_false(sc->sc_ext_callback_cnt > 0)) {
1181 1.1 hikaru int timo;
1182 1.1 hikaru
1183 1.1 hikaru /* ??? */
1184 1.1 hikaru timo = hz - (100 * sc->sc_ext_callback_cnt);
1185 1.1 hikaru if (timo < 10)
1186 1.1 hikaru timo = 10;
1187 1.1 hikaru callout_schedule(&sc->sc_tick_free_ch, timo);
1188 1.1 hikaru }
1189 1.1 hikaru #endif
1190 1.1 hikaru
1191 1.1 hikaru last:
1192 1.1 hikaru octeon_eth_send_queue_flush_fetch(sc);
1193 1.1 hikaru }
1194 1.1 hikaru
1195 1.1 hikaru static void
1196 1.1 hikaru octeon_eth_watchdog(struct ifnet *ifp)
1197 1.1 hikaru {
1198 1.1 hikaru struct octeon_eth_softc *sc = ifp->if_softc;
1199 1.1 hikaru
1200 1.1 hikaru printf("%s: device timeout\n", device_xname(sc->sc_dev));
1201 1.1 hikaru
1202 1.1 hikaru octeon_eth_configure(sc);
1203 1.1 hikaru
1204 1.1 hikaru SET(ifp->if_flags, IFF_RUNNING);
1205 1.1 hikaru CLR(ifp->if_flags, IFF_OACTIVE);
1206 1.1 hikaru ifp->if_timer = 0;
1207 1.1 hikaru
1208 1.1 hikaru octeon_eth_start(ifp);
1209 1.1 hikaru }
1210 1.1 hikaru
1211 1.1 hikaru static int
1212 1.1 hikaru octeon_eth_init(struct ifnet *ifp)
1213 1.1 hikaru {
1214 1.1 hikaru struct octeon_eth_softc *sc = ifp->if_softc;
1215 1.1 hikaru
1216 1.1 hikaru /* XXX don't disable commonly used parts!!! XXX */
1217 1.1 hikaru if (sc->sc_init_flag == 0) {
1218 1.1 hikaru /* Cancel any pending I/O. */
1219 1.1 hikaru octeon_eth_stop(ifp, 0);
1220 1.1 hikaru
1221 1.1 hikaru /* Initialize the device */
1222 1.1 hikaru octeon_eth_configure(sc);
1223 1.1 hikaru
1224 1.1 hikaru octeon_pko_enable(sc->sc_pko);
1225 1.1 hikaru octeon_ipd_enable(sc->sc_ipd);
1226 1.1 hikaru
1227 1.1 hikaru sc->sc_init_flag = 1;
1228 1.1 hikaru } else {
1229 1.1 hikaru octeon_gmx_port_enable(sc->sc_gmx_port, 1);
1230 1.1 hikaru }
1231 1.1 hikaru octeon_eth_mediachange(ifp);
1232 1.1 hikaru
1233 1.1 hikaru octeon_gmx_set_filter(sc->sc_gmx_port);
1234 1.1 hikaru
1235 1.1 hikaru callout_reset(&sc->sc_tick_misc_ch, hz, octeon_eth_tick_misc, sc);
1236 1.1 hikaru callout_reset(&sc->sc_tick_free_ch, hz, octeon_eth_tick_free, sc);
1237 1.1 hikaru
1238 1.1 hikaru SET(ifp->if_flags, IFF_RUNNING);
1239 1.1 hikaru CLR(ifp->if_flags, IFF_OACTIVE);
1240 1.1 hikaru
1241 1.1 hikaru return 0;
1242 1.1 hikaru }
1243 1.1 hikaru
1244 1.1 hikaru static void
1245 1.1 hikaru octeon_eth_stop(struct ifnet *ifp, int disable)
1246 1.1 hikaru {
1247 1.1 hikaru struct octeon_eth_softc *sc = ifp->if_softc;
1248 1.1 hikaru
1249 1.1 hikaru callout_stop(&sc->sc_tick_misc_ch);
1250 1.1 hikaru callout_stop(&sc->sc_tick_free_ch);
1251 1.1 hikaru
1252 1.1 hikaru mii_down(&sc->sc_mii);
1253 1.1 hikaru
1254 1.1 hikaru octeon_gmx_port_enable(sc->sc_gmx_port, 0);
1255 1.1 hikaru
1256 1.1 hikaru /* Mark the interface as down and cancel the watchdog timer. */
1257 1.1 hikaru CLR(ifp->if_flags, IFF_RUNNING | IFF_OACTIVE);
1258 1.1 hikaru ifp->if_timer = 0;
1259 1.1 hikaru }
1260 1.1 hikaru
1261 1.1 hikaru /* ---- misc */
1262 1.1 hikaru
1263 1.1 hikaru #define PKO_INDEX_MASK ((1ULL << 12/* XXX */) - 1)
1264 1.1 hikaru
1265 1.1 hikaru static int
1266 1.1 hikaru octeon_eth_reset(struct octeon_eth_softc *sc)
1267 1.1 hikaru {
1268 1.1 hikaru octeon_gmx_reset_speed(sc->sc_gmx_port);
1269 1.1 hikaru octeon_gmx_reset_flowctl(sc->sc_gmx_port);
1270 1.1 hikaru octeon_gmx_reset_timing(sc->sc_gmx_port);
1271 1.1 hikaru
1272 1.1 hikaru return 0;
1273 1.1 hikaru }
1274 1.1 hikaru
1275 1.1 hikaru static int
1276 1.1 hikaru octeon_eth_configure(struct octeon_eth_softc *sc)
1277 1.1 hikaru {
1278 1.1 hikaru octeon_gmx_port_enable(sc->sc_gmx_port, 0);
1279 1.1 hikaru
1280 1.1 hikaru octeon_eth_reset(sc);
1281 1.1 hikaru
1282 1.1 hikaru octeon_eth_configure_common(sc);
1283 1.1 hikaru
1284 1.1 hikaru octeon_pko_port_config(sc->sc_pko);
1285 1.1 hikaru octeon_pko_port_enable(sc->sc_pko, 1);
1286 1.1 hikaru octeon_pip_port_config(sc->sc_pip);
1287 1.1 hikaru
1288 1.1 hikaru octeon_gmx_tx_stats_rd_clr(sc->sc_gmx_port, 1);
1289 1.1 hikaru octeon_gmx_rx_stats_rd_clr(sc->sc_gmx_port, 1);
1290 1.1 hikaru
1291 1.1 hikaru octeon_gmx_port_enable(sc->sc_gmx_port, 1);
1292 1.1 hikaru
1293 1.1 hikaru return 0;
1294 1.1 hikaru }
1295 1.1 hikaru
1296 1.1 hikaru static int
1297 1.1 hikaru octeon_eth_configure_common(struct octeon_eth_softc *sc)
1298 1.1 hikaru {
1299 1.1 hikaru static int once;
1300 1.1 hikaru
1301 1.1 hikaru if (once == 1)
1302 1.1 hikaru return 0;
1303 1.1 hikaru once = 1;
1304 1.1 hikaru
1305 1.1 hikaru octeon_ipd_config(sc->sc_ipd);
1306 1.1 hikaru #ifdef OCTEON_ETH_IPD_RED
1307 1.1 hikaru octeon_ipd_red(sc->sc_ipd, RECV_QUEUE_SIZE >> 2, RECV_QUEUE_SIZE >> 3);
1308 1.1 hikaru #endif
1309 1.1 hikaru octeon_pko_config(sc->sc_pko);
1310 1.1 hikaru
1311 1.1 hikaru octeon_pow_config(sc->sc_pow, OCTEON_POW_GROUP_PIP);
1312 1.1 hikaru
1313 1.1 hikaru return 0;
1314 1.1 hikaru }
1315 1.1 hikaru
1316 1.1 hikaru /* ---- receive (input) */
1317 1.1 hikaru
1318 1.1 hikaru static inline int
1319 1.1 hikaru octeon_eth_recv_mbuf(struct octeon_eth_softc *sc, uint64_t *work,
1320 1.1 hikaru struct mbuf **rm)
1321 1.1 hikaru {
1322 1.1 hikaru struct mbuf *m;
1323 1.1 hikaru void (*ext_free)(struct mbuf *, void *, size_t, void *);
1324 1.1 hikaru void *ext_buf;
1325 1.1 hikaru size_t ext_size;
1326 1.1 hikaru void *data;
1327 1.1 hikaru uint64_t word1 = work[1];
1328 1.1 hikaru uint64_t word2 = work[2];
1329 1.1 hikaru uint64_t word3 = work[3];
1330 1.1 hikaru
1331 1.1 hikaru MGETHDR(m, M_NOWAIT, MT_DATA);
1332 1.1 hikaru if (m == NULL)
1333 1.1 hikaru return 1;
1334 1.1 hikaru OCTEON_ETH_KASSERT(m != NULL);
1335 1.1 hikaru
1336 1.1 hikaru if ((word2 & PIP_WQE_WORD2_IP_BUFS) == 0) {
1337 1.1 hikaru /* Dynamic short */
1338 1.1 hikaru ext_free = octeon_eth_buf_ext_free_m;
1339 1.1 hikaru ext_buf = &work[4];
1340 1.1 hikaru ext_size = 96;
1341 1.1 hikaru
1342 1.1 hikaru data = &work[4 + sc->sc_ip_offset / sizeof(uint64_t)];
1343 1.1 hikaru } else {
1344 1.1 hikaru vaddr_t addr;
1345 1.1 hikaru vaddr_t start_buffer;
1346 1.1 hikaru
1347 1.4 matt #ifdef __mips_n32
1348 1.4 matt KASSERT((word3 & ~MIPS_PHYS_MASK) == 0);
1349 1.4 matt addr = MIPS_PHYS_TO_KSEG0(word3 & PIP_WQE_WORD3_ADDR);
1350 1.4 matt #else
1351 1.1 hikaru addr = MIPS_PHYS_TO_XKPHYS_CACHED(word3 & PIP_WQE_WORD3_ADDR);
1352 1.4 matt #endif
1353 1.1 hikaru start_buffer = addr & ~(2048 - 1);
1354 1.1 hikaru
1355 1.1 hikaru ext_free = octeon_eth_buf_ext_free_ext;
1356 1.1 hikaru ext_buf = (void *)start_buffer;
1357 1.1 hikaru ext_size = 2048;
1358 1.1 hikaru
1359 1.1 hikaru data = (void *)addr;
1360 1.1 hikaru }
1361 1.1 hikaru
1362 1.1 hikaru /* embed sc pointer into work[0] for _ext_free evcnt */
1363 1.1 hikaru work[0] = (uintptr_t)sc;
1364 1.1 hikaru
1365 1.1 hikaru MEXTADD(m, ext_buf, ext_size, 0, ext_free, work);
1366 1.1 hikaru OCTEON_ETH_KASSERT(ISSET(m->m_flags, M_EXT));
1367 1.1 hikaru
1368 1.1 hikaru m->m_data = data;
1369 1.1 hikaru m->m_len = m->m_pkthdr.len = (word1 & PIP_WQE_WORD1_LEN) >> 48;
1370 1.3 ozaki m_set_rcvif(m, &sc->sc_ethercom.ec_if);
1371 1.1 hikaru /*
1372 1.1 hikaru * not readonly buffer
1373 1.1 hikaru */
1374 1.1 hikaru m->m_flags |= M_EXT_RW;
1375 1.1 hikaru
1376 1.1 hikaru *rm = m;
1377 1.1 hikaru
1378 1.1 hikaru OCTEON_ETH_KASSERT(*rm != NULL);
1379 1.1 hikaru
1380 1.1 hikaru return 0;
1381 1.1 hikaru }
1382 1.1 hikaru
1383 1.1 hikaru static inline int
1384 1.1 hikaru octeon_eth_recv_check_code(struct octeon_eth_softc *sc, uint64_t word2)
1385 1.1 hikaru {
1386 1.1 hikaru uint64_t opecode = word2 & PIP_WQE_WORD2_NOIP_OPECODE;
1387 1.1 hikaru
1388 1.1 hikaru if (__predict_true(!ISSET(word2, PIP_WQE_WORD2_NOIP_RE)))
1389 1.1 hikaru return 0;
1390 1.1 hikaru
1391 1.1 hikaru /* this error is harmless */
1392 1.1 hikaru if (opecode == PIP_OVER_ERR)
1393 1.1 hikaru return 0;
1394 1.1 hikaru
1395 1.1 hikaru return 1;
1396 1.1 hikaru }
1397 1.1 hikaru
1398 1.1 hikaru static inline int
1399 1.1 hikaru octeon_eth_recv_check_jumbo(struct octeon_eth_softc *sc, uint64_t word2)
1400 1.1 hikaru {
1401 1.1 hikaru if (__predict_false((word2 & PIP_WQE_WORD2_IP_BUFS) > (1ULL << 56)))
1402 1.1 hikaru return 1;
1403 1.1 hikaru return 0;
1404 1.1 hikaru }
1405 1.1 hikaru
1406 1.1 hikaru static inline int
1407 1.1 hikaru octeon_eth_recv_check_link(struct octeon_eth_softc *sc, uint64_t word2)
1408 1.1 hikaru {
1409 1.1 hikaru if (__predict_false(!octeon_gmx_link_status(sc->sc_gmx_port)))
1410 1.1 hikaru return 1;
1411 1.1 hikaru return 0;
1412 1.1 hikaru }
1413 1.1 hikaru
1414 1.1 hikaru static inline int
1415 1.1 hikaru octeon_eth_recv_check(struct octeon_eth_softc *sc, uint64_t word2)
1416 1.1 hikaru {
1417 1.1 hikaru if (__predict_false(octeon_eth_recv_check_link(sc, word2)) != 0) {
1418 1.1 hikaru if (ratecheck(&sc->sc_rate_recv_check_link_last,
1419 1.1 hikaru &sc->sc_rate_recv_check_link_cap))
1420 1.1 hikaru log(LOG_DEBUG,
1421 1.1 hikaru "%s: link is not up, the packet was dropped\n",
1422 1.1 hikaru device_xname(sc->sc_dev));
1423 1.1 hikaru OCTEON_EVCNT_INC(sc, rxerrlink);
1424 1.1 hikaru return 1;
1425 1.1 hikaru }
1426 1.1 hikaru
1427 1.1 hikaru #if 0 /* XXX Performance tunig (Jumbo-frame is not supported yet!) */
1428 1.1 hikaru if (__predict_false(octeon_eth_recv_check_jumbo(sc, word2)) != 0) {
1429 1.1 hikaru /* XXX jumbo frame */
1430 1.1 hikaru if (ratecheck(&sc->sc_rate_recv_check_jumbo_last,
1431 1.1 hikaru &sc->sc_rate_recv_check_jumbo_cap))
1432 1.1 hikaru log(LOG_DEBUG,
1433 1.1 hikaru "jumbo frame was received\n");
1434 1.1 hikaru OCTEON_EVCNT_INC(sc, rxerrjmb);
1435 1.1 hikaru return 1;
1436 1.1 hikaru }
1437 1.1 hikaru #endif
1438 1.1 hikaru
1439 1.1 hikaru if (__predict_false(octeon_eth_recv_check_code(sc, word2)) != 0) {
1440 1.1 hikaru
1441 1.1 hikaru if ((word2 & PIP_WQE_WORD2_NOIP_OPECODE) ==
1442 1.1 hikaru PIP_WQE_WORD2_RE_OPCODE_LENGTH) {
1443 1.1 hikaru /* no logging */
1444 1.1 hikaru /* XXX inclement special error count */
1445 1.1 hikaru } else if ((word2 & PIP_WQE_WORD2_NOIP_OPECODE) ==
1446 1.1 hikaru PIP_WQE_WORD2_RE_OPCODE_PARTIAL) {
1447 1.1 hikaru /* not an erorr. it's because of overload */
1448 1.1 hikaru } else {
1449 1.1 hikaru
1450 1.1 hikaru if (ratecheck(&sc->sc_rate_recv_check_code_last,
1451 1.1 hikaru &sc->sc_rate_recv_check_code_cap))
1452 1.1 hikaru log(LOG_WARNING,
1453 1.6 maya "%s: reception error, packet dropped "
1454 1.6 maya "(error code = %" PRId64 ")\n",
1455 1.1 hikaru device_xname(sc->sc_dev), word2 & PIP_WQE_WORD2_NOIP_OPECODE);
1456 1.1 hikaru }
1457 1.1 hikaru OCTEON_EVCNT_INC(sc, rxerrcode);
1458 1.1 hikaru return 1;
1459 1.1 hikaru }
1460 1.1 hikaru
1461 1.1 hikaru return 0;
1462 1.1 hikaru }
1463 1.1 hikaru
1464 1.1 hikaru static inline int
1465 1.1 hikaru octeon_eth_recv(struct octeon_eth_softc *sc, uint64_t *work)
1466 1.1 hikaru {
1467 1.1 hikaru int result = 0;
1468 1.1 hikaru struct ifnet *ifp;
1469 1.1 hikaru struct mbuf *m;
1470 1.1 hikaru uint64_t word2;
1471 1.1 hikaru
1472 1.1 hikaru /* XXX XXX XXX */
1473 1.1 hikaru /*
1474 1.1 hikaru * performance tuning
1475 1.1 hikaru * presend iobdma request
1476 1.1 hikaru */
1477 1.1 hikaru if (sc->sc_soft_req_cnt > sc->sc_soft_req_thresh) {
1478 1.1 hikaru octeon_eth_send_queue_flush_prefetch(sc);
1479 1.1 hikaru }
1480 1.1 hikaru /* XXX XXX XXX */
1481 1.1 hikaru
1482 1.1 hikaru OCTEON_ETH_KASSERT(sc != NULL);
1483 1.1 hikaru OCTEON_ETH_KASSERT(work != NULL);
1484 1.1 hikaru
1485 1.1 hikaru OCTEON_EVCNT_INC(sc, rx);
1486 1.1 hikaru
1487 1.1 hikaru word2 = work[2];
1488 1.1 hikaru ifp = &sc->sc_ethercom.ec_if;
1489 1.1 hikaru
1490 1.1 hikaru OCTEON_ETH_KASSERT(ifp != NULL);
1491 1.1 hikaru
1492 1.1 hikaru if (__predict_false(octeon_eth_recv_check(sc, word2) != 0)) {
1493 1.1 hikaru ifp->if_ierrors++;
1494 1.1 hikaru result = 1;
1495 1.1 hikaru octeon_eth_buf_free_work(sc, work, word2);
1496 1.1 hikaru goto drop;
1497 1.1 hikaru }
1498 1.1 hikaru
1499 1.1 hikaru if (__predict_false(octeon_eth_recv_mbuf(sc, work, &m) != 0)) {
1500 1.1 hikaru ifp->if_ierrors++;
1501 1.1 hikaru result = 1;
1502 1.1 hikaru octeon_eth_buf_free_work(sc, work, word2);
1503 1.1 hikaru goto drop;
1504 1.1 hikaru }
1505 1.1 hikaru
1506 1.1 hikaru /* work[0] .. work[3] may not be valid any more */
1507 1.1 hikaru
1508 1.1 hikaru OCTEON_ETH_KASSERT(m != NULL);
1509 1.1 hikaru
1510 1.1 hikaru octeon_ipd_offload(word2, m->m_data, &m->m_pkthdr.csum_flags);
1511 1.1 hikaru
1512 1.1 hikaru /* XXX XXX XXX */
1513 1.1 hikaru if (sc->sc_soft_req_cnt > sc->sc_soft_req_thresh) {
1514 1.1 hikaru octeon_eth_send_queue_flush_fetch(sc);
1515 1.1 hikaru octeon_eth_send_queue_flush(sc);
1516 1.1 hikaru }
1517 1.1 hikaru
1518 1.1 hikaru /* XXX XXX XXX */
1519 1.1 hikaru if (sc->sc_flush)
1520 1.1 hikaru octeon_eth_send_queue_flush_sync(sc);
1521 1.1 hikaru /* XXX XXX XXX */
1522 1.1 hikaru
1523 1.2 ozaki if_percpuq_enqueue(ifp->if_percpuq, m);
1524 1.1 hikaru
1525 1.1 hikaru return 0;
1526 1.1 hikaru
1527 1.1 hikaru drop:
1528 1.1 hikaru /* XXX XXX XXX */
1529 1.1 hikaru if (sc->sc_soft_req_cnt > sc->sc_soft_req_thresh) {
1530 1.1 hikaru octeon_eth_send_queue_flush_fetch(sc);
1531 1.1 hikaru }
1532 1.1 hikaru /* XXX XXX XXX */
1533 1.1 hikaru
1534 1.1 hikaru return result;
1535 1.1 hikaru }
1536 1.1 hikaru
1537 1.1 hikaru static void
1538 1.1 hikaru octeon_eth_recv_redir(struct ifnet *ifp, struct mbuf *m)
1539 1.1 hikaru {
1540 1.1 hikaru struct octeon_eth_softc *rsc = ifp->if_softc;
1541 1.1 hikaru struct octeon_eth_softc *sc = NULL;
1542 1.8 jmcneill int i, wdc = 0;
1543 1.1 hikaru
1544 1.1 hikaru for (i = 0; i < 3 /* XXX */; i++) {
1545 1.1 hikaru if (rsc->sc_redir & (1 << i))
1546 1.1 hikaru sc = octeon_eth_gsc[i];
1547 1.1 hikaru }
1548 1.1 hikaru
1549 1.1 hikaru if (sc == NULL) {
1550 1.1 hikaru m_freem(m);
1551 1.1 hikaru return;
1552 1.1 hikaru }
1553 1.1 hikaru octeon_eth_send_queue_flush_prefetch(sc);
1554 1.1 hikaru
1555 1.1 hikaru octeon_eth_send_queue_flush_fetch(sc);
1556 1.1 hikaru
1557 1.1 hikaru if (octeon_eth_send_queue_is_full(sc)) {
1558 1.1 hikaru m_freem(m);
1559 1.1 hikaru return;
1560 1.1 hikaru }
1561 1.1 hikaru if (sc->sc_soft_req_cnt > sc->sc_soft_req_thresh)
1562 1.1 hikaru octeon_eth_send_queue_flush(sc);
1563 1.1 hikaru
1564 1.8 jmcneill if (octeon_eth_send(sc, m, &wdc)) {
1565 1.1 hikaru IF_DROP(&ifp->if_snd);
1566 1.1 hikaru m_freem(m);
1567 1.1 hikaru } else {
1568 1.8 jmcneill octeon_pko_op_doorbell_write(sc->sc_port, sc->sc_port, wdc);
1569 1.1 hikaru sc->sc_soft_req_cnt++;
1570 1.1 hikaru }
1571 1.1 hikaru
1572 1.1 hikaru if (sc->sc_flush)
1573 1.1 hikaru octeon_eth_send_queue_flush_sync(sc);
1574 1.1 hikaru }
1575 1.1 hikaru
1576 1.1 hikaru static inline void
1577 1.1 hikaru octeon_eth_recv_intr(void *data, uint64_t *work)
1578 1.1 hikaru {
1579 1.1 hikaru struct octeon_eth_softc *sc;
1580 1.1 hikaru int port;
1581 1.1 hikaru
1582 1.1 hikaru OCTEON_ETH_KASSERT(work != NULL);
1583 1.1 hikaru
1584 1.1 hikaru port = (work[1] & PIP_WQE_WORD1_IPRT) >> 42;
1585 1.1 hikaru
1586 1.1 hikaru OCTEON_ETH_KASSERT(port < GMX_PORT_NUNITS);
1587 1.1 hikaru
1588 1.1 hikaru sc = octeon_eth_gsc[port];
1589 1.1 hikaru
1590 1.1 hikaru OCTEON_ETH_KASSERT(sc != NULL);
1591 1.1 hikaru OCTEON_ETH_KASSERT(port == sc->sc_port);
1592 1.1 hikaru
1593 1.1 hikaru /* XXX process all work queue entries anyway */
1594 1.1 hikaru
1595 1.1 hikaru (void)octeon_eth_recv(sc, work);
1596 1.1 hikaru }
1597 1.1 hikaru
1598 1.1 hikaru /* ---- tick */
1599 1.1 hikaru
1600 1.1 hikaru /*
1601 1.1 hikaru * octeon_eth_tick_free
1602 1.1 hikaru *
1603 1.1 hikaru * => garbage collect send gather buffer / mbuf
1604 1.1 hikaru * => called at softclock
1605 1.1 hikaru */
1606 1.1 hikaru static void
1607 1.1 hikaru octeon_eth_tick_free(void *arg)
1608 1.1 hikaru {
1609 1.1 hikaru struct octeon_eth_softc *sc = arg;
1610 1.1 hikaru int timo;
1611 1.1 hikaru int s;
1612 1.1 hikaru
1613 1.1 hikaru s = splnet();
1614 1.1 hikaru /* XXX XXX XXX */
1615 1.1 hikaru if (sc->sc_soft_req_cnt > 0) {
1616 1.1 hikaru octeon_eth_send_queue_flush_prefetch(sc);
1617 1.1 hikaru octeon_eth_send_queue_flush_fetch(sc);
1618 1.1 hikaru octeon_eth_send_queue_flush(sc);
1619 1.1 hikaru octeon_eth_send_queue_flush_sync(sc);
1620 1.1 hikaru }
1621 1.1 hikaru /* XXX XXX XXX */
1622 1.1 hikaru
1623 1.1 hikaru /* XXX XXX XXX */
1624 1.1 hikaru /* ??? */
1625 1.1 hikaru timo = hz - (100 * sc->sc_ext_callback_cnt);
1626 1.1 hikaru if (timo < 10)
1627 1.1 hikaru timo = 10;
1628 1.1 hikaru callout_schedule(&sc->sc_tick_free_ch, timo);
1629 1.1 hikaru /* XXX XXX XXX */
1630 1.1 hikaru splx(s);
1631 1.1 hikaru }
1632 1.1 hikaru
1633 1.1 hikaru /*
1634 1.1 hikaru * octeon_eth_tick_misc
1635 1.1 hikaru *
1636 1.1 hikaru * => collect statistics
1637 1.1 hikaru * => check link status
1638 1.1 hikaru * => called at softclock
1639 1.1 hikaru */
1640 1.1 hikaru static void
1641 1.1 hikaru octeon_eth_tick_misc(void *arg)
1642 1.1 hikaru {
1643 1.1 hikaru struct octeon_eth_softc *sc = arg;
1644 1.1 hikaru struct ifnet *ifp;
1645 1.1 hikaru int s;
1646 1.1 hikaru
1647 1.1 hikaru s = splnet();
1648 1.1 hikaru
1649 1.1 hikaru ifp = &sc->sc_ethercom.ec_if;
1650 1.1 hikaru
1651 1.1 hikaru octeon_gmx_stats(sc->sc_gmx_port);
1652 1.1 hikaru octeon_pip_stats(sc->sc_pip, ifp, sc->sc_port);
1653 1.1 hikaru mii_tick(&sc->sc_mii);
1654 1.1 hikaru
1655 1.1 hikaru splx(s);
1656 1.1 hikaru
1657 1.1 hikaru callout_schedule(&sc->sc_tick_misc_ch, hz);
1658 1.1 hikaru }
1659 1.1 hikaru
1660 1.1 hikaru /* ---- odd nibble preamble workaround (software CRC processing) */
1661 1.1 hikaru
1662 1.1 hikaru /* ---- sysctl */
1663 1.1 hikaru
1664 1.1 hikaru static int octeon_eth_sysctl_verify(SYSCTLFN_ARGS);
1665 1.1 hikaru static int octeon_eth_sysctl_pool(SYSCTLFN_ARGS);
1666 1.1 hikaru static int octeon_eth_sysctl_rd(SYSCTLFN_ARGS);
1667 1.1 hikaru
1668 1.1 hikaru static int octeon_eth_sysctl_pkocmdw0n2_num;
1669 1.1 hikaru static int octeon_eth_sysctl_pipdynrs_num;
1670 1.1 hikaru static int octeon_eth_sysctl_redir_num;
1671 1.1 hikaru static int octeon_eth_sysctl_pkt_pool_num;
1672 1.1 hikaru static int octeon_eth_sysctl_wqe_pool_num;
1673 1.1 hikaru static int octeon_eth_sysctl_cmd_pool_num;
1674 1.1 hikaru static int octeon_eth_sysctl_sg_pool_num;
1675 1.1 hikaru static int octeon_eth_sysctl_pktbuf_num;
1676 1.1 hikaru
1677 1.1 hikaru /*
1678 1.1 hikaru * Set up sysctl(3) MIB, hw.cnmac.*.
1679 1.1 hikaru */
1680 1.1 hikaru SYSCTL_SETUP(sysctl_octeon_eth, "sysctl cnmac subtree setup")
1681 1.1 hikaru {
1682 1.1 hikaru int rc;
1683 1.1 hikaru int octeon_eth_sysctl_root_num;
1684 1.1 hikaru const struct sysctlnode *node;
1685 1.1 hikaru
1686 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, NULL,
1687 1.1 hikaru 0, CTLTYPE_NODE, "hw", NULL,
1688 1.1 hikaru NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) {
1689 1.1 hikaru goto err;
1690 1.1 hikaru }
1691 1.1 hikaru
1692 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, &node,
1693 1.1 hikaru 0, CTLTYPE_NODE, "cnmac",
1694 1.1 hikaru SYSCTL_DESCR("cnmac interface controls"),
1695 1.1 hikaru NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
1696 1.1 hikaru goto err;
1697 1.1 hikaru }
1698 1.1 hikaru
1699 1.1 hikaru octeon_eth_sysctl_root_num = node->sysctl_num;
1700 1.1 hikaru
1701 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, &node,
1702 1.1 hikaru CTLFLAG_PERMANENT | CTLFLAG_READWRITE,
1703 1.1 hikaru CTLTYPE_INT, "pko_cmd_w0_n2",
1704 1.1 hikaru SYSCTL_DESCR("PKO command WORD0 N2 bit"),
1705 1.1 hikaru octeon_eth_sysctl_verify, 0,
1706 1.1 hikaru &octeon_eth_param_pko_cmd_w0_n2,
1707 1.1 hikaru 0, CTL_HW, octeon_eth_sysctl_root_num, CTL_CREATE,
1708 1.1 hikaru CTL_EOL)) != 0) {
1709 1.1 hikaru goto err;
1710 1.1 hikaru }
1711 1.1 hikaru
1712 1.1 hikaru octeon_eth_sysctl_pkocmdw0n2_num = node->sysctl_num;
1713 1.1 hikaru
1714 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, &node,
1715 1.1 hikaru CTLFLAG_PERMANENT | CTLFLAG_READWRITE,
1716 1.1 hikaru CTLTYPE_INT, "pip_dyn_rs",
1717 1.1 hikaru SYSCTL_DESCR("PIP dynamic short in WQE"),
1718 1.1 hikaru octeon_eth_sysctl_verify, 0,
1719 1.1 hikaru &octeon_eth_param_pip_dyn_rs,
1720 1.1 hikaru 0, CTL_HW, octeon_eth_sysctl_root_num, CTL_CREATE,
1721 1.1 hikaru CTL_EOL)) != 0) {
1722 1.1 hikaru goto err;
1723 1.1 hikaru }
1724 1.1 hikaru
1725 1.1 hikaru octeon_eth_sysctl_pipdynrs_num = node->sysctl_num;
1726 1.1 hikaru
1727 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, &node,
1728 1.1 hikaru CTLFLAG_PERMANENT | CTLFLAG_READWRITE,
1729 1.1 hikaru CTLTYPE_INT, "redir",
1730 1.1 hikaru SYSCTL_DESCR("input port redirection"),
1731 1.1 hikaru octeon_eth_sysctl_verify, 0,
1732 1.1 hikaru &octeon_eth_param_redir,
1733 1.1 hikaru 0, CTL_HW, octeon_eth_sysctl_root_num, CTL_CREATE,
1734 1.1 hikaru CTL_EOL)) != 0) {
1735 1.1 hikaru goto err;
1736 1.1 hikaru }
1737 1.1 hikaru
1738 1.1 hikaru octeon_eth_sysctl_redir_num = node->sysctl_num;
1739 1.1 hikaru
1740 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, &node,
1741 1.1 hikaru CTLFLAG_PERMANENT,
1742 1.1 hikaru CTLTYPE_INT, "pkt_pool",
1743 1.1 hikaru SYSCTL_DESCR("packet pool available"),
1744 1.1 hikaru octeon_eth_sysctl_pool, 0, NULL,
1745 1.1 hikaru 0, CTL_HW, octeon_eth_sysctl_root_num, CTL_CREATE,
1746 1.1 hikaru CTL_EOL)) != 0) {
1747 1.1 hikaru goto err;
1748 1.1 hikaru }
1749 1.1 hikaru
1750 1.1 hikaru octeon_eth_sysctl_pkt_pool_num = node->sysctl_num;
1751 1.1 hikaru
1752 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, &node,
1753 1.1 hikaru CTLFLAG_PERMANENT,
1754 1.1 hikaru CTLTYPE_INT, "wqe_pool",
1755 1.1 hikaru SYSCTL_DESCR("wqe pool available"),
1756 1.1 hikaru octeon_eth_sysctl_pool, 0, NULL,
1757 1.1 hikaru 0, CTL_HW, octeon_eth_sysctl_root_num, CTL_CREATE,
1758 1.1 hikaru CTL_EOL)) != 0) {
1759 1.1 hikaru goto err;
1760 1.1 hikaru }
1761 1.1 hikaru
1762 1.1 hikaru octeon_eth_sysctl_wqe_pool_num = node->sysctl_num;
1763 1.1 hikaru
1764 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, &node,
1765 1.1 hikaru CTLFLAG_PERMANENT,
1766 1.1 hikaru CTLTYPE_INT, "cmd_pool",
1767 1.1 hikaru SYSCTL_DESCR("cmd pool available"),
1768 1.1 hikaru octeon_eth_sysctl_pool, 0, NULL,
1769 1.1 hikaru 0, CTL_HW, octeon_eth_sysctl_root_num, CTL_CREATE,
1770 1.1 hikaru CTL_EOL)) != 0) {
1771 1.1 hikaru goto err;
1772 1.1 hikaru }
1773 1.1 hikaru
1774 1.1 hikaru octeon_eth_sysctl_cmd_pool_num = node->sysctl_num;
1775 1.1 hikaru
1776 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, &node,
1777 1.1 hikaru CTLFLAG_PERMANENT,
1778 1.1 hikaru CTLTYPE_INT, "sg_pool",
1779 1.1 hikaru SYSCTL_DESCR("sg pool available"),
1780 1.1 hikaru octeon_eth_sysctl_pool, 0, NULL,
1781 1.1 hikaru 0, CTL_HW, octeon_eth_sysctl_root_num, CTL_CREATE,
1782 1.1 hikaru CTL_EOL)) != 0) {
1783 1.1 hikaru goto err;
1784 1.1 hikaru }
1785 1.1 hikaru
1786 1.1 hikaru octeon_eth_sysctl_sg_pool_num = node->sysctl_num;
1787 1.1 hikaru
1788 1.1 hikaru if ((rc = sysctl_createv(clog, 0, NULL, &node,
1789 1.1 hikaru CTLFLAG_PERMANENT | CTLFLAG_READONLY,
1790 1.1 hikaru CTLTYPE_INT, "pktbuf",
1791 1.1 hikaru SYSCTL_DESCR("input packet buffer size on POW"),
1792 1.1 hikaru octeon_eth_sysctl_rd, 0,
1793 1.1 hikaru &octeon_eth_param_pktbuf,
1794 1.1 hikaru 0, CTL_HW, octeon_eth_sysctl_root_num, CTL_CREATE,
1795 1.1 hikaru CTL_EOL)) != 0) {
1796 1.1 hikaru goto err;
1797 1.1 hikaru }
1798 1.1 hikaru
1799 1.1 hikaru octeon_eth_sysctl_pktbuf_num = node->sysctl_num;
1800 1.1 hikaru
1801 1.1 hikaru return;
1802 1.1 hikaru
1803 1.1 hikaru err:
1804 1.1 hikaru aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc);
1805 1.1 hikaru }
1806 1.1 hikaru
1807 1.1 hikaru static int
1808 1.1 hikaru octeon_eth_sysctl_verify(SYSCTLFN_ARGS)
1809 1.1 hikaru {
1810 1.1 hikaru int error, v;
1811 1.1 hikaru struct sysctlnode node;
1812 1.1 hikaru struct octeon_eth_softc *sc;
1813 1.1 hikaru int i;
1814 1.1 hikaru int s;
1815 1.1 hikaru
1816 1.1 hikaru node = *rnode;
1817 1.1 hikaru v = *(int *)rnode->sysctl_data;
1818 1.1 hikaru node.sysctl_data = &v;
1819 1.1 hikaru error = sysctl_lookup(SYSCTLFN_CALL(&node));
1820 1.1 hikaru if (error || newp == NULL)
1821 1.1 hikaru return error;
1822 1.1 hikaru
1823 1.1 hikaru if (node.sysctl_num == octeon_eth_sysctl_pkocmdw0n2_num) {
1824 1.1 hikaru if (v < 0 || v > 1)
1825 1.1 hikaru return EINVAL;
1826 1.1 hikaru *(int *)rnode->sysctl_data = v;
1827 1.1 hikaru return 0;
1828 1.1 hikaru }
1829 1.1 hikaru
1830 1.1 hikaru if (node.sysctl_num == octeon_eth_sysctl_pipdynrs_num) {
1831 1.1 hikaru if (v < 0 || v > 1)
1832 1.1 hikaru return EINVAL;
1833 1.1 hikaru *(int *)rnode->sysctl_data = v;
1834 1.1 hikaru s = splnet();
1835 1.1 hikaru for (i = 0; i < 3/* XXX */; i++) {
1836 1.1 hikaru sc = octeon_eth_gsc[i]; /* XXX */
1837 1.1 hikaru octeon_pip_prt_cfg_enable(sc->sc_pip, PIP_PRT_CFGN_DYN_RS, v);
1838 1.1 hikaru }
1839 1.1 hikaru splx(s);
1840 1.1 hikaru return 0;
1841 1.1 hikaru }
1842 1.1 hikaru
1843 1.1 hikaru if (node.sysctl_num == octeon_eth_sysctl_redir_num) {
1844 1.1 hikaru if (v & ~((0x7 << (4 * 0)) | (0x7 << (4 * 1)) | (0x7 << (4 * 2))))
1845 1.1 hikaru return EINVAL;
1846 1.1 hikaru *(int *)rnode->sysctl_data = v;
1847 1.1 hikaru s = splnet();
1848 1.1 hikaru for (i = 0; i < 3/* XXX */; i++) {
1849 1.1 hikaru struct ifnet *ifp;
1850 1.1 hikaru
1851 1.1 hikaru sc = octeon_eth_gsc[i]; /* XXX */
1852 1.1 hikaru ifp = &sc->sc_ethercom.ec_if;
1853 1.1 hikaru
1854 1.1 hikaru sc->sc_redir = (octeon_eth_param_redir >> (4 * i)) & 0x7;
1855 1.1 hikaru if (sc->sc_redir == 0) {
1856 1.1 hikaru if (ISSET(ifp->if_flags, IFF_PROMISC)) {
1857 1.1 hikaru CLR(ifp->if_flags, IFF_PROMISC);
1858 1.1 hikaru octeon_eth_mii_statchg(ifp);
1859 1.1 hikaru /* octeon_gmx_set_filter(sc->sc_gmx_port); */
1860 1.1 hikaru }
1861 1.2 ozaki ifp->_if_input = ether_input;
1862 1.1 hikaru }
1863 1.1 hikaru else {
1864 1.1 hikaru if (!ISSET(ifp->if_flags, IFF_PROMISC)) {
1865 1.1 hikaru SET(ifp->if_flags, IFF_PROMISC);
1866 1.1 hikaru octeon_eth_mii_statchg(ifp);
1867 1.1 hikaru /* octeon_gmx_set_filter(sc->sc_gmx_port); */
1868 1.1 hikaru }
1869 1.2 ozaki ifp->_if_input = octeon_eth_recv_redir;
1870 1.1 hikaru }
1871 1.1 hikaru }
1872 1.1 hikaru splx(s);
1873 1.1 hikaru return 0;
1874 1.1 hikaru }
1875 1.1 hikaru
1876 1.1 hikaru return EINVAL;
1877 1.1 hikaru }
1878 1.1 hikaru
1879 1.1 hikaru static int
1880 1.1 hikaru octeon_eth_sysctl_pool(SYSCTLFN_ARGS)
1881 1.1 hikaru {
1882 1.1 hikaru int error, newval = 0;
1883 1.1 hikaru struct sysctlnode node;
1884 1.1 hikaru int s;
1885 1.1 hikaru
1886 1.1 hikaru node = *rnode;
1887 1.1 hikaru node.sysctl_data = &newval;
1888 1.1 hikaru s = splnet();
1889 1.1 hikaru if (node.sysctl_num == octeon_eth_sysctl_pkt_pool_num) {
1890 1.1 hikaru error = octeon_fpa_available_fpa_pool(&newval, OCTEON_POOL_NO_PKT);
1891 1.1 hikaru } else if (node.sysctl_num == octeon_eth_sysctl_wqe_pool_num) {
1892 1.1 hikaru error = octeon_fpa_available_fpa_pool(&newval, OCTEON_POOL_NO_WQE);
1893 1.1 hikaru } else if (node.sysctl_num == octeon_eth_sysctl_cmd_pool_num) {
1894 1.1 hikaru error = octeon_fpa_available_fpa_pool(&newval, OCTEON_POOL_NO_CMD);
1895 1.1 hikaru } else if (node.sysctl_num == octeon_eth_sysctl_sg_pool_num) {
1896 1.1 hikaru error = octeon_fpa_available_fpa_pool(&newval, OCTEON_POOL_NO_SG);
1897 1.1 hikaru } else {
1898 1.1 hikaru splx(s);
1899 1.1 hikaru return EINVAL;
1900 1.1 hikaru }
1901 1.1 hikaru splx(s);
1902 1.1 hikaru if (error)
1903 1.1 hikaru return error;
1904 1.1 hikaru error = sysctl_lookup(SYSCTLFN_CALL(&node));
1905 1.1 hikaru if (error || newp == NULL)
1906 1.1 hikaru return error;
1907 1.1 hikaru
1908 1.1 hikaru return 0;
1909 1.1 hikaru }
1910 1.1 hikaru
1911 1.1 hikaru static int
1912 1.1 hikaru octeon_eth_sysctl_rd(SYSCTLFN_ARGS)
1913 1.1 hikaru {
1914 1.1 hikaru int error, v;
1915 1.1 hikaru struct sysctlnode node;
1916 1.1 hikaru int s;
1917 1.1 hikaru
1918 1.1 hikaru node = *rnode;
1919 1.1 hikaru v = *(int *)rnode->sysctl_data;
1920 1.1 hikaru node.sysctl_data = &v;
1921 1.1 hikaru error = sysctl_lookup(SYSCTLFN_CALL(&node));
1922 1.1 hikaru if (error || newp != NULL)
1923 1.1 hikaru return error;
1924 1.1 hikaru
1925 1.1 hikaru if (node.sysctl_num == octeon_eth_sysctl_pktbuf_num) {
1926 1.1 hikaru uint64_t tmp;
1927 1.1 hikaru int n;
1928 1.1 hikaru
1929 1.1 hikaru s = splnet();
1930 1.1 hikaru tmp = octeon_fpa_query(0);
1931 1.1 hikaru n = (int)tmp;
1932 1.1 hikaru splx(s);
1933 1.1 hikaru *(int *)rnode->sysctl_data = n;
1934 1.1 hikaru octeon_eth_param_pktbuf = n;
1935 1.1 hikaru *(int *)oldp = n;
1936 1.1 hikaru return 0;
1937 1.1 hikaru }
1938 1.1 hikaru
1939 1.1 hikaru return EINVAL;
1940 1.1 hikaru }
1941